Native RC Z180 & Interrupt Framework Improvements

- Added official support for Steve Cousin's RC2014 Z180 + Native Memory modules (SC111 & SC119).  Thanks to Steve for his assistance with this.
- Improved interrupt framework to remove need to extra stubs for each IM2 interrupt handler.

Source/CBIOS/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.13"
+#DEFINE BIOSVER	"2.9.1-pre.15"

Source/HBIOS/Build.ps1

@@ -28,8 +28,8 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
 $Platform = $Platform.ToUpper()
 while ($true)
 {
-	if (($Platform -eq "SBC") -or ($Platform -eq "ZETA") -or ($Platform -eq "ZETA2") -or ($Platform -eq "RC") -or ($Platform -eq "EZZ80") -or ($Platform -eq "RC180") -or ($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "UNA")) {break}
-	$Platform = (Read-Host -prompt "Platform [SBC|ZETA|ZETA2|RC|EZZ80|RC180|N8|MK4|UNA]").Trim().ToUpper()
+	if (($Platform -eq "SBC") -or ($Platform -eq "ZETA") -or ($Platform -eq "ZETA2") -or ($Platform -eq "RCZ80") -or ($Platform -eq "EZZ80") -or ($Platform -eq "RCZ180") -or ($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "UNA")) {break}
+	$Platform = (Read-Host -prompt "Platform [SBC|ZETA|ZETA2|RCZ80|EZZ80|RCZ180|N8|MK4|UNA]").Trim().ToUpper()
 }
 
 #
@@ -66,7 +66,7 @@ while ($true)
 # TASM should be invoked with the proper CPU type.  Below, the CPU type is inferred
 # from the platform.
 #
-if (($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "RC180")) {$CPUType = "180"} else {$CPUType = "80"}
+if (($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "RCZ180")) {$CPUType = "180"} else {$CPUType = "80"}
 
 #
 # The $RomName variable determines the name of the image created by the script.  By default,

Source/HBIOS/Config/RCZ180_ext.asm

@@ -0,0 +1,28 @@
+;
+;==================================================================================================
+;   RC2014 W/ Z180 CPU USING EXTERNAL MEMORY MANAGER -- 512K RAM/ROM MODULE
+;==================================================================================================
+;
+#include "cfg_rcz180.asm"
+;
+MEMMGR		.SET	MM_Z2		; 512K RAM/ROM MODULE MEM MGR
+Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
+Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ
+DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
+SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
+SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
+ACIAENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
+;
+FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
+FDMODE		.SET	FDMODE_RCWDC	; FDMODE_RCSMC, FDMODE_RCWDC
+;
+IDEENABLE	.SET	TRUE		; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
+IDEMODE		.SET	IDEMODE_RC	; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
+PPIDEENABLE	.SET	FALSE		; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
+;
+DSRTCENABLE	.SET	FALSE		; DS-1302 CLOCK DRIVER

Source/HBIOS/Config/RCZ180_nat.asm

@@ -1,9 +1,9 @@
 ;
 ;==================================================================================================
-;   RC2014 STANDARD CONFIGURATION
+;   RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER
 ;==================================================================================================
 ;
-#include "cfg_rc180.asm"
+#include "cfg_rcz180.asm"
 ;
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)

Source/HBIOS/Config/RCZ80_std.asm

@@ -3,7 +3,7 @@
 ;   RC2014 STANDARD CONFIGURATION
 ;==================================================================================================
 ;
-#include "cfg_rc.asm"
+#include "cfg_rcz80.asm"
 ;
 CPUOSC		.SET	7372800		; CPU OSC FREQ
 DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)

Source/HBIOS/ay.asm

@@ -75,7 +75,7 @@ AY_BEEP:
 ; 
 AY_WRTPSG:
 	HB_DI
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	IN0	A,(Z180_DCNTL)		; GET WAIT STATES
 	PUSH	AF			; SAVE VALUE
 	OR	%00110000		; FORCE SLOW OPERATION (I/O W/S=3)
@@ -85,7 +85,7 @@ AY_WRTPSG:
 	OUT	(AY_RSEL),A
 	LD	A,E
 	OUT	(AY_RDAT),A
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	POP	AF			; GET SAVED DCNTL VALUE
 	OUT0	(Z180_DCNTL),A		; AND RESTORE IT
 #ENDIF

Source/HBIOS/cfg_ezz80.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	10000000	; CPU OSC FREQ
+MEMMGR		.EQU	MM_Z2		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_mk4.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	18432000	; CPU OSC FREQ
+MEMMGR		.EQU	MM_Z180		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_n8.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	18432000	; CPU OSC FREQ
+MEMMGR		.EQU	MM_N8		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_rcz180.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	18432000	; CPU OSC FREQ
+MEMMGR		.EQU	MM_Z180		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_rcz80.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	7372800		; CPU OSC FREQ
+MEMMGR		.EQU	MM_Z2		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	1		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_sbc.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	8000000		; CPU OSC FREQ
+MEMMGR		.EQU	MM_SBC		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_zeta.asm

@@ -6,6 +6,7 @@
 ; BUILD CONFIGURATION OPTIONS
 ;
 CPUOSC		.EQU	20000000	; CPU OSC FREQ
+MEMMGR		.EQU	MM_SBC		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2

Source/HBIOS/cfg_zeta2.asm

@@ -7,6 +7,7 @@
 ;
 #INCLUDE "cfg_zeta.asm"			; USE ZETA CONFIG TO START
 ;
+MEMMGR		.SET	MM_Z2		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 INTMODE		.SET	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
 ;
 FDMODE		.SET	FDMODE_ZETA2	; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3

Source/HBIOS/hbios.asm

@@ -67,7 +67,7 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 ;
-#IF ((PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180))
 #DEFINE	DIAGP	$00
 #ENDIF
 ;
@@ -266,7 +266,8 @@ HBX_BNKSEL:
 ;
 HBX_BNKSEL_INT:
 ;
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
+;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA))
+#IF (MEMMGR == MM_SBC)
   #IF (INTMODE == 1)
 	; THIS BIT OF ABSURDITY HANDLES A RARE (BUT FATAL) SITUATION
 	; WHERE AN IM1 INTERRUPT OCCURS BETWEEN SETTING THE RAM AND
@@ -290,7 +291,8 @@ HBX_ROM:
 	OUT	(MPCL_ROM),A		; SET ROM PAGE SELECTOR
 	RET				; DONE
 #ENDIF
-#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180) | (PLATFORM == PLT_EZZ80))
+;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80))
+#IF (MEMMGR == MM_Z2)
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
@@ -304,7 +306,8 @@ HBX_ROM:
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
 	RET				; DONE
 #ENDIF
-#IF (PLATFORM == PLT_N8)
+;#IF (PLATFORM == PLT_N8)
+#IF (MEMMGR == MM_N8)
 	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
 	JR	Z,HBX_ROM		; IF NOT SET, SELECT ROM PAGE
 ;
@@ -327,7 +330,8 @@ HBX_ROM:
 	RET				; DONE
 ;
 #ENDIF
-#IF (PLATFORM == PLT_MK4)
+;#IF (PLATFORM == PLT_MK4)
+#IF (MEMMGR == MM_Z180)
 	RLCA				; RAM FLAG TO CARRY FLAG AND BIT 0
 	JR	NC,HBX_BNKSEL1		; IF NC, WANT ROM PAGE, SKIP AHEAD
 	XOR	%00100001		; SET BIT FOR HI 512K, CLR BIT 0
@@ -499,7 +503,7 @@ HBX_STACK	.EQU	$
 ; 15
 ; 16
 ;
-; #	RC		RC180		EZZ80
+; #	RCZ80		RCZ180		EZZ80
 ; ---	--------------	--------------	-------------
 ; 0	CTC0A		Z180/INT1	CTC0A/SIO0CLK
 ; 1	CTC0B		Z180/INT2	CTC0B/SIO1CLK
@@ -520,85 +524,103 @@ HBX_STACK	.EQU	$
 ; 16
 ;
 HBX_IVT:
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
-	.DW	INT_BAD
+	.DW	HBX_IV00
+	.DW	HBX_IV01
+	.DW	HBX_IV02
+	.DW	HBX_IV03
+	.DW	HBX_IV04
+	.DW	HBX_IV05
+	.DW	HBX_IV06
+	.DW	HBX_IV07
+	.DW	HBX_IV08
+	.DW	HBX_IV09
+	.DW	HBX_IV0A
+	.DW	HBX_IV0B
+	.DW	HBX_IV0C
+	.DW	HBX_IV0D
+	.DW	HBX_IV0E
+	.DW	HBX_IV0F
 ;
 HBX_IVTCNT	.EQU	($ - HBX_IVT) / 2
 ;
+HBX_IV00:	CALL HBX_INT \ .DB $00 << 2
+HBX_IV01:	CALL HBX_INT \ .DB $01 << 2
+HBX_IV02:	CALL HBX_INT \ .DB $02 << 2
+HBX_IV03:	CALL HBX_INT \ .DB $03 << 2
+HBX_IV04:	CALL HBX_INT \ .DB $04 << 2
+HBX_IV05:	CALL HBX_INT \ .DB $05 << 2
+HBX_IV06:	CALL HBX_INT \ .DB $06 << 2
+HBX_IV07:	CALL HBX_INT \ .DB $07 << 2
+HBX_IV08:	CALL HBX_INT \ .DB $08 << 2
+HBX_IV09:	CALL HBX_INT \ .DB $09 << 2
+HBX_IV0A:	CALL HBX_INT \ .DB $0A << 2
+HBX_IV0B:	CALL HBX_INT \ .DB $0B << 2
+HBX_IV0C:	CALL HBX_INT \ .DB $0C << 2
+HBX_IV0D:	CALL HBX_INT \ .DB $0D << 2
+HBX_IV0E:	CALL HBX_INT \ .DB $0E << 2
+HBX_IV0F:	CALL HBX_INT \ .DB $0F << 2
+;
 #ENDIF
 ;
+INT_IM1:
+#IF (INTMODE == 1)
+	CALL	HBX_INT
+	.DB	$00
+#ELSE
+	RETI				; UNEXPECTED INT, RET W/ INTS LEFT DISABLED
+#ENDIF
+;
+; *** INTERRUPT HANDLER STUBS ARE DEPRECATED!!!!
+; NO LONGER NEEDED NOR SUPPORTED
+; 
 ; INTERRUPT HANDLER STUBS
 ;
 ; THE FOLLOWING INTERRUPT STUBS RECEIVE CONTROL FROM THE
 ; INTERRUPT, SETUP A HANDLER VECTOR IN HBIOS AND THEN
 ; BRANCH TO THE COMMON INTERRUPT DISPATCHER
 ;
-;
-INT_IM1:
-#IF (INTMODE == 1)
-	PUSH	HL			; SAVE HL
-	LD	HL,HB_IM1INT		; HL := IM1 INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; TO TO ROUTING CODE
-#ELSE
-	RETI				; UNEXPECTED INT, RET W/ INTS LEFT DISABLED
-#ENDIF
-;
-#IF (INTMODE == 2)
-;
-INT_BAD:	; BAD INTERRUPT HANDLER
-	PUSH	HL			; SAVE HL
-	LD	HL,HB_BADINT		; HL := INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-;
-INT_TIMER:	; TIMER INTERRUPT HANDLER
-	PUSH	HL			; SAVE HL
-	LD	HL,HB_TIMINT		; HL := INT ADR IN BIOS
-	JR	HBX_INT			; GO TO ROUTING CODE
-;
-  #IF (SIOENABLE)
-INT_SIO:	; SIO INTERRUPT HANDLER
-	PUSH	HL			; SAVE HL
-	LD	HL,SIO_INT		; HL := SIO INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-  #ENDIF
-;
-#IF (PIO_ZP)
-INT_ZP0:	; PIO INTERRUPT HANDLER
-	PUSH	HL			; SAVE HL
-	LD	HL,PIO0INT		; HL := PIO INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-INT_ZP1
-	PUSH	HL			; SAVE HL
-	LD	HL,PIO1INT		; HL := PIO INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-#ENDIF
-;
-#IF (PIO_4P)
-INT_4P0:	; PIO INTERRUPT HANDLER
-	PUSH	HL			; SAVE HL
-	LD	HL,PIO2INT		; HL := PIO INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-INT_4P1:
-	PUSH	HL			; SAVE HL
-	LD	HL,PIO3INT		; HL := PIO INT HANDLER IN BIOS BANK
-	JR	HBX_INT			; GO TO ROUTING CODE
-#ENDIF
-;
-#ENDIF
+;#IF (INTMODE == 2)
+;;
+;INT_BAD:	; BAD INTERRUPT HANDLER
+;	PUSH	HL			; SAVE HL
+;	LD	HL,HB_BADINT		; HL := INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;;
+;INT_TIMER:	; TIMER INTERRUPT HANDLER
+;	PUSH	HL			; SAVE HL
+;	LD	HL,HB_TIMINT		; HL := INT ADR IN BIOS
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;;
+;  #IF (SIOENABLE)
+;INT_SIO:	; SIO INTERRUPT HANDLER
+;	PUSH	HL			; SAVE HL
+;	LD	HL,SIO_INT		; HL := SIO INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;  #ENDIF
+;;
+;#IF (PIO_ZP)
+;INT_ZP0:	; PIO INTERRUPT HANDLER
+;	PUSH	HL			; SAVE HL
+;	LD	HL,PIO0INT		; HL := PIO INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;INT_ZP1
+;	PUSH	HL			; SAVE HL
+;	LD	HL,PIO1INT		; HL := PIO INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;#ENDIF
+;;
+;#IF (PIO_4P)
+;INT_4P0:	; PIO INTERRUPT HANDLER
+;	PUSH	HL			; SAVE HL
+;	LD	HL,PIO2INT		; HL := PIO INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;INT_4P1:
+;	PUSH	HL			; SAVE HL
+;	LD	HL,PIO3INT		; HL := PIO INT HANDLER IN BIOS BANK
+;	JR	HBX_INT			; GO TO ROUTING CODE
+;#ENDIF
+;;
+;#ENDIF
 ;
 #IF (INTMODE > 0)
 ;
@@ -607,6 +629,8 @@ INT_4P1:
 ;
 HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 ;
+	EX	(SP),HL			; SAVE HL AND GET INT JP TABLE OFFSET
+
 	LD	(HBX_INT_SP),SP		; SAVE ORIGINAL STACK FRAME
 	LD	SP,HBX_STACK		; USE STACK FRAME IN HI MEM
 
@@ -619,7 +643,10 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 	LD	A,BID_BIOS		; HBIOS BANK
 	CALL	HBX_BNKSEL_INT		; SELECT IT
 
-	CALL	JPHL			; CALL INTERRUPT ROUTINE
+	LD	L,(HL)			; OFFSET INTO JP TABLE FOR THIS INT
+	LD	H,HB_IVT >> 8		; MSB OF HBIOS INT JP TABLE
+	
+	CALL	JPHL			; CALL HANDLER VIA INT JP TABLE
 
 	LD	A,(HB_CURBNK)		; GET PRE-INT BANK
 	CALL	HBX_BNKSEL		; SELECT IT
@@ -693,7 +720,73 @@ HB_STKSIZ	.EQU	HB_ENTRYTBL + 256 - $
 ;
 		.FILL	HB_STKSIZ,$FF	; USE REMAINDER OF PAGE FOR HBIOS STACK
 HB_STACK	.EQU	$		; TOP OF HBIOS STACK
-
+;
+;==================================================================================================
+;   INTERRUPT VECTOR TABLE (MUST START AT PAGE BOUNDARY!!!)
+;==================================================================================================
+;
+; IM1 INTERRUPTS ARRIVE HERE AFTER BANK SWITCH TO HBIOS BANK
+; LIST OF IM1 INT CALLS IS BUILT DYNAMICALLY BELOW
+; SEE HB_ADDIM1 ROUTINE
+; EACH ENTRY WILL LOOK LIKE:
+;	CALL	XXXX			; CALL INT HANDLER
+;	RET	NZ			; RETURN IF HANDLED
+;
+; NOTE THAT THE LIST IS INITIALLY FILLED WITH CALLS TO HB_BADINT.
+; AS THE TABLE IS POPULATED, THE ADDRESS OF HB_BADINT IS OVERLAID
+; WITH THE ADDRESS OF A REAL INTERRUPT HANDLER.
+;
+; THERE IS ROOM FOR 8 ENTRIES PLUS A FINAL CALL TO HB_BADINT.
+;
+#IF (INTMODE < 2)
+;
+HB_IVT:
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+	CALL HB_BADINT \ RET NZ
+;
+#ENDIF
+;
+; IM2 INTERRUPTS ARRIVE HERE AFTER BANK SWITCH TO HBIOS BANK
+; THE LIST OF JP TABLE ENTRIES MATCHES THE IM2 VECTORS ONE FOR
+; ONE.  ANY CALL TO THE PRIMARY IVT (HBX_IVT) WILL BE MAPPED TO
+; THE CORRESPONDING JP TABLE ENTRY BELOW AFTER THE BANK SWITCH.
+;
+; NOTE THAT THE LIST IS INITIALLY FILLED WITH CALLS TO HB_BADINT.
+; IT IS INTENDED THAT HARDWARE DRIVERS WILL DYNAMICALLY OVERLAY
+; THE ADDRESS PORTION OF THE APPROPRIATE JP TO POINT TO THE
+; DESIRED INTERRUPT HANDLER DURING THE DRIVERS INITIALIZATION.
+;
+; NOTE THAT EACH ENTRY HAS A FILLER BYTE OF VALUE ZERO.  THIS BYTE
+; HAS NO FUNCTION.  IT IS JUST USED TO MAKE ENTRIES AN EVEN 4 BYTES.
+;
+#IF (INTMODE == 2)
+;
+HB_IVT:
+HB_IVT00:	JP	HB_BADINT \ .DB 0
+HB_IVT01:	JP	HB_BADINT \ .DB 0
+HB_IVT02:	JP	HB_BADINT \ .DB 0
+HB_IVT03:	JP	HB_BADINT \ .DB 0
+HB_IVT04:	JP	HB_BADINT \ .DB 0
+HB_IVT05:	JP	HB_BADINT \ .DB 0
+HB_IVT06:	JP	HB_BADINT \ .DB 0
+HB_IVT07:	JP	HB_BADINT \ .DB 0
+HB_IVT08:	JP	HB_BADINT \ .DB 0
+HB_IVT09:	JP	HB_BADINT \ .DB 0
+HB_IVT0A:	JP	HB_BADINT \ .DB 0
+HB_IVT0B:	JP	HB_BADINT \ .DB 0
+HB_IVT0C:	JP	HB_BADINT \ .DB 0
+HB_IVT0D:	JP	HB_BADINT \ .DB 0
+HB_IVT0E:	JP	HB_BADINT \ .DB 0
+HB_IVT0F:	JP	HB_BADINT \ .DB 0
+;
+#ENDIF
 ;
 ;==================================================================================================
 ;   SYSTEM INITIALIZATION
@@ -710,7 +803,7 @@ HB_START:
 ;
 	LD	SP,HBX_LOC		; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	; SET BASE FOR CPU IO REGISTERS
 	LD	A,Z180_BASE
 	OUT0	(Z180_ICR),A
@@ -734,7 +827,8 @@ HB_START:
 	LD	A,$F0
 	OUT0	(Z180_DCNTL),A
 
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+;#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+#IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
 	; MMU SETUP
 	LD	A,$80
 	OUT0	(Z180_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
@@ -760,7 +854,8 @@ HB_START:
 
 #ENDIF
 ;
-#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180) | (PLATFORM == PLT_EZZ80))
+;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80))
+#IF (MEMMGR == MM_Z2)
 	; SET PAGING REGISTERS
 #IFDEF ROMBOOT
 	XOR	A
@@ -877,7 +972,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 ;
 	CALL	HB_CPUSPD		; CPU SPEED DETECTION
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 ;
 	; SET DESIRED WAIT STATES
 	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
@@ -980,7 +1075,7 @@ PSCNX	.EQU	$ + 1
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
 	LD	I,A			; ... AND PLACE IT IN I REGISTER
 
-  #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+  #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	; SETUP Z180 IVT
 	XOR	A			; SETUP LO BYTE OF IVT ADDRESS
 	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
@@ -999,7 +1094,7 @@ PSCNX	.EQU	$ + 1
     #ENDIF
 ;
     #IF (INTMODE == 2)
-	;LD	HL,INT_TIMER
+	;LD	HL,HB_TIMINT
 	;LD	(HBX_IVT),HL
     #ENDIF
 ;
@@ -1017,8 +1112,8 @@ PSCNX	.EQU	$ + 1
   #IF (INTMODE == 2)
 ;
 	; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT
-	LD	HL,INT_TIMER		; TIMER INT HANDLER ADR
-	LD	(HBX_IVT + 2),HL	; IVT SLOT 2
+	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
+	LD	(HB_IVT01 + 1),HL	; IVT INDEX 1
 ;
 	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
 	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
@@ -1072,8 +1167,8 @@ PSCNX	.EQU	$ + 1
   #IF (INTMODE == 2)
 ;
 	; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
-	LD	HL,INT_TIMER		; TIMER INT HANDLER ADR
-	LD	(HBX_IVT + 6),HL	; IVT SLOT 4
+	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
+	LD	(HB_IVT03 + 1),HL	; IVT INDEX 3
 ;
 	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
 	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
@@ -1117,7 +1212,7 @@ PSCNX	.EQU	$ + 1
 ;
 #ENDIF
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 ;
   #IF (INTMODE == 2)
 ;
@@ -1127,8 +1222,8 @@ PSCNX	.EQU	$ + 1
 	OUT0	(Z180_ITC),A		; WRITE TO INT/TRAP CONTROL REGISTER
 ;
 	; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
-	LD	HL,INT_TIMER
-	LD	(HBX_IVT + IVT_TIM0),HL
+	LD	HL,HB_TIMINT
+	LD	(HB_IVT02 + 1),HL	; IVT INDEX 3
 
 	; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
 	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
@@ -1158,7 +1253,7 @@ PSCNX	.EQU	$ + 1
 	LD	HL,(CB_CPUKHZ)
 	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
 	PRTS("MHz$")
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	CALL	PC_COMMA
 	PRTS(" IO=0x$")
 	LD	A,Z180_BASE
@@ -1170,7 +1265,7 @@ PSCNX	.EQU	$ + 1
 	;CALL	PRTSTRD
 	;.TEXT	", $"
 	CALL	NEWLINE
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	LD	A,Z180_MEMWAIT
 #ELSE
 	LD	A,0
@@ -1178,7 +1273,7 @@ PSCNX	.EQU	$ + 1
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" MEM W/S, $"
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	LD	A,Z180_IOWAIT + 1
 #ELSE
 	LD	A,1
@@ -1247,7 +1342,7 @@ INITSYS1:
 ; IF PLATFORM HAS A CONFIG JUMPER, CHECK TO SEE IF IT IS JUMPERED.
 ; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE)
 ;
-#IF ((PLATFORM != PLT_N8) & (PLATFORM != PLT_MK4) & (PLATFORM != PLT_RC) & (PLATFORM != PLT_RC180) & (PLATFORM != PLT_EZZ80))
+#IF ((PLATFORM != PLT_N8) & (PLATFORM != PLT_MK4) & (PLATFORM != PLT_RCZ80) & (PLATFORM != PLT_RCZ180) & (PLATFORM != PLT_EZZ80))
 	IN	A,(RTC)			; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER
 	BIT	6,A			; BIT 6 HAS CONFIG JUMPER STATE
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
@@ -1997,20 +2092,13 @@ SYS_INTVECADR:
 	OR	$FF
 	RET
 SYS_INTGET1:
-	OR	A
-	RLA				; HL := (A * 2) FOR IM2
-#IF (INTMODE == 1)
-	RLA				; ... HL := (A * 4) + 1 FOR IM1
-	INC	A
-#ENDIF
+	OR	A			; CLEAR CARRY
+	RLA				; ADJUST FOR TABLE ENTRY
+	RLA				; SIZE OF 4 BYTES
+	INC	A			; BUMP TO ADR FIELD
 	LD	H,0
 	LD	L,A
-#IF (INTMODE == 1)
-	LD	DE,HB_IM1INT		; DE := START OF CALL LIST
-#ENDIF
-#IF (INTMODE == 2)
-	LD	DE,HBX_IVT		; DE := START OF VECTOR TABLE
-#ENDIF
+	LD	DE,HB_IVT		; DE := START OF VECTOR TABLE
 	ADD	HL,DE			; HL := ADR OF VECTOR
 	XOR	A			; INDICATE SUCCESS
 	RET
@@ -2052,9 +2140,9 @@ SYS_INTSET1:
 	INC	HL
 	LD	(HL),B			; SAVE MSB
 	EX	DE,HL			; HL := PREV VEC
-#IF (INTMODE == 2)
-	LD	DE,HBX_INT		; DE := IM2 INT ROUTING ENGINE
-#ENDIF
+;#IF (INTMODE == 2)
+;	LD	DE,HBX_INT		; DE := IM2 INT ROUTING ENGINE
+;#ENDIF
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
 ;
@@ -2076,30 +2164,6 @@ CIO_IDLE:
 ;
 #IF (INTMODE == 1)
 ;
-; IM1 INTERRUPTS ARRIVE HERE AFTER BANK SWITCH TO HBIOS BANK
-; LIST OF IM1 INT CALLS IS BUILT DYNAMICALLY BELOW
-; SEE HB_ADDIM1 ROUTINE
-; EACH ENTRY WILL LOOK LIKE:
-;	CALL	XXXX			; CALL INT HANDLER
-;	RET	NZ			; RETURN IF HANDLED
-;
-; NOTE THAT THE LIST IS INITIALLY FILLED WITH CALLS TO HB_BADINT.
-; AS THE TABLE IS POPULATED, THE ADDRESS OF HB_BADINT IS OVERLAID
-; WITH THE ADDRESS OF A REAL INTERRUPT HANDLER.
-;
-; THERE IS ROOM FOR 8 ENTRIES PLUS A FINAL CALL TO HB_BADINT.
-;
-HB_IM1INT:	; IM1 DEVICE INTERRUPT HANDLER CALL LIST
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-	CALL HB_BADINT \ RET NZ
-;
 ; ROUTINE BELOW IS USED TO ADD A NEW VECTOR TO THE IM1
 ; CALL LIST ABOVE.  ENTER WITH HL=VECTOR ADDRESS IN HBIOS
 ;
@@ -2119,7 +2183,7 @@ HB_ADDIM1:
 ;
 HB_IM1CNT	.DB	0		; NUMBER OF ENTRIES IN CALL LIST
 HB_IM1MAX	.DB	8		; MAX ENTRIES IN CALL LIST
-HB_IM1PTR	.DW	HB_IM1INT	; POINTER FOR NEXT IM1 ENTRY
+HB_IM1PTR	.DW	HB_IVT		; POINTER FOR NEXT IM1 ENTRY
 ;
 #ENDIF
 ;
@@ -2158,7 +2222,7 @@ TEMPCNT	.DB	250
 ;
 HB_TIMINT2:
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	; ACK/RESET Z180 TIMER INTERRUPT
 	IN0	A,(Z180_TCR)
 	IN0	A,(Z180_TMDR0L)
@@ -2187,7 +2251,13 @@ HB_BADINTCNT	.DB	0
 #ENDIF	; *DEBUG*
 
 	CALL	NEWLINE2
-	PRTS("+++ BAD INT: $")
+	PRTS("+++ BAD INT $")
+	LD	A,L
+	RRCA
+	RRCA
+	CALL PRTHEXBYTE
+	PRTS("H: $")
+	
 	CALL	_REGDMP
 	;CALL	CONTINUE
 	OR	$FF			; SIGNAL INTERRUPT HANDLED
@@ -2653,7 +2723,7 @@ HB_CPUSPD1:
 ;
 	; TIMES 4 FOR CPU SPEED IN KHZ
 	RES	0,L			; GRANULARITY
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	SLA	L
 	RL	H
 #ENDIF
@@ -2675,7 +2745,7 @@ HB_WAITSEC:
 	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_EZZ80))
+#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_EZZ80))
 	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY32
 	CALL	DLY8
@@ -2691,7 +2761,7 @@ HB_WAITSEC1:
 	NOP				; 4 TSTATES
 #ENDIF
 
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	; LOOP TARGET IS 8000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 8
 	;CALL	DLY64
 	CALL	DLY32

Source/HBIOS/pio.asm

@@ -128,7 +128,8 @@ PIO_PREINIT2:
 #IF (INTMODE == 2)
 	; SETUP PIO INTERRUPT VECTOR IN IVT
 	LD	HL,PIO0INT
-	LD	(HBX_IVT + IVT_PIO0),HL
+;	LD	(HBX_IVT + IVT_PIO0),HL
+	LD	(HB_IVT09 + 1),HL	; WW: IVT INDEX 9 FOR PIO0
 #ENDIF
 PIO_PREINIT3:
 	XOR	A			; SIGNAL SUCCESS

Source/HBIOS/plt_rcz180.inc

@@ -1,6 +1,8 @@
 ;
 ; RC2014 Z180 HARDWARE DEFINITIONS
 ;
+RAMBIAS		.EQU	512		; RAM STARTS AT 512K
+;
 MPGSEL_0	.EQU	$78		; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)

Source/HBIOS/sio.asm

@@ -100,8 +100,8 @@ SIO_PREINIT2:
 ;
 #IF (INTMODE == 2)
 	; SETUP SIO INTERRUPT VECTOR IN IVT
-	LD	HL,INT_SIO
-	LD	(HBX_IVT + IVT_SER0),HL
+	LD	HL,SIO_INT
+	LD	(HB_IVT07 + 1),HL	; IVT INDEX 7
 #ENDIF
 ;
 SIO_PREINIT3:

Source/HBIOS/std.asm

@@ -8,7 +8,9 @@
 ; 4. N8		MSX-compatible Z180 SBC w/ onboard video and sound
 ; 5. MK4	Mark IV Z180 based SBC w/ ECB interface
 ; 6. UNA	Any Z80/Z180 computer with UNA BIOS
-; 7. RC		RC2014 based system with SMB 512K RAM/ROM card
+; 7. RCZ80	RC2014 based system with 512K banked RAM/ROM card
+; 8. RCZ180	RC2014 based system with Z180 CPU
+; 9. EZZ80	Easy Z80, Z80 SBC w/ RC2014 bus and CTC
 
 ; All the classes require certain generic definitions, and these are
 ; defined here prior to the inclusion of platform specific .inc files.
@@ -33,14 +35,22 @@ PLT_ZETA2	.EQU	3		; ZETA Z80 V2 SBC
 PLT_N8		.EQU	4		; N8 (HOME COMPUTER) Z180 SBC
 PLT_MK4		.EQU	5		; MARK IV
 PLT_UNA		.EQU	6		; UNA BIOS
-PLT_RC		.EQU	7		; RC2014
-PLT_RC180	.EQU	8		; RC2014 W/ Z180
+PLT_RCZ80	.EQU	7		; RC2014 W Z80
+PLT_RCZ180	.EQU	8		; RC2014 W/ Z180
 PLT_EZZ80	.EQU	9		; EASY Z80
 ;
 #IF (PLATFORM != PLT_UNA)
 #INCLUDE "hbios.inc"
 #ENDIF
 ;
+; MEMORY MANAGERS
+;
+MM_NONE		.EQU	0
+MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
+MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
+MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
+MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
+;
 ; BOOT STYLE
 ;
 BT_MENU		.EQU	1		; WAIT FOR MENU SELECTION AT LOADER PROMPT
@@ -245,7 +255,7 @@ IVT_PIO3	.EQU	24
 ;
 #INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 #DEFINE CPU_Z180
 #ELSE
 #DEFINE CPU_Z80
@@ -271,10 +281,10 @@ IVT_PIO3	.EQU	24
 #IF (PLATFORM == PLT_UNA)
   #DEFINE	PLATFORM_NAME	"UNA"
 #ENDIF
-#IF (PLATFORM == PLT_RC)
+#IF (PLATFORM == PLT_RCZ80)
   #DEFINE	PLATFORM_NAME	"RC2014 Z80"
 #ENDIF
-#IF (PLATFORM == PLT_RC180)
+#IF (PLATFORM == PLT_RCZ180)
   #DEFINE	PLATFORM_NAME	"RC2014 Z180"
 #ENDIF
 #IF (PLATFORM == PLT_EZZ80)
@@ -307,12 +317,12 @@ IVT_PIO3	.EQU	24
 #INCLUDE "plt_una.inc"
 #ENDIF
 ;
-#IF (PLATFORM == PLT_RC)
-#INCLUDE "plt_rc.inc"
+#IF (PLATFORM == PLT_RCZ80)
+#INCLUDE "plt_rcz80.inc"
 #ENDIF
 ;
-#IF (PLATFORM == PLT_RC180)
-#INCLUDE "plt_rc180.inc"
+#IF (PLATFORM == PLT_RCZ180)
+#INCLUDE "plt_rcz180.inc"
 #ENDIF
 ;
 #IF (PLATFORM == PLT_EZZ80)

Source/HBIOS/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.13"
+#DEFINE BIOSVER	"2.9.1-pre.15"