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Merge pull request #10 from b1ackmai1er/master

Add startup beep support for SBC V2 using PSG on TMS or bit port on SBC RTC
pull/11/merge
Wayne Warthen 8 years ago
committed by GitHub
parent
commit
b084b075e6
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
  1. 1
      Source/HBIOS/cfg_mk4.asm
  2. 1
      Source/HBIOS/cfg_n8.asm
  3. 13
      Source/HBIOS/cfg_rc.asm
  4. 1
      Source/HBIOS/cfg_rc180.asm
  5. 17
      Source/HBIOS/cfg_sbc.asm
  6. 1
      Source/HBIOS/cfg_zeta.asm
  7. 13
      Source/HBIOS/hbios.asm
  8. 131
      Source/HBIOS/sound.asm
  9. 86
      Source/HBIOS/std.asm

1
Source/HBIOS/cfg_mk4.asm

@ -32,6 +32,7 @@ CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU FALSE ; TRUE FOR PSG OR IOBIT SOUND
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

1
Source/HBIOS/cfg_n8.asm

@ -32,6 +32,7 @@ CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU TRUE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU TRUE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU FALSE ; TRUE FOR PSG OR IOBIT SOUND
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

13
Source/HBIOS/cfg_rc.asm

@ -25,12 +25,12 @@ UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TR
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU TRUE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ACIAENABLE .EQU TRUE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
; ;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT ;PS
SIOMODE .EQU SIOMODE_RC ; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP ;PS
DEFSIOACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ;PS
DEFSIOBCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ;PS
DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 ;PS
DEFSIOCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY ;PS
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT
SIOMODE .EQU SIOMODE_RC ; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP
DEFSIOACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
DEFSIOBCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG
DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
DEFSIOCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIODEBUG .EQU FALSE ;PS SIODEBUG .EQU FALSE ;PS
; ;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
@ -38,6 +38,7 @@ CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU FALSE ; TRUE FOR PSG OR IOBIT SOUND
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

1
Source/HBIOS/cfg_rc180.asm

@ -32,6 +32,7 @@ CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU FALSE ; TRUE FOR PSG OR IOBIT SOUND
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

17
Source/HBIOS/cfg_sbc.asm

@ -25,19 +25,22 @@ UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRU
UARTOSC .EQU 1843200 ; UART OSC FREQUENCY UARTOSC .EQU 1843200 ; UART OSC FREQUENCY
ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
; ;
SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT ;PS
SIOMODE .EQU SIOMODE_ZP ; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP ;PS
DEFSIOACFG .EQU SER_9600_8N1 ; DEFAULT SERIAL LINE CONFIG ;PS
DEFSIOBCFG .EQU SER_9600_8N1 ; DEFAULT SERIAL LINE CONFIG ;PS
DEFSIODIV .EQU 8 ; 1=RC2014, SMB, 2/4/8/16/32/64/128/256 for ZP depending on jumper X5 ;PS
DEFSIOCLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY ;PS
SIODEBUG .EQU TRUE ;PS
SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO SUPPORT
SIOMODE .EQU SIOMODE_ZP ; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP
DEFSIOACFG .EQU SER_9600_8N1 ; DEFAULT SERIAL LINE CONFIG
DEFSIOBCFG .EQU SER_9600_8N1 ; DEFAULT SERIAL LINE CONFIG
DEFSIODIV .EQU 8 ; 1=RC2014, SMB, 2/4/8/16/32/64/128/256 for ZP depending on jumper X5
DEFSIOCLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
SIODEBUG .EQU FALSE ;
; ;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU TRUE ; TRUE FOR PSG OR IOBIT SOUND
CONBELL .EQU CONBELL_PSG ; CONBELL_IOBIT / CONBELL_PSG
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

1
Source/HBIOS/cfg_zeta.asm

@ -32,6 +32,7 @@ CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT
SNDENABLE .EQU FALSE ; TRUE FOR PSG OR IOBIT SOUND
; ;
MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)

13
Source/HBIOS/hbios.asm

@ -1135,6 +1135,9 @@ INITSYS3:
;================================================================================================== ;==================================================================================================
; ;
HB_INITTBL: HB_INITTBL:
#IF (SNDENABLE)
.DW SND_INIT ; AUDIBLE INDICATOR OF BOOT START
#ENDIF
#IF (ASCIENABLE) #IF (ASCIENABLE)
.DW ASCI_INIT .DW ASCI_INIT
#ENDIF #ENDIF
@ -2227,6 +2230,16 @@ SIZ_TERM .EQU $ - ORG_TERM
.ECHO SIZ_TERM .ECHO SIZ_TERM
.ECHO " bytes.\n" .ECHO " bytes.\n"
#ENDIF #ENDIF
;
#IF (SNDENABLE)
ORG_SND .EQU $
#INCLUDE "sound.asm"
SIZ_SND .EQU $ - ORG_SND
.ECHO "SND occupies "
.ECHO SIZ_SND
.ECHO " bytes.\n"
#ENDIF
; ;
#DEFINE USEDELAY #DEFINE USEDELAY
#INCLUDE "util.asm" #INCLUDE "util.asm"

131
Source/HBIOS/sound.asm

@ -0,0 +1,131 @@
;
;======================================================================
; PSG AY-3-8910 DRIVER FOR CONSOLE BELL
;======================================================================
;
#IF (CONBELL == CONBELL_PSG)
PSG_RSEL .EQU $9A
PSG_RDAT .EQU $9B
PSG_ACR .EQU $9C
AYR0CHAP .EQU $00
AYR1CHAP .EQU $01
AYR2CHBP .EQU $02
AYR3CHBP .EQU $03
AYR7ENAB .EQU $07
AYR8AVOL .EQU $08
AYR9BVOL .EQU $09
;
;======================================================================
; PSG AY-3-8910 DRIVER - INITIALIZATION
;======================================================================
;
SND_INIT:
CALL NEWLINE ; FORMATTING
PRTS("PSG: IO=0x$")
LD A,PSG_RSEL
CALL PRTHEXBYTE
CALL PSG_PROBE ; CHECK FOR HW EXISTENCE
JR Z,PSG_INIT1 ; CONTINUE IF PRESENT
;
; HARDWARE NOT PRESENT
;
PRTS(" NOT PRESENT$")
OR $FF ; SIGNAL FAILURE
RET
;
PSG_INIT1:
CALL PSG_INIT2
CALL BEEP
PSG_INIT2:
LD A,AYR7ENAB ; SET MIXER CONTROL / IO ENABLE
LD E,$FF ; $FF - 11 111 111
CALL WRTPSG ; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A DISABLE
;
LD B,2
LD A,AYR8AVOL ; SET VOLUME TO 0
LD E,$00
AYQUIET:
CALL WRTPSG ; CYCLING THROUGH ALL CHANNELS
INC A
DJNZ AYQUIET
RET
;
; PLAY A BEEP TONE ON CENTER CHANNEL (LEFT AND RIGHT SPEAKERS)
;
BEEP:
LD A,AYR2CHBP ; SET TONE PERIOD
LD E,$55 ; CHANNEL B - R00 & R01
CALL WRTPSG ; $0055 = XXXX0000 01010101
LD E,0
LD A,AYR3CHBP
CALL WRTPSG
;
LD E,$FD ; SET MIXER CONTROL / IO ENABLE
LD A,AYR7ENAB ; $FD = 11 111 101
CALL WRTPSG ; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL B ENABLE
;
LD E,$07 ; SET CHANNEL B VOLUME TO 50% (7/16)
LD A,AYR9BVOL ;
CALL WRTPSG
;
CALL LDELAY ; HALF SECOND
RET
;
; WRITE DATA E TO PSG REG A
;
WRTPSG:
HB_DI
OUT (PSG_RSEL),A
PUSH AF
LD A,E
OUT (PSG_RDAT),A
HB_EI
POP AF
RET
;
; CHECK THERE IS A DEVICE PRESENT
;
PSG_PROBE:
LD A,$FF
OUT (PSG_ACR),A ; INIT AUX CONTROL REG
XOR A
RET
;
#ENDIF
;
;======================================================================
; I/O BIT DRIVER FOR CONSOLE BELL FOR SBC V2 USING BIT 0 OF RTC DRIVER
;======================================================================
;
#IF (CONBELL == CONBELL_IOBIT)
SND_INIT:
CALL NEWLINE ; FORMATTING
PRTS("SND: IO=0x$")
LD A,DSRTC_BASE
CALL PRTHEXBYTE
CALL BEEP
XOR A
RET
BEEP:
PUSH DE
PUSH HL
LD HL,400 ; Cycles of tone
LD B,%00000100 ; D2 mapped to Q0
BEEP1:
LD A,B
OUT (DSRTC_BASE),A
XOR %00000100
LD B,A
LD DE,17
CALL VDELAY
DEC HL
LD A,H
OR L
JR NZ,BEEP1
POP HL
POP DE
RET
#ENDIF

86
Source/HBIOS/std.asm

@ -79,6 +79,12 @@ SIOMODE_RC .EQU 1 ; RC2014 SIO MODULE (SPENCER OWEN)
SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE (SCOTT BAKER) SIOMODE_SMB .EQU 2 ; RC2014 SIO MODULE (SCOTT BAKER)
SIOMODE_ZP .EQU 3 ; ZILOG PERIPHERALS BOARD SIOMODE_ZP .EQU 3 ; ZILOG PERIPHERALS BOARD
; ;
; TYPE OF CONSOLE BELL TO USE
;
CONBELL_NONE .EQU 0
CONBELL_PSG .EQU 1
CONBELL_IOBIT .EQU 2
;
; FD MODE SELECTIONS ; FD MODE SELECTIONS
; ;
FDMODE_NONE .EQU 0 FDMODE_NONE .EQU 0
@ -140,8 +146,8 @@ SER_STOP2 .EQU 1 << 2
; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y ; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
; AND STORED AS 5 BITS: YXXXX ; AND STORED AS 5 BITS: YXXXX
; ;
SER_BAUD75 .EQU $00 << 8 ;PS
SER_BAUD150 .EQU $01 << 8 ;PS
SER_BAUD75 .EQU $00 << 8
SER_BAUD150 .EQU $01 << 8
SER_BAUD300 .EQU $02 << 8 SER_BAUD300 .EQU $02 << 8
SER_BAUD600 .EQU $03 << 8 SER_BAUD600 .EQU $03 << 8
SER_BAUD1200 .EQU $04 << 8 SER_BAUD1200 .EQU $04 << 8
@ -151,35 +157,35 @@ SER_BAUD9600 .EQU $07 << 8
SER_BAUD19200 .EQU $08 << 8 SER_BAUD19200 .EQU $08 << 8
SER_BAUD38400 .EQU $09 << 8 SER_BAUD38400 .EQU $09 << 8
SER_BAUD76800 .EQU $0A << 8 SER_BAUD76800 .EQU $0A << 8
SER_BAUD153600 .EQU $0B << 8 ;PS
SER_BAUD307200 .EQU $0C << 8 ;PS
SER_BAUD614400 .EQU $0D << 8 ;PS
SER_BAUD1228800 .EQU $0E << 8 ;PS
SER_BAUD2457600 .EQU $0F << 8 ;PS
SER_BAUD225 .EQU $10 << 8 ;PS
SER_BAUD450 .EQU $11 << 8 ;PS
SER_BAUD900 .EQU $12 << 8 ;PS
SER_BAUD1800 .EQU $13 << 8 ;PS
SER_BAUD3600 .EQU $14 << 8 ;PS
SER_BAUD7200 .EQU $15 << 8 ;PS
SER_BAUD14400 .EQU $16 << 8 ;PS
SER_BAUD28800 .EQU $17 << 8 ;PS
SER_BAUD57600 .EQU $18 << 8 ;PS
SER_BAUD153600 .EQU $0B << 8
SER_BAUD307200 .EQU $0C << 8
SER_BAUD614400 .EQU $0D << 8
SER_BAUD1228800 .EQU $0E << 8
SER_BAUD2457600 .EQU $0F << 8
SER_BAUD225 .EQU $10 << 8
SER_BAUD450 .EQU $11 << 8
SER_BAUD900 .EQU $12 << 8
SER_BAUD1800 .EQU $13 << 8
SER_BAUD3600 .EQU $14 << 8
SER_BAUD7200 .EQU $15 << 8
SER_BAUD14400 .EQU $16 << 8
SER_BAUD28800 .EQU $17 << 8
SER_BAUD57600 .EQU $18 << 8
SER_BAUD115200 .EQU $19 << 8 SER_BAUD115200 .EQU $19 << 8
SER_BAUD230400 .EQU $1A << 8 SER_BAUD230400 .EQU $1A << 8
SER_BAUD460800 .EQU $1B << 8 SER_BAUD460800 .EQU $1B << 8
SER_BAUD921600 .EQU $1C << 8 ;PS
SER_BAUD1843200 .EQU $1D << 8 ;PS
SER_BAUD3686400 .EQU $1E << 8 ;PS
SER_BAUD7372800 .EQU $1F << 8 ;PS
SER_BAUD921600 .EQU $1C << 8
SER_BAUD1843200 .EQU $1D << 8
SER_BAUD3686400 .EQU $1E << 8
SER_BAUD7372800 .EQU $1F << 8
; ;
SER_XON .EQU 1 << 6 SER_XON .EQU 1 << 6
SER_DTR .EQU 1 << 7 SER_DTR .EQU 1 << 7
SER_RTS .EQU 1 << 13 SER_RTS .EQU 1 << 13
; ;
SER_75_8N1 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_150_8N1 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_75_8N1 .EQU SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_150_8N1 .EQU SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_300_8N1 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_300_8N1 .EQU SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_600_8N1 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_600_8N1 .EQU SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_1200_8N1 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_1200_8N1 .EQU SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
@ -189,27 +195,27 @@ SER_9600_8N1 .EQU SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_19200_8N1 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_19200_8N1 .EQU SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_38400_8N1 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_38400_8N1 .EQU SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_76800_8N1 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_76800_8N1 .EQU SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_153600_8N1 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_307200_8N1 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_614400_8N1 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_1228800_8N1 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_2457600_8N1 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_225_8N1 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_450_8N1 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_900_8N1 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_1800_8N1 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_3600_8N1 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_7200_8N1 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_14400_8N1 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_28800_8N1 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_57600_8N1 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_153600_8N1 .EQU SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_307200_8N1 .EQU SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_614400_8N1 .EQU SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_1228800_8N1 .EQU SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_2457600_8N1 .EQU SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_225_8N1 .EQU SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_450_8N1 .EQU SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_900_8N1 .EQU SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_1800_8N1 .EQU SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_3600_8N1 .EQU SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_7200_8N1 .EQU SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_14400_8N1 .EQU SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_28800_8N1 .EQU SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_57600_8N1 .EQU SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_115200_8N1 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_115200_8N1 .EQU SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_230400_8N1 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_230400_8N1 .EQU SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_460800_8N1 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1 SER_460800_8N1 .EQU SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_921600_8N1 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1 ;PS
SER_921600_8N1 .EQU SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_1843200_8N1 .EQU SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_3686400_8N1 .EQU SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1
SER_7372800_8N1 .EQU SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1
; ;
; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE) ; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE)
; ;

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