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Merge pull request #23 from wwarthen/master

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Cleanup
This commit is contained in:
b1ackmai1er
2019-10-07 12:22:26 +08:00
committed by GitHub
parent 98bec91318 782bcba9f7
commit b498f5a744
17 changed files with 39 additions and 18 deletions
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2
Source/CBIOS/ver.inc
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@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.13"
#DEFINE BIOSVER "2.9.2-pre.14"

4
Source/HBIOS/Config/EZZ80_std.asm
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@@ -25,4 +25,6 @@
#include "cfg_ezz80.asm"
;
CPUOSC .SET 10000000 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
;SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
;SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG

3
Source/HBIOS/Config/RCZ180_ext.asm
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@@ -33,6 +33,9 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

3
Source/HBIOS/Config/RCZ180_nat.asm
View File

@@ -33,6 +33,9 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

3
Source/HBIOS/Config/RCZ80_kio.asm
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@@ -34,12 +34,15 @@ CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIO0MODE .SET SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
;SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
;SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]

6
Source/HBIOS/Config/RCZ80_std.asm
View File

@@ -25,10 +25,14 @@
#include "cfg_rcz80.asm"
;
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;ACIA0CFG .SET SER_115200_8N1 ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
;ACIA1CFG .SET SER_115200_8N1 ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
;
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
;SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]

3
Source/HBIOS/Config/SCZ180_126.asm
View File

@@ -33,6 +33,9 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

3
Source/HBIOS/Config/SCZ180_130.asm
View File

@@ -35,6 +35,9 @@ Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

4
Source/HBIOS/acia.asm
View File

@@ -691,7 +691,7 @@ ACIA0_CFG:
.DB 0 ; ACIA TYPE (SET DURING INIT)
.DB 0 ; MODULE ID
.DB ACIA0BASE ; BASE PORT
.DW DEFSERCFG ; LINE CONFIGURATION
.DW ACIA0CFG ; LINE CONFIGURATION
.DW ACIA0_RCVBUF ; POINTER TO RCV BUFFER STRUCT
.DW ACIA0_INT ; INT HANDLER POINTER
.DW (ACIA0CLK / ACIA0DIV) & $FFFF ; CLOCK FREQ AS
@@ -707,7 +707,7 @@ ACIA1_CFG:
.DB 0 ; ACIA TYPE (SET DURING INIT)
.DB 1 ; MODULE ID
.DB ACIA1BASE ; BASE PORT
.DW DEFSERCFG ; LINE CONFIGURATION
.DW ACIA1CFG ; LINE CONFIGURATION
.DW ACIA1_RCVBUF ; POINTER TO RCV BUFFER STRUCT
.DW ACIA1_INT ; INT HANDLER POINTER
.DW (ACIA1CLK / ACIA1DIV) & $FFFF ; CLOCK FREQ AS

4
Source/HBIOS/cfg_ezz80.asm
View File

@@ -77,7 +77,7 @@ SIO0MODE .EQU SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
@@ -85,7 +85,7 @@ SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_master.asm
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@@ -116,7 +116,7 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
@@ -124,7 +124,7 @@ SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_rcz180.asm
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@@ -83,7 +83,7 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU SER_115200_8N1 ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
@@ -91,7 +91,7 @@ SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU SER_115200_8N1 ; AIO 1A: SERIAL LINE CONFIG
SIO1ACFG .EQU SER_115200_8N1 ; SER_115200_8N1 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_rcz80.asm
View File

@@ -86,7 +86,7 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
@@ -94,7 +94,7 @@ SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU DEFSERCFG ; AIO 1A: SERIAL LINE CONFIG
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG

2
Source/HBIOS/cfg_sbc.asm
View File

@@ -82,7 +82,7 @@ SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 4915200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 8 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU DEFSERCFG ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 4915200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 8 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_scz180.asm
View File

@@ -78,7 +78,7 @@ SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0ACFG .EQU SER_115200_8N1 ; AIO 0A: SERIAL LINE CONFIG
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
@@ -86,7 +86,7 @@ SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1ACFG .EQU SER_115200_8N1 ; AIO 1A: SERIAL LINE CONFIG
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG

2
Source/HBIOS/ver.inc
View File

@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.13"
#DEFINE BIOSVER "2.9.2-pre.14"