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more build fixes

pull/80/head
Curt Mayer 6 years ago
parent
ad35748d5c
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b4c1ca7fcb
2 changed files with 1 additions and 374 deletions
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  1. 2
      Source/BPBIOS/Makefile
  2. 373
      Source/BPBIOS/def-ww.lib

2
Source/BPBIOS/Makefile
View File

@ -6,7 +6,7 @@ VERSIONS = \
41tbnk 41nbnk
OBJECTS = $(foreach ver,$(VERSIONS),bp$(ver).img)
OTHERS = zcpr33n.rel zcpr33t.rel bpbio-ww.rel bpsys.dat bpsys.bak
OTHERS = zcpr33n.rel zcpr33t.rel bpbio-ww.rel bpsys.dat bpsys.bak bpbio-ww.err def-ww.lib
TOOLS = ../../Tools
CPMCP = $(TOOLS)/`uname`/cpmcp

373
Source/BPBIOS/def-ww.lib
View File

@ -1,373 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - D-X Designs Pty Ltd P112 CPU Board - **********************
; Tailor your system here.
;
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '17 Jan 14' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX Z41 ',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU YES ; Is this a banked BIOS?
ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; Internal HBIOS Mini Proxy
CONF_T EQU NO ; Set for Segment Configuration T
CONF_N EQU YES ; Set for Segment Configuration N
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
ESCC_B EQU no ; Include ESCC Channel B Driver?
; The following two devices result in non-standard data rates
; with the standard 16.00 MHz crystal in the P112. If a more
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
; is used, the ports become usable.
; Driver code for ASCI0 and ASCI1 includes an option for
; assembling Polled or Interrupt-driven buffered input.
; Select the desired option for ASCI0 with the BUFFA0 flag,
; and BUFFA1 for ASCI1.
ASCI_0 EQU false ; Include ASCI0 Driver?
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
ASCI_1 EQU false ; Include ASCI1 Driver?
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
;--- Floppy Diskette Section ---
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;--- RAM Disk Section ---
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
SCSI EQU NO ; YES = Use SCSI Driver
IDE EQU NO ; YES = Use IDE Driver
SIMHDSK EQU NO ; YES = Use SIMH HDSK Driver
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
DRV_A EQU no ; Set each of these equates for the drive and
DRV_B EQU no ; partition complement of your system. Assume
DRV_C EQU no ; that A-D are Floppies.
DRV_D EQU no
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
DRV_F EQU yes ; Partitions
DRV_G EQU yes
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes
DRV_L EQU yes
DRV_M EQU RAMDSK ; This is Yes for RAM drive
DRV_N EQU yes
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
DRV_P EQU no
;========== Configuration Unique Equates (P112) ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In P112, the ROM occupies the first 32k
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================

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