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Preliminary S100 Z80 CPU Support

Adds support for a general modular Z180-based S100 system.
pull/614/head
Wayne Warthen 4 months ago
parent
commit
b5f402554c
No known key found for this signature in database GPG Key ID: 8B34ED29C07EEB0A
  1. 1
      Doc/ChangeLog.txt
  2. BIN
      Doc/RomWBW Applications.pdf
  3. BIN
      Doc/RomWBW Disk Catalog.pdf
  4. BIN
      Doc/RomWBW Hardware.pdf
  5. BIN
      Doc/RomWBW Introduction.pdf
  6. BIN
      Doc/RomWBW System Guide.pdf
  7. BIN
      Doc/RomWBW User Guide.pdf
  8. 2
      ReadMe.md
  9. 2
      ReadMe.txt
  10. 2
      Source/Build.cmd
  11. 4
      Source/BuildFZ80.cmd
  12. 4
      Source/BuildSZ80.cmd
  13. 53
      Source/Doc/Hardware.md
  14. 18
      Source/FZ80/Bank Layout.txt
  15. BIN
      Source/FZ80/fz80_ptbl.bin
  16. 2
      Source/HBIOS/Bank Layout.txt
  17. 3
      Source/HBIOS/Build.cmd
  18. 2
      Source/HBIOS/Build.ps1
  19. 3
      Source/HBIOS/Build.sh
  20. 72
      Source/HBIOS/Config/SZ80_fpga.asm
  21. 16
      Source/HBIOS/Config/SZ80_std.asm
  22. 4
      Source/HBIOS/cfg_DUO.asm
  23. 4
      Source/HBIOS/cfg_DYNO.asm
  24. 4
      Source/HBIOS/cfg_EPITX.asm
  25. 4
      Source/HBIOS/cfg_EZZ80.asm
  26. 4
      Source/HBIOS/cfg_GMZ180.asm
  27. 4
      Source/HBIOS/cfg_HEATH.asm
  28. 4
      Source/HBIOS/cfg_MASTER.asm
  29. 4
      Source/HBIOS/cfg_MBC.asm
  30. 4
      Source/HBIOS/cfg_MK4.asm
  31. 4
      Source/HBIOS/cfg_MON.asm
  32. 4
      Source/HBIOS/cfg_N8.asm
  33. 4
      Source/HBIOS/cfg_NABU.asm
  34. 4
      Source/HBIOS/cfg_RCEZ80.asm
  35. 4
      Source/HBIOS/cfg_RCZ180.asm
  36. 4
      Source/HBIOS/cfg_RCZ280.asm
  37. 4
      Source/HBIOS/cfg_RCZ80.asm
  38. 4
      Source/HBIOS/cfg_RPH.asm
  39. 4
      Source/HBIOS/cfg_S100.asm
  40. 4
      Source/HBIOS/cfg_SBC.asm
  41. 4
      Source/HBIOS/cfg_SCZ180.asm
  42. 34
      Source/HBIOS/cfg_SZ80.asm
  43. 2
      Source/HBIOS/cfg_UNA.asm
  44. 4
      Source/HBIOS/cfg_Z80RETRO.asm
  45. 4
      Source/HBIOS/cfg_ZETA.asm
  46. 4
      Source/HBIOS/cfg_ZETA2.asm
  47. 60
      Source/HBIOS/hbios.asm
  48. 2
      Source/HBIOS/hbios.inc
  49. 12
      Source/HBIOS/plt_pretty.inc
  50. 16
      Source/HBIOS/ppide.asm
  51. 24
      Source/HBIOS/scon.asm
  52. 24
      Source/HBIOS/sd.asm
  53. 10
      Source/HBIOS/std.asm
  54. 8
      Source/Makefile
  55. 38
      Source/SZ80/Bank Layout.txt
  56. 4
      Source/SZ80/Build.cmd
  57. 0
      Source/SZ80/Clean.cmd
  58. 4
      Source/SZ80/Makefile
  59. 4
      Source/SZ80/SZ80 Disk Layout.txt
  60. 2
      Source/ver.inc
  61. 2
      Source/ver.lib

1
Doc/ChangeLog.txt

@ -26,6 +26,7 @@ Version 3.6
- MAP: User guide. Reorder sections around disk formatting
- R?M: Randy Merkel provided ZSDOS Programmer's Manual as translated by Wayne Hortensius
- WBW: Updated Cowgol disk image with latest COWFIX.COM from Ladislau Szilagyi
- WBW: Preliminary support for S100 Computers Z80 CPU
Version 3.5.1
-------------

BIN
Doc/RomWBW Applications.pdf

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Doc/RomWBW Disk Catalog.pdf

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Doc/RomWBW Hardware.pdf

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Doc/RomWBW Introduction.pdf

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Doc/RomWBW System Guide.pdf

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Doc/RomWBW User Guide.pdf

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2
ReadMe.md

@ -7,7 +7,7 @@
**RomWBW Introduction** \
Version 3.6 \
Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
12 Sep 2025
22 Sep 2025
# Overview

2
ReadMe.txt

@ -1,6 +1,6 @@
RomWBW Introduction
Wayne Warthen (wwarthen@gmail.com)
12 Sep 2025
22 Sep 2025

2
Source/Build.cmd

@ -10,7 +10,7 @@ call BuildZRC || exit /b
call BuildZ1RCC || exit /b
call BuildZZRCC || exit /b
call BuildZRC512 || exit /b
call BuildFZ80 || exit /b
call BuildSZ80 || exit /b
call BuildEZ512 || exit /b
if "%1" == "dist" (

4
Source/BuildFZ80.cmd

@ -1,4 +0,0 @@
@echo off
setlocal
pushd FZ80 && call Build || exit /b & popd

4
Source/BuildSZ80.cmd

@ -0,0 +1,4 @@
@echo off
setlocal
pushd SZ80 && call Build || exit /b & popd

53
Source/Doc/Hardware.md

@ -118,7 +118,8 @@ Others
| [Heath H8 Z80 System]^5^ | H8 | HEATH_std.rom | 115200 |
| [NABU w/ RomWBW Option Board]^5^ | NABU | NABU_std.rom | 115200 |
| [S100 Computers Z180 SBC]^4^ | S100 | S100_std.rom | 57600 |
| [S100 Computers FPGA Z80 SBC]^4^ | S100 | FZ80_std.rom | 9600 |
| [S100 Computers Z80 CPU]^4^ | S100 | SZ80_std.rom | 9600 |
| [S100 Computers FPGA Z80 SBC]^4^ | S100 | SZ80_fpga.rom | 9600 |
| [UNA Hardware BIOS]^1^ | - | UNA_std.rom | - |
| [Z80-Retro SBC]^3^ | - | Z80RETRO_std.rom | 38400 |
| [Z180 Mark IV SBC]^1^ | ECB | MK4_std.rom | 38400 |
@ -414,14 +415,56 @@ of the SIO ports, for ease of use with modern computers.
`\clearpage`{=latex}
## S100 Computers FPGA Z80 SBC
## S100 Computers
### S100 Computers Z80 CPU
Z80-based S100 Modular System
* Creator: John Monahan
* Website: [S100 Computers Z80 CPU](http://www.s100computers.com/My%20System%20Pages/Z80%20Board/Z80%20CPU%20Board.htm)
#### ROM Image File: SZ80_std.rom
| | |
|-------------------|---------------|
| Bus | S100 |
| Default CPU Speed | 8.000 MHz |
| Interrupts | None |
| System Timer | None |
| Serial Default | 9600 Baud |
| Memory Manager | SZ80 |
| ROM Size | 0 KB |
| RAM Size | 512 KB |
#### Supported Hardware
- SCON: IO=0
- ESPSD: IO=128, PRIMARY
- ESPSD: IO=128, SECONDARY
- MD: TYPE=RAM
- PPIDE: MODE=STD, IO=48, MASTER
- PPIDE: MODE=STD, IO=48, SLAVE
- PPIDE: MODE=S100A, IO=56, MASTER
- PPIDE: MODE=S100A, IO=56, SLAVE
- PPIDE: MODE=S100B, IO=56, MASTER
- PPIDE: MODE=S100B, IO=56, SLAVE
- SD: MODE=FZ80, IO=108, UNITS=2
#### Notes:
- Requires Propeller Console Board (or equivalent)
`\clearpage`{=latex}
### S100 Computers FPGA Z80 SBC
An FPGA Z80 based S100 SBC
* Creator: John Monahan |
* Creator: John Monahan
* Website: [S100 Computers FPGA Z80 SBC](http://www.s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm)
#### ROM Image File: FZ80_std.rom
#### ROM Image File: SZ80_fpga.rom
| | |
|-------------------|---------------|
@ -455,7 +498,7 @@ An FPGA Z80 based S100 SBC
#### Notes:
- Requires matching FPGA code
- Requires matching FPGA code, see [S100 Projects RomWBW T35 Project](https://github.com/s100projects/ROMWBW_T35).
`\clearpage`{=latex}

18
Source/FZ80/Bank Layout.txt

@ -1,18 +0,0 @@
FPGA Z80 has no real ROM. It has a single 512K RAM chip.
The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM
must be preloaded by the FPGA Monitor CF Loader. There will be no ROM
disk available under RomWBW. There will be a RAM Disk and it's initial
contents will be seeded by the image loaded by the CF Loader.
Bank Contents Description
-------- -------- -----------
0x0 BIOS HBIOS Bank (operating)
0x1 IMG0 ROM Loader, Monitor, ROM OSes
0x2 IMG1 ROM Applications
0x3 IMG2 Reserved
0x4-0xB RAMD RAM Disk Banks
0xC BUF OS Buffers (CP/M3)
0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0xE USR User Bank (CP/M TPA, etc.)
0xF COM Common Bank, Upper 32KB

BIN
Source/FZ80/fz80_ptbl.bin

Binary file not shown.

2
Source/HBIOS/Bank Layout.txt

@ -71,7 +71,7 @@ Bank ID Usage
0x82 User TPA
0x83 Common
ROMless Standard Bank Layout (512K): ZRC, ZRC512, EZ512, Z1RCC, ZZRCC, FZ80
ROMless Standard Bank Layout (512K): ZRC, ZRC512, EZ512, Z1RCC, ZZRCC
Bank ID Usage
------- ------

3
Source/HBIOS/Build.cmd

@ -269,7 +269,8 @@ call Build HEATH std || exit /b
call Build EPITX std || exit /b
:: call Build MON std || exit /b
call Build NABU std || exit /b
call Build FZ80 std || exit /b
call Build SZ80 std || exit /b
call Build SZ80 fpga || exit /b
call Build UNA std || exit /b
goto :eof

2
Source/HBIOS/Build.ps1

@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
# UNA BIOS is simply imbedded, it is not built here.
#
$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80", "RCEZ80"
$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180"
$PlatformListZ280 = "RCZ280"

3
Source/HBIOS/Build.sh

@ -53,7 +53,8 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
# ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="SZ80"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="SZ80"; ROM_CONFIG="fpga"; bash Build.sh
ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
exit
fi

72
Source/HBIOS/Config/SZ80_fpga.asm

@ -0,0 +1,72 @@
;
;==================================================================================================
; ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80
;==================================================================================================
;
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
;
; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
;
; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
; |
; +-> cfg_<platform>.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
; |
; +-> Config/<plt>_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
; |
; +-> Config/<plt>_<cust>.asm - USER: CUSTOM USER BUILD SETTINGS
;
; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
; OVERRIDE THESE SETTINGS AS DESIRED.
;
; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE
; MODIFIED.
;
; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
;
; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
;
; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
;
#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
;
#INCLUDE "cfg_SZ80.asm"
;
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
;
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
;
DS5RTCENABLE .SET TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
;
SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
;
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
;
FVENABLE .SET TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
;
ESPSDENABLE .SET TRUE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
ESPSD0DUAL .SET TRUE ; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)

16
Source/HBIOS/Config/FZ80_std.asm → Source/HBIOS/Config/SZ80_std.asm

@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80
; ROMWBW DEFAULT BUILD SETTINGS FOR S100 Z80
;==================================================================================================
;
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@ -43,18 +43,22 @@
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
;
#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
#DEFINE DEFSERCFG SER_9600_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
;
#INCLUDE "cfg_FZ80.asm"
#INCLUDE "cfg_SZ80.asm"
;
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
MEMMGR .SET MM_SZ80 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
;
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
ESPSDENABLE .SET TRUE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
ESPSD0DUAL .SET TRUE ; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
#DEFINE SIZERAM

4
Source/HBIOS/cfg_DUO.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -296,7 +296,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_DYNO.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -311,7 +311,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_EPITX.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -307,7 +307,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_EZZ80.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -316,7 +316,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_GMZ180.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -306,7 +306,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_HEATH.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -316,7 +316,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_MASTER.asm

@ -49,7 +49,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -375,7 +375,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_MBC.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -290,7 +290,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_MK4.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -301,7 +301,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_MON.asm

@ -51,7 +51,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -313,7 +313,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_N8.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -303,7 +303,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_NABU.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -316,7 +316,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_RCEZ80.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -314,7 +314,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_RCZ180.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -311,7 +311,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_RCZ280.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -321,7 +321,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_RCZ80.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -319,7 +319,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_RPH.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -291,7 +291,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_S100.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -311,7 +311,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_SBC.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -291,7 +291,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_SCZ180.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -311,7 +311,7 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

34
Source/HBIOS/cfg_FZ80.asm → Source/HBIOS/cfg_SZ80.asm

@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: FZ80
; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SZ80
;==================================================================================================
;
; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@ -42,14 +42,14 @@
; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
;
#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
#DEFINE PLATFORM_NAME "S100 Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_SZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -105,7 +105,7 @@ SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
;
FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
FPLED_IO .SET $FF ; FP: PORT ADDRESS FOR FP LEDS
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
@ -165,9 +165,9 @@ SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
;
DS5RTCENABLE .SET TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
;
SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
SSERSTATUS .SET $34 ; SSER: STATUS PORT
SSERDATA .SET $35 ; SSER: DATA PORT
@ -259,7 +259,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
FVENABLE .SET TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
;
MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDROM .SET FALSE ; MD: ENABLE ROM DISK
@ -299,24 +299,24 @@ IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 3 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDECNT .SET 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_S100A ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1MODE .SET PPIDEMODE_S100A ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $38 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1MODE .SET PPIDEMODE_S100B ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE1BASE .SET $30 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2MODE .SET PPIDEMODE_S100B ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $38 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2MODE .SET PPIDEMODE_NONE ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_T35 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@ -348,7 +348,7 @@ PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
;
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
LPTMODE .SET LPTMODE_S100 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_UNA.asm

@ -15,7 +15,7 @@
;
#INCLUDE "../UBIOS/ubios.inc"
;
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;

4
Source/HBIOS/cfg_Z80RETRO.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -269,7 +269,7 @@ PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE

4
Source/HBIOS/cfg_ZETA.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -238,7 +238,7 @@ PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

4
Source/HBIOS/cfg_ZETA2.asm

@ -49,7 +49,7 @@
;
#INCLUDE "cfg_MASTER.asm"
;
PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -249,7 +249,7 @@ PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

60
Source/HBIOS/hbios.asm

@ -663,7 +663,7 @@ HBX_ROM:
;
#IF (MEMMGR == MM_Z2)
#IF (CPUFAM == CPU_EZ80)
#IF (CPUFAM == CPU_EZ80)
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
@ -676,16 +676,16 @@ HBX_ROM:
OUT_NN_A(MPGSEL_1) ; BANK_1: 16K - 32K
RET ; DONE
#ELSE
#ELSE
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
#IF (PLATFORM == PLT_DUO)
#IF (PLATFORM == PLT_DUO)
ADD A,64 ; ADD 64 x 32K - RAM STARTS FROM 2048K
#ELSE
#ELSE
ADD A,ROMSIZE / 32 ; STARTING RAM BANK NUMBER OFFSET
#ENDIF
#ENDIF
;
HBX_ROM:
RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
@ -694,11 +694,11 @@ HBX_ROM:
INC A ;
EZ80_IO()
OUT (MPGSEL_1),A ; BANK_1: 16K - 32K
#IF (CPUFAM == CPU_Z280)
#IF (CPUFAM == CPU_Z280)
PCACHE
#ENDIF
#ENDIF
RET ; DONE
#ENDIF
#ENDIF
#ENDIF
;
#IF (MEMMGR == MM_N8)
@ -939,6 +939,27 @@ Z280_SYSCALL_GO:
RETIL ; RETURN FROM INT
#ENDIF
;
#IF (MEMMGR == MM_SZ80)
;
; 1MB OF RAM IN 16K PAGES. STARTS AT 4TH 16K PAGE AND WRAPS AROUND
; BECAUSE PAGE 2 & 3 ARE FIXED TO HIGH 32K OF CPU ADDRESS SPACE.
;
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
ADD A,ROMSIZE / 32 ; STARTING RAM BANK NUMBER OFFSET
;
HBX_ROM:
ADD A,2 ; OFFSET TO SKIP OVER FIXED PAGES
RLA ; LOW 2 BITS
RLA ; ... ARE NOT USED
RLA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
OUT ($D2),A ; BANK_0: 0K - 16K
ADD A,4 + 1 ; +1 TO KEEP MONITOR ROM INACTIVE
OUT ($D3),A ; BANK_1: 16K - 32K
RET ; DONE
#ENDIF
;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; Copy Data - Possibly between banks. This resembles CP/M 3, but
; usage of the HL and DE registers is reversed.
@ -1851,12 +1872,25 @@ ROMRESUME:
EZ80_IO()
OUT (MPGENA),A ; ENABLE MMU NOW
;
#IF (PLATFORM == PLT_FZ80)
#IF (PLATFORM == PLT_SZ80)
; REMOVE FPGA ROM MONITOR FROM THE CPU ADDRESS SPACE
LD A,%00000010
OUT ($07),A
#ENDIF
#ENDIF
;
; S100 Z80 MMU INITIALIZATION
;
#IF (MEMMGR == MM_SZ80)
;
#IFDEF ROMBOOT
LD A,4 << 2
OUT ($D2),A
LD A,(5 << 2) + 1 ; +1 TO DEACTIVATE MONITOR ROM
OUT ($D3),A
#ENDIF
;
#ENDIF
;
;--------------------------------------------------------------------------------------------------
@ -3259,6 +3293,9 @@ HB_Z280BUS1:
;#ENDIF
#IF (MEMMGR == MM_EZ512)
.TEXT "EZ512$"
#ENDIF
#IF (MEMMGR == MM_SZ80)
.TEXT "SZ80$"
#ENDIF
CALL PRTSTRD
.TEXT " MMU$"
@ -3588,7 +3625,7 @@ HB_WDZ:
JR NZ,INITSYS3 ; NOT SET, BYPASS CONSOLE SWITCH
#ENDIF
;
#IF (PLATFORM == PLT_FZ80)
#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2))
; IOBYTE: XXXXXVVC
; 00- FORCE ONBOARD VGA/PS2 KBD (FV)
; --1 FORCE PROPELLER CONSOLE (SCON)
@ -3963,6 +4000,9 @@ HB_PCINITTBL:
#ENDIF
#IF (TMSENABLE)
.DW TMS_PREINIT
#ENDIF
#IF (SCONENABLE)
.DW SCON_PREINIT
#ENDIF
.DW TERM_PREINIT ; ALWAYS DO THIS ONE
#IF (PIOENABLE)

2
Source/HBIOS/hbios.inc

@ -207,7 +207,7 @@ PLT_EPITX .EQU 19 ; Z180 MINI-ITX
PLT_MON .EQU 20 ; MONSPUTER (DEPRECATED)
PLT_GMZ180 .EQU 21 ; GENESIS Z180 SYSTEM
PLT_NABU .EQU 22 ; NABU PC W/ ROMWBW OPTION BOARD
PLT_FZ80 .EQU 23 ; S100 FPGA Z80
PLT_SZ80 .EQU 23 ; S100 Z80
PLT_RCEZ80 .EQU 24 ; RCBUS W/ eZ80
;
; HBIOS GLOBAL ERROR RETURN VALUES

12
Source/HBIOS/plt_pretty.inc

@ -38,7 +38,7 @@
; MONSPUTER
; GENESIS Z180
; NABU
; S100 FPGA Z80
; S100 Z80
; RCBUS eZ80
;
STR_PLT_PRETTY:
@ -177,11 +177,11 @@ STR_PLT_PRETTY:
.DB "| .` | / _ \\ | _ \\ | |_| |",10,13
.DB "|_|\\_| /_/ \\_\\ |___/ \\___/",10,13
#ENDIF
#IF (PLATFORM == PLT_FZ80)
.DB " ___ _ __ __ ___ ___ ___ _ ____ ___ __",10,13
.DB "/ __| / | / \\ / \\ | __| | _ \\ / __| /_\\ |_ / ( _ ) / \\ ",10,13
.DB "\\__ \\ | | | () | | () | | _| | _/ | (_ | / _ \\ / / / _ \\ | () |",10,13
.DB "|___/ |_| \\__/ \\__/ |_| |_| \\___|/_/ \\_\\ /___| \\___/ \\__/",10,13
#IF (PLATFORM == PLT_SZ80)
.DB " ___ _ __ __ _______ __",10,13
.DB " / __/ |/ \\ / \\ |_ ( _ )/ \\",10,13
.DB " \\__ \\ | () | () | / // _ \\ () |",10,13
.DB " |___/_|\\__/ \\__/ /___\\___/\\__/",10,13
#ENDIF
#IF (PLATFORM == PLT_RCEZ80)
.DB " ___ ___ ___ _ _ ___ ____ ___ __",10,13

16
Source/HBIOS/ppide.asm

@ -477,6 +477,19 @@ PPIDE_INIT2:
LD A,(IY+PPIDE_DATALO) ; GET IO BASE ADDRES
CALL PRTHEXBYTE ; DISPLAY IT
;
LD A,(IY+PPIDE_MODE) ; GET MODE
LD DE,PPIDE_STR_PRIMARY ; LOAD PRIMARY STRING
CP PPIDEMODE_S100A ; PRIMARY?
JR Z,PPIDE_INIT2A ; IF SO, DISPLAY IT
LD DE,PPIDE_STR_SECONDARY ; LOAD SECONDARY STRING
CP PPIDEMODE_S100B ; SECONDARY?
JR Z,PPIDE_INIT2A ; IF SO, DISPLAY IT
JR PPIDE_INIT2B ; NEITHER, SKIP IT
;
PPIDE_INIT2A:
CALL WRITESTR ; DISPLAY IT
;
PPIDE_INIT2B:
CALL PPIDE_DETECT ; PROBE FOR INTERFACE
JR Z,PPIDE_INIT3 ; GOT IT, MOVE ON TO INIT UNITS
CALL PC_SPACE ; FORMATTING
@ -2311,6 +2324,9 @@ PPIDE_STR_8BIT .TEXT " 8-BIT$"
PPIDE_STR_TYPEATA .TEXT " ATA$"
PPIDE_STR_TYPEATAPI .TEXT " ATAPI$"
;
PPIDE_STR_PRIMARY .TEXT " PRIMARY$"
PPIDE_STR_SECONDARY .TEXT " SECONDARY$"
;
;=============================================================================
; DATA STORAGE
;=============================================================================

24
Source/HBIOS/scon.asm

@ -22,6 +22,21 @@ SCON_ROWS .EQU 40
;
;
;
SCON_PREINIT:
;
; ADD OURSELVES TO CIO DISPATCH TABLE
;
LD D,0 ; PHYSICAL UNIT IS ZERO
LD E,CIODEV_SCON ; DEVICE TYPE
LD BC,SCON_FNTBL ; BC := FUNCTION TABLE ADDRESS
CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED
CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE
;
XOR A ; SIGNAL SUCCESS
RET
;
;
;
SCON_INIT:
CALL NEWLINE
PRTS("SCON:$")
@ -39,15 +54,6 @@ SCON_INIT:
CALL PRTDECB
CALL PRTSTRD
.TEXT " TEXT (ANSI)$"
;
; ADD OURSELVES TO CIO DISPATCH TABLE
;
LD D,0 ; PHYSICAL UNIT IS ZERO
LD E,CIODEV_SCON ; DEVICE TYPE
LD BC,SCON_FNTBL ; BC := FUNCTION TABLE ADDRESS
CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED
;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE
CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE
;
XOR A ; SIGNAL SUCCESS
RET

24
Source/HBIOS/sd.asm

@ -420,7 +420,7 @@ SD_INVCS .EQU FALSE ; INVERT CS
; 0: PRIMARY DEVICE, USE VALUE ~$01
; 1: SECONDARY DEVICE, USE VALUE ~$02
;
#IF (SDMODE == SDMODE_FZ80) ; S100 FPGA Z80
#IF (SDMODE == SDMODE_T35) ; S100 FPGA Z80
SD_IOBASE .EQU $6C ; IOBASE
SD_DATA .EQU SD_IOBASE + 0 ; DATA IN/OUT PORT
SD_CLKSEL .EQU SD_IOBASE + 1 ; CLOCK SPEED SELECT PORT
@ -433,7 +433,7 @@ SD_OPRDEF .EQU $FF ; QUIESCENT STATE
SD_CS0 .EQU %00000001 ; PRIMARY DEVICE SELECT BIT
SD_CS1 .EQU %00000010 ; SECONDARY DEVICE SELECT BIT
SD_INVCS .EQU TRUE ; INVERT CS
DEVECHO "FZ80"
DEVECHO "T35"
#ENDIF
;
#IF (SDMODE == SDMODE_EZ512) ; Z80 PIO ON EAZY80-512
@ -728,8 +728,8 @@ SD_INIT:
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
PRTS(" MODE=FZ80$")
#IF (SDMODE == SDMODE_T35)
PRTS(" MODE=T35$")
PRTS(" IO=0x$")
LD A,SD_IOBASE
CALL PRTHEXBYTE
@ -2021,7 +2021,7 @@ SD_SETUP:
OUT (SD_OPRREG),A
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
#IF (SDMODE == SDMODE_T35)
LD A,SD_OPRDEF ; DEFAULT SELECT VALUE
LD (SD_OPRVAL),A ; PUT IN SHADOW
OUT (SD_OPRREG),A ; WRITE TO PORT
@ -2076,7 +2076,7 @@ SD_SELECT:
; CALL SD_WAITTX
;#ENDIF
;
#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM))
#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_T35) | (SDMODE == SDMODE_GM))
LD A,(IY+SD_DEV) ; GET CURRENT DEVICE
OR A ; SET FLAGS
LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK
@ -2108,7 +2108,7 @@ SD_SELECT2:
; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM))
#IF (SD_INVCS)
#IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
#IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_T35) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
XOR SD_CS0 | SD_CS1
#ELSE
XOR SD_CS0
@ -2140,7 +2140,7 @@ SD_DESELECT:
CALL DLY32 ; DELAY FOR FINAL BIT
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
#IF (SDMODE == SDMODE_T35)
CALL SD_WAITBSY
#ENDIF
;
@ -2156,7 +2156,7 @@ SD_DESELECT:
#ENDIF
; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
#IF (SD_INVCS)
#IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
#IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_T35) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1))
XOR SD_CS0 | SD_CS1
#ELSE
XOR SD_CS0
@ -2186,7 +2186,7 @@ SD_WAITRX:
;
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
#IF (SDMODE == SDMODE_T35)
;
; WAIT WHILE FPGA SPI INTERFACE IS BUSY SENDING OR RECEIVING
;
@ -2276,7 +2276,7 @@ SD_PUT1:
OUT (SD_OPRREG),A ; LEAVE WITH CLOCK LOW
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
#IF (SDMODE == SDMODE_T35)
CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
OUT (SD_DATA),A ; POST THE VALUE
OUT (SD_ACTION),A ; INITIATE THE WRITE
@ -2387,7 +2387,7 @@ SD_GET1:
#ENDIF
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
#IF (SDMODE == SDMODE_T35)
CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
IN A,(SD_ACTION) ; INITIATE READ
CALL SD_WAITBSY ; WAIT FOR DONE

10
Source/HBIOS/std.asm

@ -24,7 +24,7 @@
; 20. MON Jacques Pelletier's Monsputer (deprecated)
; 21. GMZ180 Doug Jacksons' Genesis Z180 System
; 22. NABU NABU w/ Les Bird's RomWBW Option Board
; 23. FZ80 S100 Computers FPGA Z80
; 23. SZ80 S100 Computers Z80
; 24. RCEZ80 RCBus eZ80
;
;
@ -98,6 +98,7 @@ MM_MBC .EQU 7 ; MBC MEMORY MANAGER
MM_RPH .EQU 8 ; Z180 WITH RPH EXTENSIONS
MM_MON .EQU 9 ; MONSPUTER MMU (DEPRECATED)
MM_EZ512 .EQU 10 ; EZ512 BANK SWITCHING
MM_SZ80 .EQU 11 ; S100 Z80 CPU ONBAORD MEMORY MANAGER
;
; BOOT STYLE
;
@ -241,7 +242,7 @@ SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE)
SDMODE_PIO .EQU 11 ; Z80 PIO bitbang
SDMODE_Z80R .EQU 12 ; Z80 Retro
SDMODE_EPITX .EQU 13 ; Mini ITX Z180
SDMODE_FZ80 .EQU 14 ; S100 FPGA Z80
SDMODE_T35 .EQU 14 ; S100 FPGA Z80
SDMODE_GM .EQU 15 ; Genesis SD Driver
SDMODE_EZ512 .EQU 16 ; EZ512 SD
SDMODE_K80W .EQU 17 ; K80W SD
@ -777,7 +778,10 @@ DSCVAL .EQU DEFSERCFG
SYSECHO "MONSPUTER ONBOARD (MON)" ; DEPRECATED
#ENDIF
#IF (MEMMGR == MM_EZ512)
SYSECHO "EAZY80-512 ONBOARD" ; DEPRECATED
SYSECHO "EAZY80-512 ONBOARD"
#ENDIF
#IF (MEMMGR == MM_SZ80)
SYSECHO "S100 Z80"
#ENDIF
SYSECHO "\n"
#ENDIF

8
Source/Makefile

@ -2,12 +2,12 @@
# order is actually important, because of build dependencies
#
.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 ez512
.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512 sz80 ez512
.ONESHELL:
.SHELLFLAGS = -ce
all: prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 ez512
all: prop shared bp images rom zrc z1rcc zzrcc zrc512 sz80 ez512
doc:
$(MAKE) --directory Doc $(ACTION)
@ -53,8 +53,8 @@ zzrcc:
zrc512:
$(MAKE) --directory ZRC512 $(ACTION)
fz80:
$(MAKE) --directory FZ80 $(ACTION)
sz80:
$(MAKE) --directory SZ80 $(ACTION)
ez512:
$(MAKE) --directory EZ512 $(ACTION)

38
Source/SZ80/Bank Layout.txt

@ -0,0 +1,38 @@
S100 Z80 has no real ROM. It has 1024K RAM.
The ROMless startup mode treats the entire 1024KB as RAM. 128KB of RAM
must be preloaded by the Monitor CF Loader. There will be no ROM
disk available under RomWBW. There will be a RAM Disk and it's initial
contents will be seeded by the image loaded by the CF Loader.
Bank Contents Description
-------- -------- -----------
0x0 BIOS HBIOS Bank (operating)
0x1 IMG0 ROM Loader, Monitor, ROM OSes
0x2 IMG1 ROM Applications
0x3 IMG2 Reserved
0x4-0x1B RAMD RAM Disk Banks
0x1C BUF OS Buffers (CP/M3)
0x1D AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0x1E USR User Bank (CP/M TPA, etc.)
0x1F COM Common Bank, Upper 32KB
FPGA Z80 has no real ROM. It has a single 512K RAM chip.
The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM
must be preloaded by the FPGA Monitor CF Loader. There will be no ROM
disk available under RomWBW. There will be a RAM Disk and it's initial
contents will be seeded by the image loaded by the CF Loader.
Bank Contents Description
-------- -------- -----------
0x0 BIOS HBIOS Bank (operating)
0x1 IMG0 ROM Loader, Monitor, ROM OSes
0x2 IMG1 ROM Applications
0x3 IMG2 Reserved
0x4-0xB RAMD RAM Disk Banks
0xC BUF OS Buffers (CP/M3)
0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0xE USR User Bank (CP/M TPA, etc.)
0xF COM Common Bank, Upper 32KB

4
Source/FZ80/Build.cmd → Source/SZ80/Build.cmd

@ -5,7 +5,7 @@ set TOOLS=../../Tools
set PATH=%TOOLS%\srecord;%PATH%
for %%f in (..\..\Binary\FZ80_*.rom) do call :build %%~nf
for %%f in (..\..\Binary\SZ80_*.rom) do call :build %%~nf
goto :eof
@ -15,7 +15,7 @@ echo Creating %1 disk image...
echo.
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 sz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\%1.rom -binary -offset 0x80000 -o temp.dat -binary
move temp.dat ..\..\Binary\%1_hd1k_prefix.dat

0
Source/FZ80/Clean.cmd → Source/SZ80/Clean.cmd

4
Source/FZ80/Makefile → Source/SZ80/Makefile

@ -3,7 +3,7 @@ DEST=../../Binary
HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \
$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img
ROMS := $(wildcard $(DEST)/FZ80_*.rom)
ROMS := $(wildcard $(DEST)/SZ80_*.rom)
ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS))
OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS))
@ -17,7 +17,7 @@ DIFFPATH = $(DIFFTO)/Binary
%_hd1k_prefix.dat: $(DEST)/%.rom
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 sz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $< -binary -offset 0x80000 -o temp.dat -binary
mv temp.dat $@

4
Source/FZ80/FZ80 Disk Layout.txt → Source/SZ80/SZ80 Disk Layout.txt

@ -13,7 +13,7 @@ Start Length Start Length Description
Notes
-----
- FPGA Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM
- FPGA Z80 ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
- Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM
- Z80 Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
-- WBW 3:18 PM 6/30/2024

2
Source/ver.inc

@ -2,7 +2,7 @@
#DEFINE RMN 6
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.6.0-dev.25"
#DEFINE BIOSVER "3.6.0-dev.26"
#define rmj RMJ
#define rmn RMN
#define rup RUP

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 6
rup equ 0
rtp equ 0
biosver macro
db "3.6.0-dev.25"
db "3.6.0-dev.26"
endm

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