mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Fix for LCD Display of CPU Type
This commit is contained in:
Mark Pruden
@@ -67,7 +67,7 @@
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;
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; MEMORY LAYOUT:
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;
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;
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;
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; DESCRIPTION START LENGTH
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; ----------------------------- ------- -------
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; Page Zero 0x0000 0x0100
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@@ -97,7 +97,7 @@
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; D4 ~PSG_RES ~PSG_RES ~PSG_RES ROM_A19 ~PSG_RES
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; D3 STATUS_LED STATUS_LED VDP_LED PSG_LED ROM_A18 PSG_LED
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; D2 VDP_A14 VDP_A14 ROM_A17 VDP_LED
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; D1 ~VDP_SYN ~VDP_SYN ROM_A16
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; D1 ~VDP_SYN ~VDP_SYN ROM_A16
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; D0 ~VDP_RES ~VDP_RES VDP_RES ROM_A15 VDP_RES
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;
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; PORT SCG:0x9C 0x94 VDP:0x92 PSG:0xA2 0x80 MEDIA:0xA6
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@@ -183,7 +183,7 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
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; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC)
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; S100: LED Port = $0E, bit 2, inverted, dedicated port (LEDMODE_SC)
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; NABU: LED Port = $00, bits 5-3, normal, shared w/ control port (LEDMODE_NABU)
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;
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;
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#IF (LEDENABLE)
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#IF (LEDMODE == LEDMODE_STD)
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#DEFINE DIAG(N) PUSH AF
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@@ -1077,23 +1077,23 @@ HBX_INTSTK .EQU $
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;
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; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM)
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;
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; # Z80/Z280 Z180 MBC DUO NABU
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; --- -------------- -------------- -------------- -------------- --------------
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; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+
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; 1 CTC0B INT2 | | | HCCASND |
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; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2
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; 3 CTC0D TIM1 | | INT | INT VDP | INT
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; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC
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; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN
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; 6 CSIO | | | OPTCRD2 |
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; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+
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; 8 SIO1 SER1 -+ SIO0 SIO0
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; 9 PIO0A PIO0A SIO1 SIO1
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; 10 PIO0B PIO0B PIO0A PIO0A
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; 11 PIO1A PIO1A PIO0B PIO0B
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; 12 PIO1B PIO1B CTC0A CTC0A
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; 13 SIO0 CTC0B CTC0B
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; 14 SIO1 CTC0C CTC0C
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; # Z80/Z280 Z180 MBC DUO NABU
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; --- -------------- -------------- -------------- -------------- --------------
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; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+
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; 1 CTC0B INT2 | | | HCCASND |
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; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2
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; 3 CTC0D TIM1 | | INT | INT VDP | INT
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; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC
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; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN
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; 6 CSIO | | | OPTCRD2 |
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; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+
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; 8 SIO1 SER1 -+ SIO0 SIO0
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; 9 PIO0A PIO0A SIO1 SIO1
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; 10 PIO0B PIO0B PIO0A PIO0A
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; 11 PIO1A PIO1A PIO0B PIO0B
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; 12 PIO1B PIO1B CTC0A CTC0A
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; 13 SIO0 CTC0B CTC0B
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; 14 SIO1 CTC0C CTC0C
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; 15 CTC0D CTC0D
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;
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; IVT MUST START AT PAGE BOUNDARY
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@@ -1477,7 +1477,7 @@ BOOTWAIT:
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LD C,Z280_MSR ; MASTER STATUS REGISTER
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LD HL,$0000 ; SYS MODE, NO INTERRUPTS
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LDCTL (C),HL ; DO IT
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;
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;
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; SET MAXIMUM I/O WAIT STATES FOR NOW
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LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
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LD HL,$0033 ; 3 I/O WAIT STATES ADDED
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@@ -1880,23 +1880,23 @@ S100MON_SKIP:
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; MBC BANK SELECT MASK SETUP
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;--------------------------------------------------------------------------------------------------
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;
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; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS
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; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS
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; FIXED BY HARDWARE TO BE THE TOP 32K OF THE *FIRST* RAM CHIP. WHEN THERE
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; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN
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; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE
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; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT
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; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN
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; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE
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; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO
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; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE
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; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN
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; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE
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; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT
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; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN
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; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE
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; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO
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; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE
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; END OF THE RAM BANKS. THE MASK IS SETUP HERE BASED ON THE NUMBER OF RAM
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; CHIPS AND THEIR SIZE. NOTE THAT THE NUMBER OF RAM CHIPS IS INFERRED BY
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; THE TOTAL RAM SIZE. A SINGLE CHIP WILL BE EITHER 128K OR 512K. IF THE
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; TOTAL RAM SIZE OF THE SYSTEM IS 256K OR 1M, THEN THERE MUST BE TWO CH
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; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK
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; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK
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; SELECT ROUTINE.
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;
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#IF (MEMMGR == MM_MBC)
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;
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#IF (MEMMGR == MM_MBC)
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;
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; ALTHOUGH DYNAMIC SYSTEM RAM SIZING IS NOT POSSIBLE FOR MBC
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; (SEE COMMENTS ABOVE), WE ARE STILL DOING THE MASK SETUP
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@@ -2015,7 +2015,7 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM
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;
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LD A,(CB_BIDUSR)
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LD (HB_SRCBNK),A ; POPULATE HB_SRCBNK
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LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK
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LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK
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;
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LD A,BID_RAM0 ; POPULATE CB_BIDRAMD0 ; START RAMBANK
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LD (HL),A
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@@ -2163,12 +2163,12 @@ HB_START2:
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LD (HB_IM1CNT),A ; ... TO CLEAR IM1 VECTOR CNT
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LD HL,HB_IM1INT ; POINTER TO START OF IM1 IVT
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LD (HB_IM1PTR),HL ; ... TO CLEAR IM1 PTR
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LD HL,HB_TICK
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LD (VEC_TICK + 1),HL
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LD HL,HB_SECOND
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LD (VEC_SECOND + 1),HL
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JR HB_CLRIVT_Z ; DONE, JUMP OVER SUBROUTINE
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;
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HB_CLRIVT:
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@@ -2381,7 +2381,7 @@ HB_CPU2:
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; ADJUST HL TO REFLECT HALF SPEED OPERATION
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SRL H ; ADJUST HL ASSUMING
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RR L ; HALF SPEED OPERATION
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;
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;
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#IF (Z180_CLKDIV >= 1)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 2 ; Z8S180 REV K OR BETTER?
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@@ -3390,7 +3390,7 @@ HB_FP2:
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LD B,A ; MOVE TO B
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LD A,SECCON ; GET SEC CONSOLE SETTING
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CP $FF ; $FF MEANS USE INCREMENT
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JR NZ,HB_FP3 ; BYPASS IF NOT $FF
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JR NZ,HB_FP3 ; BYPASS IF NOT $FF
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;
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; INCREMENT CONSOLE UNIT
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LD A,(HB_NEWCON) ; GET NEW CONSOLE UNIT
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@@ -6605,7 +6605,7 @@ Z280_PRIVINST:
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;;;HB_DI ; DO THE DI
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XOR A ; NO INTERRUPTS
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LD (HB_MSRSAV),A ; UPDATE SAVED MSR LSB
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INC HL ; BUMP PAST IT
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JR Z280_PRIVINSTX
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;
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@@ -7049,7 +7049,7 @@ RS_IMAGE:
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RS_START:
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LD A,(HB_CURBNK) ; GET CURRENT BANK
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PUSH AF ; SAVE IT
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LD C,0 ; RUNNING BANK COUNT
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LD HL,$7FFF ; BYTE TEST ADDRESS
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LD IX,RS_ARY ; ORIG BYTE STORAGE ARRAY PTR
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@@ -7081,7 +7081,7 @@ RS_LOOP1:
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LD (HL),A
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OR A ; ZERO?
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JR Z,RS_NEXT ; SKIP STORED VALUE CHECK
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; VERIFY ALL STORED VALUES
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LD B,C ; INIT LOOP COUNTER
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LD E,0 ; INIT BANK ID
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@@ -7098,7 +7098,7 @@ RS_LOOP3:
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RS_NEXT:
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INC C ; ADD 1 TO RAM BANK COUNT
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JR RS_LOOP1 ; AND LOOP TILL DONE
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;
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;
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RS_DONE:
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LD E,C ; FINAL BANK COUNT TO E
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LD A,C
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@@ -7214,7 +7214,7 @@ FP_SETLEDS:
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#IF (FPLED_INV)
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XOR $FF ; INVERT BITS IF NEEDED
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#ENDIF
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OUT (FPLED_IO),A ; WRITE
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OUT (FPLED_IO),A ; WRITE
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FP_SETLEDS1:
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POP HL ; RESTORE HL
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RET ; DONE
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@@ -7451,7 +7451,7 @@ PS_PRTDT:
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LD A,00001111B
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CALL PRTIDXMSK
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CALL PS_PAD18 ; PAD TO 18 SPACES
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RET
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RET
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;
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; PRINT DISK CAPACITY (UNIT IN C, ATTRIBUTE IN E)
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;
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@@ -8560,7 +8560,7 @@ HB_TICKS .FILL 4,0 ; 32 BIT TICK COUNTER
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HB_SECTCK .DB TICKFREQ ; TICK COUNTER FOR FRACTIONAL SECONDS
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HB_SECS .FILL 4,0 ; 32 BIT SECONDS COUNTER
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;
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HB_CPUTYPE .DB 0 ; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
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HB_CPUTYPE .DB 0 ; 0=Z80, 1=Z180, 2=Z180-K, 3=Z180-N, 4=Z280
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HB_CPUOSC .DW CPUOSC ; ACTUAL CPU HARDWARE OSC FREQ IN KHZ
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;
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HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK)
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@@ -8638,7 +8638,7 @@ HB_APPBOOT1:
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; APPBOOT REQUIRES THAT THE COMMON BANK IS NOT CHANGED BY
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; THE NEW CONFIG. TEST FOR THIS AND DIAGNOSE IF SO.
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LD A,(HCB_BIDCOM) ; RUNNING COMMON BANK ID
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LD B,BF_SYSGET ; HBIOS SYSGET
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LD C,BF_SYSGET_BNKINFO ; BANK INFORMATION
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RST 08 ; D = BIOS BANK ID
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@@ -8847,7 +8847,7 @@ SLACK .EQU BNKTOP - $
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!!! ; FORCE AN ASSEMBLY ERROR
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#ENDIF
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;
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;;;#IF (SLACK < (1024 * 3))
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;;;#IF (SLACK < (1024 * 3))
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;;; .ECHO "*** ERROR: Low HEAP space!!!\n"
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;;; !!! ; FORCE AN ASSEMBLY ERROR
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;;;#ENDIF
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@@ -263,7 +263,7 @@ LCD_OUTF1:
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;
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; SEND FUNCTION STRING
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; DE=STRING ADDRESS, NULL TERMINATED
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;
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;
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LCD_OUTFS:
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LD A,(DE) ; NEXT BYTE TO SEND
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OR A ; SET FLAGS
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@@ -286,7 +286,7 @@ LCD_OUTD1:
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;
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; SEND DATA STRING
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; DE=STRING ADDRESS, NULL TERMINATED
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;
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;
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LCD_OUTDS:
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LD A,(DE) ; NEXT BYTE TO SEND
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OR A ; SET FLAGS
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@@ -384,9 +384,9 @@ LCD_CPU .DW LCD_CPU_Z80
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.DW LCD_CPU_Z280
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;
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LCD_CPU_Z80 .DB "Z80",0
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LCD_CPU_Z180 .DB "Z180-K",0
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LCD_CPU_Z180K .DB "Z180-N",0
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LCD_CPU_Z180N .DB "Z180",0
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LCD_CPU_Z180 .DB "Z180",0
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LCD_CPU_Z180K .DB "Z180-K",0
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LCD_CPU_Z180N .DB "Z180-N",0
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LCD_CPU_Z280 .DB "Z280",0
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