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Fix for LCD Display of CPU Type

pull/414/head
Mark Pruden 1 year ago
parent
2b6fbe7c58
commit
b7352da5c1
2 changed files with 52 additions and 52 deletions
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  1. 92
      Source/HBIOS/hbios.asm
  2. 12
      Source/HBIOS/lcd.asm

92
Source/HBIOS/hbios.asm
View File

@ -67,7 +67,7 @@
;
; MEMORY LAYOUT:
;
;
;
; DESCRIPTION START LENGTH
; ----------------------------- ------- -------
; Page Zero 0x0000 0x0100
@ -97,7 +97,7 @@
; D4 ~PSG_RES ~PSG_RES ~PSG_RES ROM_A19 ~PSG_RES
; D3 STATUS_LED STATUS_LED VDP_LED PSG_LED ROM_A18 PSG_LED
; D2 VDP_A14 VDP_A14 ROM_A17 VDP_LED
; D1 ~VDP_SYN ~VDP_SYN ROM_A16
; D1 ~VDP_SYN ~VDP_SYN ROM_A16
; D0 ~VDP_RES ~VDP_RES VDP_RES ROM_A15 VDP_RES
;
; PORT SCG:0x9C 0x94 VDP:0x92 PSG:0xA2 0x80 MEDIA:0xA6
@ -183,7 +183,7 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC)
; S100: LED Port = $0E, bit 2, inverted, dedicated port (LEDMODE_SC)
; NABU: LED Port = $00, bits 5-3, normal, shared w/ control port (LEDMODE_NABU)
;
;
#IF (LEDENABLE)
#IF (LEDMODE == LEDMODE_STD)
#DEFINE DIAG(N) PUSH AF
@ -1077,23 +1077,23 @@ HBX_INTSTK .EQU $
;
; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM)
;
; # Z80/Z280 Z180 MBC DUO NABU
; --- -------------- -------------- -------------- -------------- --------------
; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+
; 1 CTC0B INT2 | | | HCCASND |
; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2
; 3 CTC0D TIM1 | | INT | INT VDP | INT
; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC
; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN
; 6 CSIO | | | OPTCRD2 |
; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+
; 8 SIO1 SER1 -+ SIO0 SIO0
; 9 PIO0A PIO0A SIO1 SIO1
; 10 PIO0B PIO0B PIO0A PIO0A
; 11 PIO1A PIO1A PIO0B PIO0B
; 12 PIO1B PIO1B CTC0A CTC0A
; 13 SIO0 CTC0B CTC0B
; 14 SIO1 CTC0C CTC0C
; # Z80/Z280 Z180 MBC DUO NABU
; --- -------------- -------------- -------------- -------------- --------------
; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+
; 1 CTC0B INT2 | | | HCCASND |
; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2
; 3 CTC0D TIM1 | | INT | INT VDP | INT
; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC
; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN
; 6 CSIO | | | OPTCRD2 |
; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+
; 8 SIO1 SER1 -+ SIO0 SIO0
; 9 PIO0A PIO0A SIO1 SIO1
; 10 PIO0B PIO0B PIO0A PIO0A
; 11 PIO1A PIO1A PIO0B PIO0B
; 12 PIO1B PIO1B CTC0A CTC0A
; 13 SIO0 CTC0B CTC0B
; 14 SIO1 CTC0C CTC0C
; 15 CTC0D CTC0D
;
; IVT MUST START AT PAGE BOUNDARY
@ -1477,7 +1477,7 @@ BOOTWAIT:
LD C,Z280_MSR ; MASTER STATUS REGISTER
LD HL,$0000 ; SYS MODE, NO INTERRUPTS
LDCTL (C),HL ; DO IT
;
;
; SET MAXIMUM I/O WAIT STATES FOR NOW
LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
LD HL,$0033 ; 3 I/O WAIT STATES ADDED
@ -1880,23 +1880,23 @@ S100MON_SKIP:
; MBC BANK SELECT MASK SETUP
;--------------------------------------------------------------------------------------------------
;
; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS
; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS
; FIXED BY HARDWARE TO BE THE TOP 32K OF THE *FIRST* RAM CHIP. WHEN THERE
; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN
; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE
; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT
; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN
; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE
; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO
; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE
; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN
; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE
; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT
; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN
; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE
; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO
; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE
; END OF THE RAM BANKS. THE MASK IS SETUP HERE BASED ON THE NUMBER OF RAM
; CHIPS AND THEIR SIZE. NOTE THAT THE NUMBER OF RAM CHIPS IS INFERRED BY
; THE TOTAL RAM SIZE. A SINGLE CHIP WILL BE EITHER 128K OR 512K. IF THE
; TOTAL RAM SIZE OF THE SYSTEM IS 256K OR 1M, THEN THERE MUST BE TWO CH
; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK
; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK
; SELECT ROUTINE.
;
#IF (MEMMGR == MM_MBC)
;
#IF (MEMMGR == MM_MBC)
;
; ALTHOUGH DYNAMIC SYSTEM RAM SIZING IS NOT POSSIBLE FOR MBC
; (SEE COMMENTS ABOVE), WE ARE STILL DOING THE MASK SETUP
@ -2015,7 +2015,7 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM
;
LD A,(CB_BIDUSR)
LD (HB_SRCBNK),A ; POPULATE HB_SRCBNK
LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK
LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK
;
LD A,BID_RAM0 ; POPULATE CB_BIDRAMD0 ; START RAMBANK
LD (HL),A
@ -2163,12 +2163,12 @@ HB_START2:
LD (HB_IM1CNT),A ; ... TO CLEAR IM1 VECTOR CNT
LD HL,HB_IM1INT ; POINTER TO START OF IM1 IVT
LD (HB_IM1PTR),HL ; ... TO CLEAR IM1 PTR
LD HL,HB_TICK
LD (VEC_TICK + 1),HL
LD HL,HB_SECOND
LD (VEC_SECOND + 1),HL
JR HB_CLRIVT_Z ; DONE, JUMP OVER SUBROUTINE
;
HB_CLRIVT:
@ -2381,7 +2381,7 @@ HB_CPU2:
; ADJUST HL TO REFLECT HALF SPEED OPERATION
SRL H ; ADJUST HL ASSUMING
RR L ; HALF SPEED OPERATION
;
;
#IF (Z180_CLKDIV >= 1)
LD A,(HB_CPUTYPE) ; GET CPU TYPE
CP 2 ; Z8S180 REV K OR BETTER?
@ -3390,7 +3390,7 @@ HB_FP2:
LD B,A ; MOVE TO B
LD A,SECCON ; GET SEC CONSOLE SETTING
CP $FF ; $FF MEANS USE INCREMENT
JR NZ,HB_FP3 ; BYPASS IF NOT $FF
JR NZ,HB_FP3 ; BYPASS IF NOT $FF
;
; INCREMENT CONSOLE UNIT
LD A,(HB_NEWCON) ; GET NEW CONSOLE UNIT
@ -6605,7 +6605,7 @@ Z280_PRIVINST:
;;;HB_DI ; DO THE DI
XOR A ; NO INTERRUPTS
LD (HB_MSRSAV),A ; UPDATE SAVED MSR LSB
INC HL ; BUMP PAST IT
JR Z280_PRIVINSTX
;
@ -7049,7 +7049,7 @@ RS_IMAGE:
RS_START:
LD A,(HB_CURBNK) ; GET CURRENT BANK
PUSH AF ; SAVE IT
LD C,0 ; RUNNING BANK COUNT
LD HL,$7FFF ; BYTE TEST ADDRESS
LD IX,RS_ARY ; ORIG BYTE STORAGE ARRAY PTR
@ -7081,7 +7081,7 @@ RS_LOOP1:
LD (HL),A
OR A ; ZERO?
JR Z,RS_NEXT ; SKIP STORED VALUE CHECK
; VERIFY ALL STORED VALUES
LD B,C ; INIT LOOP COUNTER
LD E,0 ; INIT BANK ID
@ -7098,7 +7098,7 @@ RS_LOOP3:
RS_NEXT:
INC C ; ADD 1 TO RAM BANK COUNT
JR RS_LOOP1 ; AND LOOP TILL DONE
;
;
RS_DONE:
LD E,C ; FINAL BANK COUNT TO E
LD A,C
@ -7214,7 +7214,7 @@ FP_SETLEDS:
#IF (FPLED_INV)
XOR $FF ; INVERT BITS IF NEEDED
#ENDIF
OUT (FPLED_IO),A ; WRITE
OUT (FPLED_IO),A ; WRITE
FP_SETLEDS1:
POP HL ; RESTORE HL
RET ; DONE
@ -7451,7 +7451,7 @@ PS_PRTDT:
LD A,00001111B
CALL PRTIDXMSK
CALL PS_PAD18 ; PAD TO 18 SPACES
RET
RET
;
; PRINT DISK CAPACITY (UNIT IN C, ATTRIBUTE IN E)
;
@ -8560,7 +8560,7 @@ HB_TICKS .FILL 4,0 ; 32 BIT TICK COUNTER
HB_SECTCK .DB TICKFREQ ; TICK COUNTER FOR FRACTIONAL SECONDS
HB_SECS .FILL 4,0 ; 32 BIT SECONDS COUNTER
;
HB_CPUTYPE .DB 0 ; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
HB_CPUTYPE .DB 0 ; 0=Z80, 1=Z180, 2=Z180-K, 3=Z180-N, 4=Z280
HB_CPUOSC .DW CPUOSC ; ACTUAL CPU HARDWARE OSC FREQ IN KHZ
;
HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK)
@ -8638,7 +8638,7 @@ HB_APPBOOT1:
; APPBOOT REQUIRES THAT THE COMMON BANK IS NOT CHANGED BY
; THE NEW CONFIG. TEST FOR THIS AND DIAGNOSE IF SO.
LD A,(HCB_BIDCOM) ; RUNNING COMMON BANK ID
LD B,BF_SYSGET ; HBIOS SYSGET
LD C,BF_SYSGET_BNKINFO ; BANK INFORMATION
RST 08 ; D = BIOS BANK ID
@ -8847,7 +8847,7 @@ SLACK .EQU BNKTOP - $
!!! ; FORCE AN ASSEMBLY ERROR
#ENDIF
;
;;;#IF (SLACK < (1024 * 3))
;;;#IF (SLACK < (1024 * 3))
;;; .ECHO "*** ERROR: Low HEAP space!!!\n"
;;; !!! ; FORCE AN ASSEMBLY ERROR
;;;#ENDIF

12
Source/HBIOS/lcd.asm
View File

@ -263,7 +263,7 @@ LCD_OUTF1:
;
; SEND FUNCTION STRING
; DE=STRING ADDRESS, NULL TERMINATED
;
;
LCD_OUTFS:
LD A,(DE) ; NEXT BYTE TO SEND
OR A ; SET FLAGS
@ -286,7 +286,7 @@ LCD_OUTD1:
;
; SEND DATA STRING
; DE=STRING ADDRESS, NULL TERMINATED
;
;
LCD_OUTDS:
LD A,(DE) ; NEXT BYTE TO SEND
OR A ; SET FLAGS
@ -384,9 +384,9 @@ LCD_CPU .DW LCD_CPU_Z80
.DW LCD_CPU_Z280
;
LCD_CPU_Z80 .DB "Z80",0
LCD_CPU_Z180 .DB "Z180-K",0
LCD_CPU_Z180K .DB "Z180-N",0
LCD_CPU_Z180N .DB "Z180",0
LCD_CPU_Z180 .DB "Z180",0
LCD_CPU_Z180K .DB "Z180-K",0
LCD_CPU_Z180N .DB "Z180-N",0
LCD_CPU_Z280 .DB "Z280",0

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