From b8930bd10a5b3e655b934dec8ab2b2eea0bee0dc Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Thu, 29 Aug 2019 12:36:54 -0700 Subject: [PATCH] Cleanup --- Source/HBIOS/cfg_ezz80.asm | 4 ++-- Source/HBIOS/cfg_master.asm | 4 ++-- Source/HBIOS/cfg_mk4.asm | 2 +- Source/HBIOS/cfg_n8.asm | 2 +- Source/HBIOS/cfg_rcz180.asm | 2 +- Source/HBIOS/cfg_rcz80.asm | 2 +- Source/HBIOS/cfg_sbc.asm | 2 +- Source/HBIOS/cfg_sc126.asm | 2 +- Source/HBIOS/cfg_zeta.asm | 2 +- Source/HBIOS/cfg_zeta2.asm | 2 +- Source/HBIOS/dsrtc.asm | 2 +- Source/HBIOS/hbios.asm | 10 ++++++---- Source/HBIOS/sd.asm | 12 ++++++------ Source/HBIOS/spk.asm | 4 ++-- 14 files changed, 27 insertions(+), 25 deletions(-) diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 3394a650..b2e9e885 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -34,8 +34,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; -RTC .EQU $C0 ; RTC LATCH REGISTER ADR -WDOG .EQU $6F ; WATCHDOG REGISTER ADR +RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR +WDOGIO .EQU $6F ; WATCHDOG REGISTER ADR ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index ea95fd58..df222c16 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -51,8 +51,8 @@ MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR ; -RTC .EQU $70 ; RTC LATCH REGISTER ADR -WDOG .EQU $6F ; WATCHDOG REGISTER ADR +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR +WDOGIO .EQU $6F ; WATCHDOG REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index 707945a2..fa35a14b 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -40,7 +40,7 @@ MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR ; -RTC .EQU MK4_RTC ; RTC LATCH REGISTER ADR +RTCIO .EQU MK4_RTC ; RTC LATCH REGISTER ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT ; diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index c2146a68..f95428d2 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -42,7 +42,7 @@ N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) ; -RTC .EQU N8_RTC ; RTC LATCH REGISTER ADR +RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR PPIBASE .EQU N8_PPI0 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index 4bed397a..86a086da 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -40,7 +40,7 @@ Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -RTC .EQU $0C ; RTC LATCH REGISTER ADR +RTCIO .EQU $0C ; RTC LATCH REGISTER ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT ; diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index d6a947fc..881d92c6 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -34,7 +34,7 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; -RTC .EQU $C0 ; RTC LATCH REGISTER ADR +RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT ; diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index f63fa549..90879e8e 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -31,7 +31,7 @@ MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; -RTC .EQU $70 ; RTC LATCH REGISTER ADR +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT diff --git a/Source/HBIOS/cfg_sc126.asm b/Source/HBIOS/cfg_sc126.asm index ab25a854..282d0eed 100644 --- a/Source/HBIOS/cfg_sc126.asm +++ b/Source/HBIOS/cfg_sc126.asm @@ -35,7 +35,7 @@ Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -RTC .EQU $0C ; RTC LATCH REGISTER ADR +RTCIO .EQU $0C ; RTC LATCH REGISTER ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT ; diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index a111bafd..46e5bc02 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -31,7 +31,7 @@ MEMMGR .EQU MM_SBC ; MM_[SBC|Z2|N8|Z180]: MEMORY MANAGER MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; -RTC .EQU $70 ; RTC LATCH REGISTER ADR +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 7e3144ce..f29ba8ce 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -34,7 +34,7 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; -RTC .EQU $70 ; RTC LATCH REGISTER ADR +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm index 9b0cff5d..aec35afb 100644 --- a/Source/HBIOS/dsrtc.asm +++ b/Source/HBIOS/dsrtc.asm @@ -85,7 +85,7 @@ ; #IF (DSRTCMODE == DSRTCMODE_STD) ; -DSRTC_BASE .EQU RTC ; RTC PORT +DSRTC_BASE .EQU RTCIO ; RTC PORT ; DSRTC_DATA .EQU %10000000 ; BIT 7 IS RTC DATA OUT DSRTC_CLK .EQU %01000000 ; BIT 6 IS RTC CLOCK (CLK) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 60edda2c..79020f5d 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1466,7 +1466,7 @@ HB_PCPU: ; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE) ; #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2)) - IN A,(RTC) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER + IN A,(RTCIO) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER BIT 6,A ; BIT 6 HAS CONFIG JUMPER STATE JR Z,INITSYS3 ; Z=SHORTED, BYPASS CONSOLE SWITCH #ENDIF @@ -1574,7 +1574,8 @@ PC_INITTBLLEN .EQU (($ - PC_INITTBL) / 2) ;================================================================================================== ; HB_INITTBL: -#IF (SPKENABLE & DSRTCENABLE) +;#IF (SPKENABLE & DSRTCENABLE) +#IF (SPKENABLE) .DW SPK_INIT ; AUDIBLE INDICATOR OF BOOT START #ENDIF #IF (AYENABLE) @@ -2401,7 +2402,7 @@ HB_TIMINT2: ; #IF (PLATFORM == PLT_EZZ80) ; PULSE WATCHDOG - OUT (WDOG),A ; VALUE IS IRRELEVANT + OUT (WDOGIO),A ; VALUE IS IRRELEVANT #ENDIF ; OR $FF ; NZ SET TO INDICATE INT HANDLED @@ -2806,7 +2807,8 @@ SIZ_TERM .EQU $ - ORG_TERM .ECHO " bytes.\n" #ENDIF ; -#IF (SPKENABLE & DSRTCENABLE) +;#IF (SPKENABLE & DSRTCENABLE) +#IF (SPKENABLE) ORG_SPK .EQU $ #INCLUDE "spk.asm" SIZ_SPK .EQU $ - ORG_SPK diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index 093b801d..fcfa6e6a 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -117,9 +117,9 @@ SD_NOPULLUP .EQU TRUE ; ASSUME NO PULLUP ; #IF (SDMODE == SDMODE_JUHA) ; JUHA MINI-BOARD SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION +SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE -SD_INPREG .EQU RTC ; INPUT REGISTER IS RTC +SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC SD_CS .EQU %00000100 ; RTC:2 IS SELECT SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) @@ -128,9 +128,9 @@ SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU) ; #IF (SDMODE == SDMODE_N8) ; UNMODIFIED N8-2511 SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION +SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE -SD_INPREG .EQU RTC ; INPUT REGISTER IS RTC +SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC SD_CS .EQU %00000100 ; RTC:2 IS SELECT SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) @@ -139,7 +139,7 @@ SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU) ; #IF (SDMODE == SDMODE_CSIO) ; N8-2312 SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION +SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE SD_CS .EQU %00000100 ; RTC:2 IS SELECT SD_CNTR .EQU Z180_CNTR @@ -196,7 +196,7 @@ SD_TRDR .EQU Z180_TRDR ; #IF (SDMODE == SDMODE_SC126) ; SC126 SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION +SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED) SD_CS .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD SD_CNTR .EQU Z180_CNTR diff --git a/Source/HBIOS/spk.asm b/Source/HBIOS/spk.asm index ffa1c42e..438b0404 100644 --- a/Source/HBIOS/spk.asm +++ b/Source/HBIOS/spk.asm @@ -6,7 +6,7 @@ SPK_INIT: CALL NEWLINE ; FORMATTING PRTS("SPK: IO=0x$") - LD A,DSRTC_BASE + LD A,RTCIO CALL PRTHEXBYTE CALL SPK_BEEP XOR A @@ -23,7 +23,7 @@ SPK_BEEP: LD B,A SPK_BEEP1: LD A,B - OUT (DSRTC_BASE),A + OUT (RTCIO),A XOR %00000100 LD B,A LD DE,17