diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 374e2937..d10cddfe 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -3986,24 +3986,24 @@ Z280_IVT:
 	.DW	$0000			; INT C MSR
 	.DW	Z280_BADINT		; INT C VECTOR
 	.DW	$0000			; COUNTER/TIMER 0 MSR
-	.DW	$Z280_BADINT		; COUNTER/TIMER 0 VECTOR
+	.DW	Z280_BADINT		; COUNTER/TIMER 0 VECTOR
 	.DW	$0000			; COUNTER/TIMER 1 MSR
-	.DW	$Z280_BADINT		; COUNTER/TIMER 1 VECTOR
+	.DW	Z280_BADINT		; COUNTER/TIMER 1 VECTOR
 	.DW	0, 0			; RESERVED
 	.DW	$0000			; COUNTER/TIMER 2 MSR
-	.DW	$Z280_BADINT		; COUNTER/TIMER 2 VECTOR
+	.DW	Z280_BADINT		; COUNTER/TIMER 2 VECTOR
 	.DW	$0000			; DMA CHANNEL 0 MSR
-	.DW	$Z280_BADINT		; DMA CHANNEL 0 VECTOR
+	.DW	Z280_BADINT		; DMA CHANNEL 0 VECTOR
 	.DW	$0000			; DMA CHANNEL 1 MSR
-	.DW	$Z280_BADINT		; DMA CHANNEL 1 VECTOR
+	.DW	Z280_BADINT		; DMA CHANNEL 1 VECTOR
 	.DW	$0000			; DMA CHANNEL 2 MSR
-	.DW	$Z280_BADINT		; DMA CHANNEL 2 VECTOR
+	.DW	Z280_BADINT		; DMA CHANNEL 2 VECTOR
 	.DW	$0000			; DMA CHANNEL 3 MSR
-	.DW	$Z280_BADINT		; DMA CHANNEL 3 VECTOR
+	.DW	Z280_BADINT		; DMA CHANNEL 3 VECTOR
 	.DW	$0000			; UART RECEIVER MSR
-	.DW	$Z280_BADINT		; UART RECEIVER VECTOR
+	.DW	Z280_BADINT		; UART RECEIVER VECTOR
 	.DW	$0000			; UART TRANSMITTER MSR
-	.DW	$Z280_BADINT		; UART TRANSMITTER VECTOR
+	.DW	Z280_BADINT		; UART TRANSMITTER VECTOR
 	.DW	$0000			; SINGLE STEP TRAP MSR
 	.DW	Z280_SSTEP		; SINGLE STEP TRAP VECTOR
 	.DW	$0000			; BREAK ON HALT TRAP MSR
diff --git a/Source/ver.inc b/Source/ver.inc
index 1f20e876..49dabc01 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.37"
+#DEFINE BIOSVER	"3.1.1-pre.38"
diff --git a/Source/ver.lib b/Source/ver.lib
index 23560d52..973c277f 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.37"
+	db	"3.1.1-pre.38"
 	endm