From dcd4a5a8f1f197fca0c905475b7b33a280e0e117 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 15 Mar 2019 15:16:49 -0700 Subject: [PATCH 1/3] Easy Z80 Platform Make Easy Z80 a separate platform. --- Binary/RomList.txt | 17 +++++- ReadMe.txt | 2 +- Source/Apps/RTC.asm | 6 ++- Source/Apps/Tune/Tune.asm | 8 ++- Source/Apps/XM/xmhb.180 | 2 + Source/CBIOS/ver.inc | 2 +- Source/HBIOS/Build.ps1 | 4 +- Source/HBIOS/Config/EZZ80_std.asm | 9 ++++ Source/HBIOS/Config/RC_ezz80.asm | 23 --------- Source/HBIOS/cfg_ezz80.asm | 86 +++++++++++++++++++++++++++++++ Source/HBIOS/hbios.asm | 8 +-- Source/HBIOS/plt_ezz80.inc | 11 ++++ Source/HBIOS/plt_sbc.inc | 2 +- Source/HBIOS/std.asm | 8 +++ Source/HBIOS/ver.inc | 2 +- Source/ReadMe.txt | 1 + 16 files changed, 154 insertions(+), 37 deletions(-) create mode 100644 Source/HBIOS/Config/EZZ80_std.asm delete mode 100644 Source/HBIOS/Config/RC_ezz80.asm create mode 100644 Source/HBIOS/cfg_ezz80.asm create mode 100644 Source/HBIOS/plt_ezz80.inc diff --git a/Binary/RomList.txt b/Binary/RomList.txt index 5131da59..6f17da80 100644 --- a/Binary/RomList.txt +++ b/Binary/RomList.txt @@ -32,6 +32,7 @@ image to use for each platform: Mark IV MK4_std.rom RC2014 RC_std.rom RC2014 w/ Z180 RC180_std.rom + Easy Z80 EZZ180_std.rom You will find there is one additional ROM image called "UNA_std.rom". This ROM image is an UNA-based RomWBW ROM image. As @@ -50,9 +51,12 @@ the UNA FAT loader for testing. All of the standard ROM Images are configured with: - 512KB ROM Disk - 512KB RAM Disk - - 38.4Kbps baud serial console (RC2014 is determined by hardware) + - 38.4Kbps baud serial console (*) - Auto-discovery of all serial ports +* RC2014 & Easy Z80 serial port speed is determined by hardware + and is typically 115,200 baud. + All hard disk type devices (IDE, PPIDE, CF Card, SD Card) will be automatically assigned two drive letters per device. The drive letters will refer to the first 2 slices of the device. The ASSIGN @@ -69,6 +73,7 @@ not detected at boot, the ROM will simply bypass support appropriately. SBC: + - CPU speed is detected at startup - Includes support for PPIDE/CF Card(s) connected to on-board parallel port. - Includes support for CVDU and VGA3 boards. If detected at @@ -86,6 +91,7 @@ SBC: V2 does not have this issue. ZETA/ZETA2: + - CPU speed is detected at startup - Includes support for on-board floppy disk controller and two attached floppy disks. - Auto-detects ParPortProp and includes support for it if it @@ -96,6 +102,7 @@ ZETA/ZETA2: ParPortProp video and keyboard ports. N8: + - CPU speed is detected at startup - Includes support for on-board floppy disk controller and two attached floppy disks. - Includes support for on-board TMS9918 video and keyboard @@ -104,6 +111,7 @@ N8: assumes a production level N8 board (date code >= 2312). MK4: + - CPU speed is detected at startup - Includes support for on-board IDE port (CF Card via adapter). - Includes support for on-board SD Card port. - Auto-detects PropIO or PropIO V2 and installs associated @@ -113,6 +121,7 @@ MK4: including VT-100/ANSI terminal emulation. RC2014: + - Assumes CPU oscillator of 7.3728 MHz - Requires 512K RAM/ROM module - Auto detects Serial I/O Module (ACIA) and Dual Serial Module (SIO/2). Either one may be used. @@ -123,6 +132,7 @@ RC2014: be enabled in config RC2014 w/ Z180: + - Assumes CPU oscillator of 18.432 MHz - Requires 512K RAM/ROM module - Console attached to Z180 onboard serial ports at 38400 baud - Includes support for Compact Flash Module @@ -130,3 +140,8 @@ RC2014 w/ Z180: - Support for alternative serial modules may be enabled in config - Support for Scott Baker floppy controllers (SMC & WDC) may be enabled in config + +EZZ80: + - Assumes CPU oscillator of 10.000 MHz + - Includes support for on-board SIO + - Includes support for IDE via RC bus diff --git a/ReadMe.txt b/ReadMe.txt index 83b9f503..4f49c114 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.1-pre.11, 2019-03-05 +Version 2.9.1-pre.12, 2019-03-15 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/Apps/RTC.asm b/Source/Apps/RTC.asm index 22e627ad..b61e826d 100644 --- a/Source/Apps/RTC.asm +++ b/Source/Apps/RTC.asm @@ -1070,6 +1070,10 @@ HINIT: LD DE,PLT_RC CP $07 ; RC2014 JR Z,RTC_INIT2 + CP $08 ; RC2014 w/ Z180 + JR Z,RTC_INIT2 + CP $09 ; Easy Z80 + JR Z,RTC_INIT2 ; ; Unknown platform LD DE,PLTERR ; BIOS error message @@ -1654,7 +1658,7 @@ UBTAG .TEXT "UNA UBIOS" PLT_SBC .TEXT ", SBC/Zeta RTC Latch Port 0x70\r\n$" PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$" PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$" -PLT_RC .TEXT ", RC2014 RTC Latch Port 0xC0\r\n$" +PLT_RC .TEXT ", RC2014 RTC Module Latch Port 0xC0\r\n$" ; ; Generic FOR-NEXT loop algorithm diff --git a/Source/Apps/Tune/Tune.asm b/Source/Apps/Tune/Tune.asm index f2c03141..f5f1a7bc 100644 --- a/Source/Apps/Tune/Tune.asm +++ b/Source/Apps/Tune/Tune.asm @@ -87,6 +87,9 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file LD DE,MSGRC ; Message for RC2014 platform CP 7 ; RC2014? JR Z,_SETP ; If so, set ports + LD DE,MSGEZ ; Message for Easy Z80 platform + CP 9 ; Easy Z80? + JR Z,_SETP ; If so, same ports as RC2014 LD HL,$9D9C ; For N8, RSEL=9C, RDAT=9D LD DE,MSGN8 ; Message for N8 platform CP 4 ; N8? @@ -610,9 +613,10 @@ MSGHW .DB "Hardware error, sound chip not detected!",0 MSGNAM .DB "Sound filename invalid (must be .PT2, .PT3, or .MYM)",0 MSGFIL .DB "Sound file not found!",0 MSGSIZ .DB "Sound file too large to load!",0 -MSGRC .DB "RC2014 Ed Brindley Sound Module",0 +MSGRC .DB "RC2014 w/ Ed Brindley Sound Module",0 +MSGEZ .DB "Easy Z80 w/ Ed Brindley Sound Module",0 MSGN8 .DB "RetroBrew N8 Onboard Sound System",0 -MSGSCG .DB "RetroBrew SCG ECB Adapter",0 +MSGSCG .DB "RetroBrew SCG ECB Adapter Sound System",0 MSGTIM .DB ", timer mode",0 MSGDLY .DB ", delay mode",0 MSGPLY .DB "Playing...",0 diff --git a/Source/Apps/XM/xmhb.180 b/Source/Apps/XM/xmhb.180 index f0c19936..3033dc9e 100644 --- a/Source/Apps/XM/xmhb.180 +++ b/Source/Apps/XM/xmhb.180 @@ -133,6 +133,8 @@ MINIT1: JR Z,RCINIT ; Handle RC2014 special CP 8 ; Check for RC2014 w/ Z180 JR Z,ARCINIT ; Handle RC2014 w/ Z180 + CP 9 ; Check for Easy Z80 + JR Z,RCINIT ; Treat same as RC2014 for now ; ; Check for Z180 which implies ASCI serial port LD DE,00202H ; D := 2, E := 2 diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index 00c91863..a444ae6e 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.1-pre.11" +#DEFINE BIOSVER "2.9.1-pre.12" diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index df80130b..c70e6d74 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -28,8 +28,8 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s $Platform = $Platform.ToUpper() while ($true) { - if (($Platform -eq "SBC") -or ($Platform -eq "ZETA") -or ($Platform -eq "ZETA2") -or ($Platform -eq "RC") -or ($Platform -eq "RC180") -or ($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "UNA")) {break} - $Platform = (Read-Host -prompt "Platform [SBC|ZETA|ZETA2|RC|RC180|N8|MK4|UNA]").Trim().ToUpper() + if (($Platform -eq "SBC") -or ($Platform -eq "ZETA") -or ($Platform -eq "ZETA2") -or ($Platform -eq "RC") -or ($Platform -eq "EZZ80") -or ($Platform -eq "RC180") -or ($Platform -eq "N8") -or ($Platform -eq "MK4") -or ($Platform -eq "UNA")) {break} + $Platform = (Read-Host -prompt "Platform [SBC|ZETA|ZETA2|RC|EZZ80|RC180|N8|MK4|UNA]").Trim().ToUpper() } # diff --git a/Source/HBIOS/Config/EZZ80_std.asm b/Source/HBIOS/Config/EZZ80_std.asm new file mode 100644 index 00000000..beed33aa --- /dev/null +++ b/Source/HBIOS/Config/EZZ80_std.asm @@ -0,0 +1,9 @@ +; +;================================================================================================== +; EASY Z80 STANDARD CONFIGURATION +;================================================================================================== +; +#include "cfg_ezz80.asm" +; +CPUOSC .SET 10000000 ; CPU OSC FREQ +DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) diff --git a/Source/HBIOS/Config/RC_ezz80.asm b/Source/HBIOS/Config/RC_ezz80.asm deleted file mode 100644 index 32d9ab11..00000000 --- a/Source/HBIOS/Config/RC_ezz80.asm +++ /dev/null @@ -1,23 +0,0 @@ -; -;================================================================================================== -; RC2014 - EASY Z80 CONFIGURATION -;================================================================================================== -; -#include "cfg_rc.asm" -; -CPUOSC .SET 10000000 ; CPU OSC FREQ -DEFSIOCLK .SET 1843200 ; SIO CLOCK FREQ -DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) -; -SIOENABLE .SET TRUE ; TRUE TO AUTO-DETECT ZILOG SIO/2 -SIOMODE .SET SIOMODE_EZZ80 ; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB, SIOMODE_EZZ80 -ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA -; -FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT -FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC -; -IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE) -IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB -PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE) -; -DSRTCENABLE .SET FALSE ; DS-1302 CLOCK DRIVER diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm new file mode 100644 index 00000000..e41e0c08 --- /dev/null +++ b/Source/HBIOS/cfg_ezz80.asm @@ -0,0 +1,86 @@ +; +;================================================================================================== +; ROMWBW 2.X CONFIGURATION DEFAULTS FOR EASY Z80 +;================================================================================================== +; +; BUILD CONFIGURATION OPTIONS +; +CPUOSC .EQU 10000000 ; CPU OSC FREQ +RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!! +DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) +INTMODE .EQU 1 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2 +; +CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP +VDAEMU .EQU EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...) +; +DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE) +; +HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT +SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER +DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER +DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC +DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) +; +ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT +UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) +UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT +; +SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT +SIOMODE .EQU SIOMODE_EZZ80 ; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP +DEFSIOACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +DEFSIOBCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +DEFSIOCLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIODEBUG .EQU FALSE ;PS +; +VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT +CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT +NECENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT +TMSENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT +VGAENABLE .EQU FALSE ; TRUE FOR VGA VIDEO/KBD SUPPORT +; +SPKENABLE .EQU FALSE ; TRUE FOR RTC LATCH IOBIT SOUND +AYENABLE .EQU FALSE ; TRUE FOR AY PSG SOUND +; +MDENABLE .EQU TRUE ; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED) +MDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE) +; +FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT +FDMODE .EQU FDMODE_RCWDC ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3 +FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE) +FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE) +FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE) +FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY +; +RFENABLE .EQU FALSE ; TRUE FOR RAM FLOPPY SUPPORT +; +IDEENABLE .EQU TRUE ; TRUE FOR IDE SUPPORT +IDEMODE .EQU IDEMODE_RC ; IDEMODE_DIO, IDEMODE_DIDE, IDEMODE_RC +IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE) +IDE8BIT .EQU TRUE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!) +; +PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE) +PPIDEMODE .EQU PPIDEMODE_RC ; PPIDEMODE_SBC, PPPIDEMODE_DIO3, PPIDEMODE_MFP, PPIDEMODE_N8, PPIDEMODE_RC +PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE) +PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!) +; +SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT +SDMODE .EQU SDMODE_PPI ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD +SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE) +SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER +; +PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SUPPORT +; +PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT +PPPSDENABLE .EQU TRUE ; TRUE FOR PARPORTPROP SD SUPPORT +PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE) +PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO) +; +HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT +; +TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL BE ENABLED IF A VDA IS ENABLED +; +BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS) +BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE +BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index a23f8e15..7c18d183 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -290,7 +290,7 @@ HBX_ROM: OUT (MPCL_ROM),A ; SET ROM PAGE SELECTOR RET ; DONE #ENDIF -#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180)) +#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180) | (PLATFORM == PLT_EZZ80)) BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT @@ -715,7 +715,7 @@ HB_START: #ENDIF ; -#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180)) +#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180) | (PLATFORM == PLT_EZZ80)) ; SET PAGING REGISTERS #IFDEF ROMBOOT XOR A @@ -1089,7 +1089,7 @@ INITSYS1: ; IF PLATFORM HAS A CONFIG JUMPER, CHECK TO SEE IF IT IS JUMPERED. ; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE) ; -#IF ((PLATFORM != PLT_N8) & (PLATFORM != PLT_MK4) & (PLATFORM != PLT_RC) & (PLATFORM != PLT_RC180)) +#IF ((PLATFORM != PLT_N8) & (PLATFORM != PLT_MK4) & (PLATFORM != PLT_RC) & (PLATFORM != PLT_RC180) & (PLATFORM != PLT_EZZ80)) IN A,(RTC) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER BIT 6,A ; BIT 6 HAS CONFIG JUMPER STATE JR Z,INITSYS3 ; Z=SHORTED, BYPASS CONSOLE SWITCH @@ -2498,7 +2498,7 @@ HB_WAITSEC: ; RETURN SECS VALUE IN A, LOOP COUNT IN DE LD DE,0 ; INIT LOOP COUNTER HB_WAITSEC1: -#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2)| (PLATFORM == PLT_RC)) +#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RC) | (PLATFORM == PLT_EZZ80)) ; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4 CALL DLY32 CALL DLY8 diff --git a/Source/HBIOS/plt_ezz80.inc b/Source/HBIOS/plt_ezz80.inc new file mode 100644 index 00000000..f848803a --- /dev/null +++ b/Source/HBIOS/plt_ezz80.inc @@ -0,0 +1,11 @@ +; +; EASY Z80 HARDWARE DEFINITIONS +; +MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY) +MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) +; +RTC .EQU $C0 ; RTC PORT address +SIOBASE .EQU $80 ; RC OR SMB SIO DEFAULT diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc index d0795108..341b2401 100644 --- a/Source/HBIOS/plt_sbc.inc +++ b/Source/HBIOS/plt_sbc.inc @@ -19,4 +19,4 @@ MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) ; RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67 -SIOBASE .EQU $B0 ; ZILOG PERIPHERALS DEFAULT ;PS +SIOBASE .EQU $B0 ; ZILOG PERIPHERALS DEFAULT ;PS diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index b670d283..a26c0893 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -35,6 +35,7 @@ PLT_MK4 .EQU 5 ; MARK IV PLT_UNA .EQU 6 ; UNA BIOS PLT_RC .EQU 7 ; RC2014 PLT_RC180 .EQU 8 ; RC2014 W/ Z180 +PLT_EZZ80 .EQU 9 ; EASY Z80 ; #IF (PLATFORM != PLT_UNA) #INCLUDE "hbios.inc" @@ -276,6 +277,9 @@ IVT_PIO3 .EQU 24 #IF (PLATFORM == PLT_RC180) #DEFINE PLATFORM_NAME "RC2014 Z180" #ENDIF +#IF (PLATFORM == PLT_EZZ80) + #DEFINE PLATFORM_NAME "EASY Z80" +#ENDIF ; ; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS ; @@ -303,6 +307,10 @@ IVT_PIO3 .EQU 24 #INCLUDE "plt_rc180.inc" #ENDIF ; +#IF (PLATFORM == PLT_EZZ80) +#INCLUDE "plt_ezz80.inc" +#ENDIF +; ; SETUP DEFAULT CPU SPEED VALUES ; CPUKHZ .EQU CPUOSC / 1000 ; CPU FREQ IN KHZ diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index 00c91863..a444ae6e 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.1-pre.11" +#DEFINE BIOSVER "2.9.1-pre.12" diff --git a/Source/ReadMe.txt b/Source/ReadMe.txt index 81990b2e..6f976949 100644 --- a/Source/ReadMe.txt +++ b/Source/ReadMe.txt @@ -95,6 +95,7 @@ to determine the component of the configuration filename: N8 N8_std.rom Mark IV MK4_std.rom RC2014 RC_std.rom + Easy Z80 EZZ80_std.rom You can use any name you choose for the component of the configuration filename. So, let's say you want to create a custom From 35d3408ab6b22cbec7bafef554bfc65ada73d9cb Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sat, 16 Mar 2019 16:41:37 -0700 Subject: [PATCH 2/3] Floppy Driver Updates Minor fixes in fd.asm. --- Source/HBIOS/fd.asm | 281 ++++++++++++++++++++++---------------------- 1 file changed, 140 insertions(+), 141 deletions(-) diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm index a200c443..dc3d7f9a 100644 --- a/Source/HBIOS/fd.asm +++ b/Source/HBIOS/fd.asm @@ -1391,7 +1391,7 @@ FOP_CMD4: ; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE CP 080H ; LOOKING FOR RQM=1, DIO=0 (FDC READY FOR A BYTE) JR Z,FOP_CMD6 ; GOOD, GO TO SEND BYTE CP 0C0H ; HMMMM... RQM=1 & DIO=1, FDC WANTS TO SEND US DATA, UNEXPECTED - JR Z,FOP_RES ; GO IMMEDIATELY TO RESULTS??? + JP Z,FOP_RES ; GO IMMEDIATELY TO RESULTS??? DJNZ FOP_CMD4 ; LOOP TILL COUNTER EXHAUSTED JP FOP_TOSNDCMD ; COUNTER EXHAUSTED, TIMEOUT / EXIT @@ -1407,28 +1407,149 @@ FOP_CMD6: ; SEND NEXT BYTE FOP_X1: LD A,(FCP_CMD) - LD HL,FOP_RES - PUSH HL - CP CFD_READ - JP Z,FXR_READ + JR Z,FXR_READ CP CFD_WRITE - JP Z,FXR_WRITE + JR Z,FXR_WRITE CP CFD_READID - JP Z,FXR_NULL - RET ; RET ACTUALLY JUST JUMPS RIGHT TO FOP_RES + JR Z,FXR_NULL + JP FOP_RES +;; +;; EXECUTION ROUTINES +;; ; -; RESULTS PHASE +; NULL EXECUTION, NO DATA TO READ/WRITE (USED BY SPECIFY, READID, ETC.) +; +; DO NOTHING, BUT WAIT FOR EXEC B IT TO CLEAR FDC READY. +; LOOP NEEDS TO ALLOW FOR 2 FULL ROTATIONS OF THE DISK +; WHICH IS 400ms AT 300RPM +; +FXR_NULL: + LD BC,$7000 ; LOOP COUNTER, $7000 * 16us = ~485ms +FXR_NULL1: + CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR + IN A,(FDC_MSR) ; GET MSR + AND 0E0H ; ISOLATE RQM/DIO/NDM + CP 0C0H ; WE WANT RQM=1,DIO=1,NDM=0 (READY TO READ A BYTE W/ EXEC INACTIVE) + JP Z,FOP_RES ; EXEC DONE, EXIT CLEAN W/O PULSING TC + ;JP Z,FXR_NULL2 ; *DEBUG* + DEC BC ; DECREMENT COUNTER (16 BIT) + LD A,B ; CHECK FOR ZERO + OR C ; " + JR NZ,FXR_NULL1 ; NOT ZERO YET, KEEP CHECKING + JP FOP_TOEXEC ; TIMEOUT EXIT +;FXR_NULL2: ; *DEBUG* +; CALL PRTHEXBYTE +; CALL PRTHEXWORD +; JP FOP_RES +; +; READ DATA +; +FXR_READ: + HB_DI ; TIME CRITICAL , INTERRUPTS WILL CAUSE I/O ERRS + LD HL,(FD_DSKBUF) ; POINT TO SECTOR BUFFER START + LD DE,(FCD_SECSZ) + ; TIMEOUT COUNTER IS CPU MHZ / 4 (MAKING SURE IT IS AT LEAST 1) +; LD A,(CPUMHZ + 3) / 4 + LD A,(CB_CPUMHZ) ; GET CPU SPEED IN MHZ + ADD A,3 ; ROUND UP + SRL A ; SHIFT RIGHT TWICE + ;SRL A ; ... TO DIVIDE BY 4 + ;INC A ; MAKE SURE RESULT IS AT LEAST 1 + LD (FCD_TO),A ; INIT TIMEOUT COUNTER +FXRR1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER +FXRR2: LD B,0 ; SETUP FOR 256 ITERATIONS +FXRR3: IN A,(FDC_MSR) ; GET MSR + CP 0F0H ; WE WANT RQM=1,DIO=1,NDM=1,BUSY=1 (READY TO RECEIVE A BYTE W/ EXEC ACTIVE) + JR Z,FXRR4 ; GOT IT, DO BYTE READ + DJNZ FXRR3 ; NOT READY, LOOP IF COUNTER NOT ZERO + JR FXRR5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC + +FXRR4: IN A,(FDC_DATA) ; GET PENDING BYTE + LD (HL),A ; STORE IT IN BUFFER + INC HL ; INCREMENT THE BUFFER POINTER + DEC DE ; DECREMENT BYTE COUNT + LD A,D + OR E + JR NZ,FXRR2 ; IF NOT ZERO, REPEAT LOOP + JR FXR_END ; CLEAN EXIT + +FXRR5: ; OUTER LOOP, REALLY ONLY HAPPENS WHEN WAITING FOR FIRST BYTE OR ABORTED + AND 0E0H ; ISOLATE RQM/DIO/NDM + CP 0C0H ; IF RQM=1, DIO=1, NDM=0 (EXECUTION ABORTED) + JR Z,FXR_ABORT ; BAIL OUT TO ERR ROUTINE, FIX: GO TO SPECIFIC ROUTINE FOR THIS??? + DEC C + JR NZ,FXRR2 ; IF NOT ZERO, LOOP SOME MORE + LD A,(FCD_TO) + DEC A + LD (FCD_TO),A + JR NZ,FXRR1 + JR FXR_TO ; OTHERWISE, TIMEOUT ERROR ; -; 1) CHECK FST_RC AND BAIL OUT IF SET??? -; 2) COMPARE MSR CHECKING TO FXR_NULL (WHICH IS RIGHT?) -; 3) WHEN DUMPING FRB, USE THE RECORDED LENGTH??? +; WRITE DATA +; +FXR_WRITE: + HB_DI ; TIME CRITICAL , INTERRUPTS WILL CAUSE I/O ERRS + LD HL,(FD_DSKBUF) ; POINT TO SECTOR BUFFER START + LD DE,(FCD_SECSZ) + ; TIMEOUT COUNTER IS CPU MHZ / 4 (MAKING SURE IT IS AT LEAST 1) +; LD A,(CPUMHZ + 3) / 4 + LD A,(CB_CPUMHZ) ; GET CPU SPEED IN MHZ + ADD A,3 ; ROUND UP + SRL A ; SHIFT RIGHT TWICE + ;SRL A ; ... TO DIVIDE BY 4 + ;INC A ; MAKE SURE RESULT IS AT LEAST 1 + LD (FCD_TO),A +FXRW1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER +FXRW2: LD B,0 ; SETUP FOR 256 ITERATIONS +FXRW3: IN A,(FDC_MSR) ; GET MSR + CP 0B0H ; WE WANT RQM=1,DIO=0,NDM=1,BUSY=1 (READY TO SEND A BYTE W/ EXEC ACTIVE) + JR Z,FXRW4 ; GOT IT, DO BYTE WRITE + DJNZ FXRW3 ; NOT READY, LOOP IF COUNTER NOT ZERO + JR FXRW5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC +FXRW4: LD A,(HL) ; GET NEXT BYTE TO WRITE + OUT (FDC_DATA),A ; WRITE IT + INC HL ; INCREMENT THE BUFFER POINTER + DEC DE ; DECREMENT LOOP COUNTER + LD A,D + OR E + JR NZ,FXRW2 ; IF NOT ZERO, REPEAT LOOP + JR FXR_END ; CLEAN EXIT +FXRW5: ; OUTER LOOP, REALLY ONLY HAPPENS WHEN WAITING FOR FIRST BYTE OR ABORTED + AND 0E0H ; ISOLATE RQM/DIO/NDM + CP 0C0H ; IF RQM=1, DIO=1, NDM=0 (EXECUTION ABORTED) + JR Z,FXR_ABORT ; BAIL OUT TO ERR ROUTINE + DEC C + JR NZ,FXRW2 ; IF NOT ZERO, LOOP SOME MORE + LD A,(FCD_TO) + DEC A + LD (FCD_TO),A + JR NZ,FXRW1 + JR FXR_TO ; OTHERWISE, TIMEOUT ERROR +; +; COMMON COMPLETION CODE FOR ALL EXECUTION ROUTINES +; +FXR_TO: ; TIMEOUT + HB_EI ; INTERRUPTS OK AGAIN + JP FOP_TOEXEC ; EXEC TIMEOUT +; +FXR_ABORT: ; EXECUTION ABORTED + HB_EI ; INTERRUPTS OK AGAIN + JR FOP_RES ; GET RSEULTS, NO NEED TO PULSE TC +; +FXR_END: ; EXECUTION COMPLETED NORMALLY + HB_EI ; INTERRUPTS OK AGAIN +FXR_END2: + CALL FC_PULSETC ; PULSE TC TO END EXECUTION + JR FOP_RES ; GET RSEULTS +; +; RESULTS PHASE ; FOP_RES: LD HL,FRB ; POINT TO RECEIVE BUFFER FOP_RES0: - LD B,0 ; B IS LOOP COUNTER + LD BC,$7000 ; LOOP COUNTER, $7000 * 16us = ~458ms FOP_RES1: CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR @@ -1438,7 +1559,12 @@ FOP_RES1: JR Z,FOP_RES2 ; GOOD, GO TO RECEIVE BYTE CP 080H ; CHECK FOR RQM=1, DIO=0 (NOTHING LEFT) JR Z,FOP_EVAL ; IF NOTHING LEFT, ALL DONE, GO TO EOD/EXIT - DJNZ FOP_RES1 ; LOOP TILL COUNTER EXHAUSTED + DEC BC ; DECREMENT COUNTER (16 BIT) + LD A,B ; CHECK FOR ZERO + OR C ; "" + JR NZ,FOP_RES1 ; LOOP TILL COUNTER EXHAUSTED + ;IN A,(FDC_MSR) ; *DEBUG* + ;CALL PRTHEXBYTE ; *DEBUG* JR FOP_TOGETRES ; OTHERWISE TIMEOUT ERROR FOP_RES2: ; PROCESS NEXT PENDING BYTE @@ -1577,133 +1703,6 @@ FOP_EXIT: CALL FC_PRTRESULTS #ENDIF JP FD_RETRC -; -; EXECUTION ROUTINES -; -FXR_NOP: - RET -; -; NULL EXECUTION, NO DATA TO READ/WRITE (USED BY READID) -; -; DO NOTHING, BUT WAIT FOR FDC READY. LOOP NEEDS TO ALLOW FOR -; 2 FULL ROTATIONS OF THE DISK WHICH IS 400ms AT 300RPM -; -FXR_NULL: - LD BC,$4000 ; LOOP COUNTER, $4000 * 25us = 410ms -FXR_NULL1: - CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR - IN A,(FDC_MSR) ; GET MSR - AND 0E0H ; ISOLATE RQM/DIO/NDM - CP 0C0H ; WE WANT RQM=1,DIO=1,NDM=0 (READY TO READ A BYTE W/ EXEC INACTIVE) - RET Z ; GOT IT, EXIT CLEAN W/O PULSING TC - DEC BC ; DECREMENT COUNTER (16 BIT) - LD A,B ; CHECK FOR ZERO - OR C ; " - JR NZ,FXR_NULL1 ; NOT ZERO YET, KEEP CHECKING - JP FXR_TO ; OTHERWISE, TIMEOUT ERROR - RET -; -; READ DATA -; -FXR_READ: - HB_DI ; TIME CRITICAL , INTERRUPTS WILL CAUSE I/O ERRS - LD HL,(FD_DSKBUF) ; POINT TO SECTOR BUFFER START - LD DE,(FCD_SECSZ) - ; TIMEOUT COUNTER IS CPU MHZ / 4 (MAKING SURE IT IS AT LEAST 1) -; LD A,(CPUMHZ + 3) / 4 - LD A,(CB_CPUMHZ) ; GET CPU SPEED IN MHZ - ADD A,3 ; ROUND UP - SRL A ; SHIFT RIGHT TWICE - SRL A ; ... TO DIVIDE BY 4 - ;INC A ; MAKE SURE RESULT IS AT LEAST 1 - LD (FCD_TO),A ; INIT TIMEOUT COUNTER -FXRR1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER -FXRR2: LD B,0 ; SETUP FOR 256 ITERATIONS -FXRR3: IN A,(FDC_MSR) ; GET MSR - CP 0F0H ; WE WANT RQM=1,DIO=1,NDM=1,BUSY=1 (READY TO RECEIVE A BYTE W/ EXEC ACTIVE) - JR Z,FXRR4 ; GOT IT, DO BYTE READ - DJNZ FXRR3 ; NOT READY, LOOP IF COUNTER NOT ZERO - JR FXRR5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC - -FXRR4: IN A,(FDC_DATA) ; GET PENDING BYTE - LD (HL),A ; STORE IT IN BUFFER - INC HL ; INCREMENT THE BUFFER POINTER - DEC DE ; DECREMENT BYTE COUNT - LD A,D - OR E - JR NZ,FXRR2 ; IF NOT ZERO, REPEAT LOOP - JR FXR_END ; CLEAN EXIT - -FXRR5: ; OUTER LOOP, REALLY ONLY HAPPENS WHEN WAITING FOR FIRST BYTE OR ABORTED - CP 0C0H ; IF RQM=1, DIO=1, NDM=0 (EXECUTION ABORTED) - JR Z,FXR_ABORT ; BAIL OUT TO ERR ROUTINE, FIX: GO TO SPECIFIC ROUTINE FOR THIS??? - DEC C - JR NZ,FXRR2 ; IF NOT ZERO, LOOP SOME MORE - LD A,(FCD_TO) - DEC A - LD (FCD_TO),A - JR NZ,FXRR1 - JR FXR_TO ; OTHERWISE, TIMEOUT ERROR -; -; WRITE DATA -; -FXR_WRITE: - HB_DI ; TIME CRITICAL , INTERRUPTS WILL CAUSE I/O ERRS - LD HL,(FD_DSKBUF) ; POINT TO SECTOR BUFFER START - LD DE,(FCD_SECSZ) - ; TIMEOUT COUNTER IS CPU MHZ / 4 (MAKING SURE IT IS AT LEAST 1) -; LD A,(CPUMHZ + 3) / 4 - LD A,(CB_CPUMHZ) ; GET CPU SPEED IN MHZ - ADD A,3 ; ROUND UP - SRL A ; SHIFT RIGHT TWICE - SRL A ; ... TO DIVIDE BY 4 - ;INC A ; MAKE SURE RESULT IS AT LEAST 1 - LD (FCD_TO),A -FXRW1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER -FXRW2: LD B,0 ; SETUP FOR 256 ITERATIONS -FXRW3: IN A,(FDC_MSR) ; GET MSR - CP 0B0H ; WE WANT RQM=1,DIO=0,NDM=1,BUSY=1 (READY TO SEND A BYTE W/ EXEC ACTIVE) - JR Z,FXRW4 ; GOT IT, DO BYTE WRITE - DJNZ FXRW3 ; NOT READY, LOOP IF COUNTER NOT ZERO - JR FXRW5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC -FXRW4: LD A,(HL) ; GET NEXT BYTE TO WRITE - OUT (FDC_DATA),A ; WRITE IT - INC HL ; INCREMENT THE BUFFER POINTER - DEC DE ; DECREMENT LOOP COUNTER - LD A,D - OR E - JR NZ,FXRW2 ; IF NOT ZERO, REPEAT LOOP - JR FXR_END ; CLEAN EXIT -FXRW5: ; OUTER LOOP, REALLY ONLY HAPPENS WHEN WAITING FOR FIRST BYTE OR ABORTED - CP 0C0H ; IF RQM=1, DIO=1, NDM=0 (EXECUTION ABORTED) - JR Z,FXR_ABORT ; BAIL OUT TO ERR ROUTINE - DEC C - JR NZ,FXRW2 ; IF NOT ZERO, LOOP SOME MORE - LD A,(FCD_TO) - DEC A - LD (FCD_TO),A - JR NZ,FXRW1 - JR FXR_TO ; OTHERWISE, TIMEOUT ERROR -; -FXR_TO: - LD A,FRC_TOEXEC - JR FXR_ERR - -FXR_ABORT: - LD A,FRC_ABORT - JR FXR_ERR -; -; COMMON COMPLETION CODE FOR ALL EXECUTION ROUTINES -; -FXR_ERR: - HB_EI ; INTERRUPTS OK AGAIN - LD (FST_RC),A - RET - -FXR_END: - HB_EI ; INTERRUPTS OK AGAIN - CALL FC_PULSETC - RET #IF (FDTRACE > 0) ; From 580d4ddf259ef5a4572a1031afb07a5600cf1f92 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Tue, 26 Mar 2019 17:01:45 -0700 Subject: [PATCH 3/3] DDT & DDTZ Update DDT & DDTZ updated with versions that use RST 30 instead of RST 38 to avoid conflicts with IM 1 interrupts. --- Doc/ChangeLog.txt | 1 + Doc/DDTZ.doc | 564 ++++++++++++++++++++++++++++++ Source/HBIOS/vdu.asm | 2 +- Source/Images/fd0/u0/DDT.COM | Bin 4864 -> 4864 bytes Source/Images/fd0/u0/DDTZ.COM | Bin 7424 -> 7424 bytes Source/Images/hd0/s0/u0/DDT.COM | Bin 4864 -> 4864 bytes Source/Images/hd0/s0/u0/DDTZ.COM | Bin 7424 -> 7424 bytes Source/Images/hd0/s1/u0/DDT.COM | Bin 4864 -> 4864 bytes Source/Images/hd0/s1/u0/DDTZ.COM | Bin 7424 -> 7424 bytes Source/RomDsk/ROM_1024KB/DDT.COM | Bin 4864 -> 4864 bytes Source/RomDsk/ROM_1024KB/DDTZ.COM | Bin 7424 -> 7424 bytes Source/RomDsk/ROM_512KB/DDT.COM | Bin 4864 -> 4864 bytes Source/RomDsk/ROM_512KB/DDTZ.COM | Bin 7424 -> 7424 bytes 13 files changed, 566 insertions(+), 1 deletion(-) create mode 100644 Doc/DDTZ.doc diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index c6ab07b7..586a8ace 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -24,6 +24,7 @@ Version 2.9.1 - WBW: Refactored DSKY code - S?K: Initial support for Easy Z80 - PMS: Enhance VDU driver to support alternative screen dimensions +- WBW: DDT and DDTZ modified to use RST 30 instead of RST 38 to avoid conflicts with IM 1 interrupts Version 2.9.0 ------------- diff --git a/Doc/DDTZ.doc b/Doc/DDTZ.doc new file mode 100644 index 00000000..46da2d3b --- /dev/null +++ b/Doc/DDTZ.doc @@ -0,0 +1,564 @@ + + DDTZ v2.7 + by C.B. Falconer + edited by George A. Havach + +Introduction: +============ +DDTZ v2.7 is a complete replacement for DDT, Digital Research's +famous Dynamic Debugging Tool, with improved functionality, bug +extermination, and full Z80 support. In general, DDTZ is fully +compatible with the original utility, but it has extra and +extended commands and many fewer quirks. All Z80-specific +instructions can be (dis)assembled, though in Intel rather then +Zilog format. Furthermore, DDTZ will correctly trace ('T' and 'U' +commands) both 8080 and Z80 instructions, depending on which CPU +is operating. On startup, the program announces which CPU it is +running on. + +DDTZ v2.7 now handles the 64180 added opcodes. It does NOT test +for a 64180 CPU, since this cannot be done without executing +illegal Z80 instructions, which in turn will crash some +simulators. However v2.7 does not execute any 64180 instructions +internally, only in the subject program. + +This issue supplies the "M" version assembled, to avoid errors +when switching between MSDOS and CPM systems. The command table +is updated accordingly. Most CPM users are also MSDOS users, but +not vice-versa. + +The program is invoked by typing + + ddtz +or + ddtz [d:]filespec + +In the second form, DDTZ will load the specified file into +memory starting at 0100H, unless it's a .HEX file that sets its +own load address. Besides reporting the NEXT free address and +the PC (program counter) after a successful load, DDTZ also shows +the number of memory pages needed for a SAVE. Instead of having +to write all this down, just use the 'X' command at any time to +redisplay these three values for the current application. + +NOTE: loading more code above the NEXT pointer revises these + values. + +As in DDT, when a program is loaded above the area holding the +'A' and 'U' (and now 'W') command code, these commands are +disabled, and the extra memory is released to the user. Thus, +DDTZ can occupy as little as 3K total memory space. Unlike DDT, +however, DDTZ will not overwrite itself or the system on program +loads (except .HEX files). + +At initialization, the stack pointer (SP) points to a return to +DDTZ, just like for the CCP. Thus, programs that normally return +to the CCP will be returned to DDTZ. The 'B' command +reinitializes this condition. + + +The intercept vector copies the BDOS version number, etc., so +an object program does not know that DDTZ is running (except +for BIOS-BDOS vector size). Thus, programs that check the version +number should execute correctly under DDTZ. + +All input parameters can now be entered in any of three formats: + + (1) hexadecimal (as in DDT), + (2) decimal, by adding a leading '#' character, + (3) ASCII, by enclosing between either single or double + quotes; either one or two characters are allowed. + +Leading blanks in command lines and parameters are absorbed. +Either a comma or a (single) space is a valid delimiter. +Either uppercase or lowercase input is accepted. + +The default command (for anything not otherwise recognizable) +is 'H'. This allows convenient calculation, along with the other +features described below. So, to convert a number, just enter +it! + +As in DDT, the prompt character is '-', and the only error +message is the query ('?'), which generally kicks you back to +command mode. + +New Commands (Over DDT): +======================= + +NOTE: letters in parenthesis, e.g. "(U)", show the equivalent + command for DDTZM version (compatible with MSDOS debug). + + @ Sets or shows (with no parameter) the internally stored + "base" value. Also used with the 'S' and 'D' commands as + an optional parameter (though without the '@') to display + memory from an arbitrary base marker (offset). When set to + zero (the default), it does not affect any screen displays. + + B B)egin: resets the USER stack pointer to its initial value, + such that any program that exits by an RET will return to + DDTZ. DDTZ provides a default stack space of + approximately 24 bytes for user programs. + + C C)ompare first_address,last_address,against_address: shows + all the byte differences between two memory areas, in the + format + + XXXX aa YYYY bb + + where XXXX and YYYY are the comparative memory addresses, + and aa and bb are the corresponding byte values. Can be + used to verify the identity of two files by first + loading them into different memory areas with the 'R' + command (see below). + + + W Write: stores the modified memory area to disk under the + (K) filename specified by the 'I' command, overwriting the + original file from which it was loaded (the user is queried + before doing so). By default, the image of memory from + 0100H through the "NEXT" value -1 is saved. "K first_addr, + last_address" overrides this and allows writing ANY memory + area to a file. Almost a necessity for CPM 3.0 (no SAVE!). + K)eep on DDTZ + + X eXamine: redisplays the "NEXT PC SAVE" report at any time. + (Q) Q)uery size on DDTZ. + + S S)earch first_address, last_addr, value: searches the + (W) specified memory area for the value (a 16-bit word, not a + byte) and shows the locations of all such. Very useful for + finding CALL's or JMP's to a particular address, etc. + W)here on DDTZ + + Y Y)our_option parm1,parm2,address: executes an arbitrary + routine at the specified address, with the BC and DE + registers set to parm1 and parm2, respectively. + + Z Displays (but does not alter) the Z80's alternate register + set, including the index registers (disabled if running on + an 8080). On Z80's, automatically included as the last + part of the display by the 'X' command. + + +Based (Offset) Displays: +======================= + +The 'D' and 'E' commands can use a stored base value (offset), +as set by the '@' command. The current @ value may be +overridden for a single execution of these commands by adding the +base as an extra parameter in the command line. The effect is +to add this value to the first/last address and display +accordingly. The address listing on the left becomes XXXX:YYYY, +where XXXX is the offset address and YYYY is the actual memory +address being displayed. For example, if you have a data area +located at 42B7H and wish to preserve easy access, just enter +"@42b7". Now, "d0,3f" will dump memory starting at 4237H. + + +Further Changes from DDT: +======================== + + A A)ssemble now accepts the full Z80 as well as 8080 + instruction set, although it expects them in Intel rather + than Zilog format (see notes below under the 'L' + command). When in doubt, see the mnemnonic list below. + + D D)isplay or D)ump will accept an optional third parameter + to set the base value for a single execution only. Format + has been cleaned up. + + H H)ex_arithmetic on two values also shows their + difference in decimal. With only one value, converts to + hexadecimal, decimal, and ASCII (low-order byte only). + + + N N)ame now allows drive specification (d:...) and sets up + (I) the complete command line, including both FCB's (at + addresses 005CH and 006CH). The tail (stored at 0081H up) + is NOT upshifted. + I)nput on DDTZ + + U U)nassemble now displays the raw hexcode, especially handy + (L) when examining non-code areas. Intel (8080 style) mnemonics + are used, so some disassembled instructions may look + strange. E.g., the Z80's 'IN B,(C)' and 'OUT (C),B' become + 'INP B' and 'OUTP B', respectively; 'LD (nnnn),BC' becomes + 'SBCD nnnn', 'ADD IX, BC' becomes 'DADX B', and 'JP (IX)' + becomes 'PCIX'. + L)ist on DDTZ + + L L)oad now permits loading a file into memory with an + (R) offset, which is added to the default load address of + 0100H. When reading in a .HEX file with a preset bias, + the 'R' command will not transfer control to an invalid + execution point. Another execution of the 'R' command will + reread the input file, e.g.: + + n blah + l + ...modify the code and generally mess about... + l + + The original file is reloaded, and the modifications are + removed. + R)ead on DDTZ + + E E)nter, like D)isplay, now accepts an optional second + (S) parameter to set the base value for a single execution + only. + S)ubstitute or S)et on DDTZ + + T T)rap/trace on termination now shows the complete CPU + state. Traps and traces no longer lock up when a user RST + 7 instruction is executed. Tracing of BDOS/BIOS calls is + heavily trun cated, avoiding clutter and preventing system + crashes. + +NOTE: Most of the UNDOCUMENTED Z80 op-codes are handled. Others + can crash the system. + + R R)egisters also shows what two-byte values the HL and SP + (X) registers are actually pointing to. On Z80's, displays the + alternate register set. + eX)amine on DDTZ + +NOTE: Any use of the 'W' or 'L' command resets the system DMA + transfer address to the standard default value of 0080H. + + +; This is the output of DDTZ when disassembling OPTYPE.TRY +NOP LDA 06A4 MOV M,H +LXI B,06A4 DCX SP MOV M,L +STAX B INR A HLT +INX B DCR A MOV M,A +INR B MVI A,20 MOV A,B +DCR B CMC MOV A,C +MVI B,20 MOV B,B MOV A,D +RLC MOV B,C MOV A,E +EXAF MOV B,D MOV A,H +DAD B MOV B,E MOV A,L +LDAX B MOV B,H MOV A,M +DCX B MOV B,L MOV A,A +INR C MOV B,M ADD B +DCR C MOV B,A ADD C +MVI C,20 MOV C,B ADD D +RRC MOV C,C ADD E +DJNZ 0134 MOV C,D ADD H +LXI D,06A4 MOV C,E ADD L +STAX D MOV C,H ADD M +INX D MOV C,L ADD A +INR D MOV C,M ADC B +DCR D MOV C,A ADC C +MVI D,20 MOV D,B ADC D +RAL MOV D,C ADC E +JR 0134 MOV D,D ADC H +DAD D MOV D,E ADC L +LDAX D MOV D,H ADC M +DCX D MOV D,L ADC A +INR E MOV D,M SUB B +DCR E MOV D,A SUB C +MVI E,20 MOV E,B SUB D +RAR MOV E,C SUB E +JRNZ 0134 MOV E,D SUB H +LXI H,06A4 MOV E,E SUB L +SHLD 06A4 MOV E,H SUB M +INX H MOV E,L SUB A +INR H MOV E,M SBB B +DCR H MOV E,A SBB C +MVI H,20 MOV H,B SBB D +DAA MOV H,C SBB E +JRZ 0134 MOV H,D SBB H +DAD H MOV H,E SBB L +LHLD 06A4 MOV H,H SBB M +DCX H MOV H,L SBB A +INR L MOV H,M ANA B +DCR L MOV H,A ANA C +MVI L,20 MOV L,B ANA D +CMA MOV L,C ANA E +JRNC 0134 MOV L,D ANA H +LXI SP,06A4 MOV L,E ANA L +STA 06A4 MOV L,H ANA M +INX SP MOV L,L ANA A +INR M MOV L,M XRA B +DCR M MOV L,A XRA C +MVI M,20 MOV M,B XRA D +STC MOV M,C XRA E +JRC 0134 MOV M,D XRA H +DAD SP MOV M,E XRA L + + +XRA M JPE 06A4 SLAR M +XRA A XCHG SLAR A +ORA B CPE 06A4 SRAR B +ORA C XRI 20 SRAR C +ORA D RST 5 SRAR D +ORA E RP SRAR E +ORA H POP PSW SRAR H +ORA L JP 06A4 SRAR L +ORA M DI SRAR M +ORA A CP 06A4 SRAR A +CMP B PUSH PSW SLLR B +CMP C ORI 20 SLLR C +CMP D RST 6 SLLR D +CMP E RM SLLR E +CMP H SPHL SLLR H +CMP L JM 06A4 SLLR L +CMP M EI SLLR M +CMP A CM 06A4 SLLR A +RNZ CPI 20 SRLR B +POP B RST 7 SRLR C +JNZ 06A4 RLCR B SRLR D +JMP 06A4 RLCR C SRLR E +CNZ 06A4 RLCR D SRLR H +PUSH B RLCR E SRLR L +ADI 20 RLCR H SRLR M +RST 0 RLCR L SRLR A +RZ RLCR M BIT 0,B +RET RLCR A BIT 0,C +JZ 06A4 RRCR B BIT 0,D +CZ 06A4 RRCR C BIT 0,E +CALL 06A4 RRCR D BIT 0,H +ACI 20 RRCR E BIT 0,L +RST 1 RRCR H BIT 0,M +RNC RRCR L BIT 0,A +POP D RRCR M BIT 1,B +JNC 06A4 RRCR A BIT 1,C +OUT 20 RALR B BIT 1,D +CNC 06A4 RALR C BIT 1,E +PUSH D RALR D BIT 1,H +SUI 20 RALR E BIT 1,L +RST 2 RALR H BIT 1,M +RC RALR L BIT 1,A +EXX RALR M BIT 2,B +JC 06A4 RALR A BIT 2,C +IN 20 RARR B BIT 2,D +CC 06A4 RARR C BIT 2,E +SBI 20 RARR D BIT 2,H +RST 3 RARR E BIT 2,L +RPO RARR H BIT 2,M +POP H RARR L BIT 2,A +JPO 06A4 RARR M BIT 3,B +XTHL RARR A BIT 3,C +CPO 06A4 SLAR B BIT 3,D +PUSH H SLAR C BIT 3,E +ANI 20 SLAR D BIT 3,H +RST 4 SLAR E BIT 3,L +RPE SLAR H BIT 3,M +PCHL SLAR L BIT 3,A + + +BIT 4,B RES 3,D SET 2,H +BIT 4,C RES 3,E SET 2,L +BIT 4,D RES 3,H SET 2,M +BIT 4,E RES 3,L SET 2,A +BIT 4,H RES 3,M SET 3,B +BIT 4,L RES 3,A SET 3,C +BIT 4,M RES 4,B SET 3,D +BIT 4,A RES 4,C SET 3,E +BIT 5,B RES 4,D SET 3,H +BIT 5,C RES 4,E SET 3,L +BIT 5,D RES 4,H SET 3,M +BIT 5,E RES 4,L SET 3,A +BIT 5,H RES 4,M SET 4,B +BIT 5,L RES 4,A SET 4,C +BIT 5,M RES 5,B SET 4,D +BIT 5,A RES 5,C SET 4,E +BIT 6,B RES 5,D SET 4,H +BIT 6,C RES 5,E SET 4,L +BIT 6,D RES 5,H SET 4,M +BIT 6,E RES 5,L SET 4,A +BIT 6,H RES 5,M SET 5,B +BIT 6,L RES 5,A SET 5,C +BIT 6,M RES 6,B SET 5,D +BIT 6,A RES 6,C SET 5,E +BIT 7,B RES 6,D SET 5,H +BIT 7,C RES 6,E SET 5,L +BIT 7,D RES 6,H SET 5,M +BIT 7,E RES 6,L SET 5,A +BIT 7,H RES 6,M SET 6,B +BIT 7,L RES 6,A SET 6,C +BIT 7,M RES 7,B SET 6,D +BIT 7,A RES 7,C SET 6,E +RES 0,B RES 7,D SET 6,H +RES 0,C RES 7,E SET 6,L +RES 0,D RES 7,H SET 6,M +RES 0,E RES 7,L SET 6,A +RES 0,H RES 7,M SET 7,B +RES 0,L RES 7,A SET 7,C +RES 0,M SET 0,B SET 7,D +RES 0,A SET 0,C SET 7,E +RES 1,B SET 0,D SET 7,H +RES 1,C SET 0,E SET 7,L +RES 1,D SET 0,H SET 7,M +RES 1,E SET 0,L SET 7,A +RES 1,H SET 0,M DADX B +RES 1,L SET 0,A DADX D +RES 1,M SET 1,B LXI X,06A4 +RES 1,A SET 1,C SIXD 06A4 +RES 2,B SET 1,D INX X +RES 2,C SET 1,E DADX X +RES 2,D SET 1,H LIXD 06A4 +RES 2,E SET 1,L DCX X +RES 2,H SET 1,M INR [X+05] +RES 2,L SET 1,A DCR [X+05] +RES 2,M SET 2,B MVI [X+05],20 +RES 2,A SET 2,C DADX SP +RES 3,B SET 2,D MOV B,[X+05] +RES 3,C SET 2,E MOV C,[X+05] + + +MOV D,[X+05] DSBC B DADY B +MOV E,[X+05] SBCD 06A4 DADY D +MOV H,[X+05] NEG LXI Y,06A4 +MOV L,[X+05] RETN SIYD 06A4 +MOV [X+05],B IM0 INX Y +MOV [X+05],C LDIA DADY Y +MOV [X+05],D INP C LIYD 06A4 +MOV [X+05],E OUTP C DCX Y +MOV [X+05],H DADC B INR [Y+05] +MOV [X+05],L LBCD 06A4 DCR [Y+05] +MOV [X+05],A RETI MVI [Y+05],2 +MOV A,[X+05] LDRA DADY SP +ADD [X+05] INP D MOV B,[Y+05] +ADC [X+05] OUTP D MOV C,[Y+05] +SUB [X+05] DSBC D MOV D,[Y+05] +SBB [X+05] SDED 06A4 MOV E,[Y+05] +ANA [X+05] IM1 MOV H,[Y+05] +XRA [X+05] LDAI MOV L,[Y+05] +ORA [X+05] INP E MOV [Y+05],B +CMP [X+05] OUTP E MOV [Y+05],C +POP X DADC D MOV [Y+05],D +XTIX LDED 06A4 MOV [Y+05],E +PUSH X IM2 MOV [Y+05],H +PCIX LDAR MOV [Y+05],L +SPIX INP H MOV [Y+05],A +RLCR [X+05] OUTP H MOV A,[Y+05] +RRCR [X+05] DSBC H ADD [Y+05] +RALR [X+05] shld 06A4 ADC [Y+05] +RARR [X+05] RRD SUB [Y+05] +SLAR [X+05] INP L SBB [Y+05] +SRAR [X+05] OUTP L ANA [Y+05] +SRLR [X+05] DADC H XRA [Y+05] +BIT 0,[X+05] lhld 06A4 ORA [Y+05] +BIT 1,[X+05] RLD CMP [Y+05] +BIT 2,[X+05] INP M POP Y +BIT 3,[X+05] OUTP M XTIY +BIT 4,[X+05] DSBC SP PUSH Y +BIT 5,[X+05] SSPD 06A4 PCIY +BIT 6,[X+05] INP A SPIY +BIT 7,[X+05] OUTP A RLCR [Y+05] +RES 0,[X+05] DADC SP RRCR [Y+05] +RES 1,[X+05] LSPD 06A4 RALR [Y+05] +RES 2,[X+05] LDI RARR [Y+05] +RES 3,[X+05] CCI SLAR [Y+05] +RES 4,[X+05] INI SRAR [Y+05] +RES 5,[X+05] OTI SRLR [Y+05] +RES 6,[X+05] LDD BIT 0,[Y+05] +RES 7,[X+05] CCD BIT 1,[Y+05] +SET 0,[X+05] IND BIT 2,[Y+05] +SET 1,[X+05] OTD BIT 3,[Y+05] +SET 2,[X+05] LDIR BIT 4,[Y+05] +SET 3,[X+05] CCIR BIT 5,[Y+05] +SET 4,[X+05] INIR BIT 6,[Y+05] +SET 5,[X+05] OTIR BIT 7,[Y+05] +SET 6,[X+05] LDDR RES 0,[Y+05] +SET 7,[X+05] CCDR RES 1,[Y+05] +INP B INDR RES 2,[Y+05] +OUTP B OTDR RES 3,[Y+05] + + +RES 4,[Y+05] SET 0,[Y+05] SET 4,[Y+05] +RES 5,[Y+05] SET 1,[Y+05] SET 5,[Y+05] +RES 6,[Y+05] SET 2,[Y+05] SET 6,[Y+05] +RES 7,[Y+05] SET 3,[Y+05] SET 7,[Y+05] + +; These are the result of disassembling 64180OPS.TRY +; These opcodes are available ONLY on the 64180 CPU +; DDTZ will both assemble and disassemble these. +IN0 B,20 TST E MLT B +OUT0 20,B IN0 H,20 MLT D +TST B OUT0 20,H TSTI 20 +IN0 C,20 TST H MLT H +OUT0 20,C IN0 L,20 TSIO 20 +TST C OUT0 20,L SLP +IN0 D,20 TST L MLT SP +OUT0 20,D TST M OTIM +TST D IN0 A,20 OTDM +IN0 E,20 OUT0 20,A OIMR +OUT0 20,E TST A ODMR + +; The following are UNDOCUMENTED z80 opcodes from XTDOPS.TRY. +; DDTZ will disassemble these, but will not assemble them. +; They use xh/xl (or yh/yl) as separate byte registers. +; Use these at your own risk. +INRX H ACXR H MOVY H,B +DCRX H ACXR L MOVY H,C +MVIX H,20 SUXR H MOVY H,D +INRX L SUXR L MOVY H,E +DCRX L SBXR H MOVY H,A +MVIX L,20 SBXR L MOVY L,B +MOVX B,H NDXR H MOVY L,C +MOVX B,L NDXR L MOVY L,D +MOVX C,H XRXR H MOVY L,E +MOVX C,L XRXR L MOVY L,A +MOVX D,H ORXR H MOVY A,H +MOVX D,L ORXR L MOVY A,L +MOVX E,H CPXR H ADYR H +MOVX E,L CPXR L ADYR L +MOVX H,B INRY H ACYR H +MOVX H,C DCRY H ACYR L +MOVX H,D MVIY H,20 SUYR H +MOVX H,E INRY L SUYR L +MOVX H,A DCRY L SBYR H +MOVX L,B MVIY L,20 SBYR L +MOVX L,C MOVY B,H NDYR H +MOVX L,D MOVY B,L NDYR L +MOVX L,E MOVY C,H XRYR H +MOVX L,A MOVY C,L XRYR L +MOVX A,H MOVY D,H ORYR H +MOVX A,L MOVY D,L ORYR L +ADXR H MOVY E,H CPYR H +ADXR L MOVY E,L CPYR L + + +Command Summary: +=============== + +DDTZM command DDTZ command +============= ============ +@ (base) +A)ssemble first_address A +B)egin {i.e., initialize stack and return} B +C)ompare first_address,last_address,against_address C +D)ump first_address[,last_address[,base]] D +E)nter_in_memory first_address[,base] S)ubstitute +F)ill first_address,last_address,value F +G)o_to [address][,trap1[,trap2]] G +H)ex_arithmetic value1(,value2) H +L)oad_file (offset) R)ead +M)ove first_address,last_address,destination M +N)nput FCBs_command_line I)nput +Q)uit (not avail) +R)egister examine/change [register|flag] X)amine +S)earch first_address,last_address,word W)hereis +T)race_execution [count] T + Untrace_execution [count] (i.e. do count instr) U)ntrace +U)nassemble_code first_address[,last_address] L)ist code +W)rite [first_address,last_address] K)eep +X)amine {i.e. display memory parameters for application} Q)uery +Y)our_option BC:=parm1,DE:=parm2,call_address Y +Z)80_register_display Z + + +If you find this program useful, contributions will be gratefully +accepted and will encourage further development and release of +useful CPM programs. My practice is to include source. + +C.B. Falconer +680 Hartford Turnpike, +Hamden, Conn. 06517 (203) 281-1438 + +DDTZ and its associated documentation and other files are +copyright (c) 1980-1988 by C.B. Falconer. They may be freely +copied and used for non-commercial purposes ONLY. +τΩ \ No newline at end of file diff --git a/Source/HBIOS/vdu.asm b/Source/HBIOS/vdu.asm index 0d140608..9a65055b 100644 --- a/Source/HBIOS/vdu.asm +++ b/Source/HBIOS/vdu.asm @@ -74,7 +74,7 @@ VDU_INIT: LD A,VDU_RAMRD CALL PRTHEXBYTE - PRTS(" MODE= $") ; OUTPUT DISPLAY FORMAT + PRTS(" MODE=$") ; OUTPUT DISPLAY FORMAT LD A,DROWS CALL PRTDECB PRTS("X$") diff --git a/Source/Images/fd0/u0/DDT.COM b/Source/Images/fd0/u0/DDT.COM index 83f8603f93e61057d63c994de083a1fd83e29781..70e4ebfe97229d3ed348abb9632a2d40a663e8b6 100644 GIT binary patch delta 41 tcmZorYf#(poSof(L9vZZ$#C;K_UDX@-#1_56k!EYulYDZys!M+%m6Vt4!{5a delta 41 tcmZorYf#(poSof*L9vZZ$#U~M_UDX@|2JRb6k!EYulYDZys!M+%m6e|4(I>? diff --git a/Source/Images/fd0/u0/DDTZ.COM b/Source/Images/fd0/u0/DDTZ.COM index e30a34c0c31b568fb7d3e9ece2d375524b8905b6..4f6eca6bd9731624a7ed8e0cf8cf9c2137e5b9ff 100644 GIT binary patch delta 37 rcmZp$YOvZ+E5P`DbDh9rHXxNG{-2TEfI;zysFLC449RKCOzrIe5ULGX delta 37 rcmZp$YOvZ+E5P`FbDh9rHXxNG{-2TEf? diff --git a/Source/Images/hd0/s0/u0/DDTZ.COM b/Source/Images/hd0/s0/u0/DDTZ.COM index e30a34c0c31b568fb7d3e9ece2d375524b8905b6..4f6eca6bd9731624a7ed8e0cf8cf9c2137e5b9ff 100644 GIT binary patch delta 37 rcmZp$YOvZ+E5P`DbDh9rHXxNG{-2TEfI;zysFLC449RKCOzrIe5ULGX delta 37 rcmZp$YOvZ+E5P`FbDh9rHXxNG{-2TEf? diff --git a/Source/Images/hd0/s1/u0/DDTZ.COM b/Source/Images/hd0/s1/u0/DDTZ.COM index e30a34c0c31b568fb7d3e9ece2d375524b8905b6..4f6eca6bd9731624a7ed8e0cf8cf9c2137e5b9ff 100644 GIT binary patch delta 37 rcmZp$YOvZ+E5P`DbDh9rHXxNG{-2TEfI;zysFLC449RKCOzrIe5ULGX delta 37 rcmZp$YOvZ+E5P`FbDh9rHXxNG{-2TEf? diff --git a/Source/RomDsk/ROM_1024KB/DDTZ.COM b/Source/RomDsk/ROM_1024KB/DDTZ.COM index e30a34c0c31b568fb7d3e9ece2d375524b8905b6..4f6eca6bd9731624a7ed8e0cf8cf9c2137e5b9ff 100644 GIT binary patch delta 37 rcmZp$YOvZ+E5P`DbDh9rHXxNG{-2TEfI;zysFLC449RKCOzrIe5ULGX delta 37 rcmZp$YOvZ+E5P`FbDh9rHXxNG{-2TEf? diff --git a/Source/RomDsk/ROM_512KB/DDTZ.COM b/Source/RomDsk/ROM_512KB/DDTZ.COM index e30a34c0c31b568fb7d3e9ece2d375524b8905b6..4f6eca6bd9731624a7ed8e0cf8cf9c2137e5b9ff 100644 GIT binary patch delta 37 rcmZp$YOvZ+E5P`DbDh9rHXxNG{-2TEfI;zysFLC449RKCOzrIe5ULGX delta 37 rcmZp$YOvZ+E5P`FbDh9rHXxNG{-2TEf