diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 3cd7910b..900bde81 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -262,16 +262,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	2		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	2		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	2		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$88		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
diff --git a/Source/HBIOS/ch.asm b/Source/HBIOS/ch.asm
index 0bfb877d..b7f52caa 100644
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
@@ -236,6 +236,7 @@ CH_INIT4:
 CH_CMD:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
 	INC	C			; BUMP TO CMD PORT
+	EZ80_IO
 	OUT	(C),A			; SEND COMMAND
 	CALL	CH_NAP			; *DEBUG*
 	RET
@@ -245,6 +246,7 @@ CH_CMD:
 CH_STAT:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
 	INC	C			; BUMP TO CMD PORT
+	EZ80_IO
 	IN	A,(C)			; READ STATUS
 	RET
 ;
@@ -252,6 +254,7 @@ CH_STAT:
 ;
 CH_RD:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	IN	A,(C)			; READ BYTE
 	RET
 ;
@@ -259,6 +262,7 @@ CH_RD:
 ;
 CH_WR:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	OUT	(C),A			; READ BYTE
 	RET
 ;
diff --git a/Source/HBIOS/chsd.asm b/Source/HBIOS/chsd.asm
index c4b38194..e1a7e81d 100644
--- a/Source/HBIOS/chsd.asm
+++ b/Source/HBIOS/chsd.asm
@@ -196,6 +196,7 @@ CHSD_READ1:
 #IF (CHSD_FASTIO)
 	LD	B,A			; BYTE COUNT TO READ
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO ;!! NOT SUPPORT INIR YET
 	INIR				; DO IT FAST
 #ELSE
 	LD	B,A			; SAVE IT
@@ -263,6 +264,7 @@ CHSD_WRITE1:
 #IF (CHSD_FASTIO)
 	LD	B,A			; BYTE COUNT TO WRITE
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO ;!! NOT SUPPORT OTIR YET
 	OTIR				; DO IT FAST
 #ELSE
 	LD	B,A			; SAVE IT