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Merge pull request #74 from b1ackmai1er/master

ppide update to begin support for multiple interfaces.
pull/90/head
Wayne Warthen 6 years ago
committed by GitHub
parent
commit
bd21224a9d
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
  1. 16
      Source/HBIOS/Build.ps1
  2. 1
      Source/HBIOS/cfg_dyno.asm
  3. 1
      Source/HBIOS/cfg_master.asm
  4. 1
      Source/HBIOS/cfg_mk4.asm
  5. 1
      Source/HBIOS/cfg_n8.asm
  6. 1
      Source/HBIOS/cfg_rcz180.asm
  7. 1
      Source/HBIOS/cfg_rcz80.asm
  8. 1
      Source/HBIOS/cfg_sbc.asm
  9. 1
      Source/HBIOS/cfg_scz180.asm
  10. 1234
      Source/HBIOS/game.asm
  11. 2
      Source/HBIOS/imgpad0.asm
  12. 299
      Source/HBIOS/ppide.asm
  13. 1
      Source/HBIOS/romldr.asm
  14. 5
      Source/HBIOS/std.asm

16
Source/HBIOS/Build.ps1

@ -170,14 +170,10 @@ Copy-Item '..\Forth\camel80.bin' 'camel80.bin'
Copy-Item '..\Fonts\font*.asm' '.'
# Assemble individual components. Note in the case of UNA, there is less to build.
Asm 'dbgmon'
Asm 'prefix'
Asm 'romldr'
Asm 'eastaegg'
Asm 'nascom'
Asm 'tastybasic'
Asm 'imgpad'
Asm 'imgpad0'
#
$RomComponentList = "dbgmon", "prefix", "romldr", "eastaegg", "nascom", "tastybasic", "game", "imgpad", "imgpad0"
ForEach ($RomComponentName in $RomComponentList) {Asm $RomComponentName}
if ($Platform -ne "UNA")
{
Asm 'hbios' '-dROMBOOT' -Output 'hbios_rom.bin' -List 'hbios_rom.lst'
@ -201,7 +197,7 @@ Concat 'prefix.bin','zsys.bin' 'zsys.sys'
# Build 32K OS chunk containing the loader, debug monitor, and OS images
Concat 'romldr.bin', 'eastaegg.bin','dbgmon.bin', 'cpm.bin', 'zsys.bin' osimg.bin
Concat 'camel80.bin', 'nascom.bin', 'tastybasic.bin', 'imgpad0.bin' osimg1.bin
Concat 'camel80.bin', 'nascom.bin', 'tastybasic.bin', 'game.bin', 'imgpad0.bin' osimg1.bin
#
# Now the ROM disk image is created. This is done by starting with a
# blank ROM disk image of the correct size, then cpmtools is used to
@ -249,5 +245,5 @@ else
Concat 'hbios_img.bin','osimg.bin' $ImgFile
}
# Remove the temprary working ROM disk file
# Remove the temporary working ROM disk file
Remove-Item $RomDiskFile

1
Source/HBIOS/cfg_dyno.asm

@ -113,6 +113,7 @@ PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_DYNO ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_master.asm

@ -172,6 +172,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_NONE ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_mk4.asm

@ -127,6 +127,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_n8.asm

@ -130,6 +130,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_rcz180.asm

@ -133,6 +133,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_rcz80.asm

@ -137,6 +137,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_sbc.asm

@ -130,6 +130,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1
Source/HBIOS/cfg_scz180.asm

@ -128,6 +128,7 @@ PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
PPICNT .EQU 1 ; PPIDE: NUMBER OF 8255 PPI INTERFACES
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]

1234
Source/HBIOS/game.asm

File diff suppressed because it is too large

2
Source/HBIOS/imgpad0.asm

@ -1,6 +1,6 @@
#INCLUDE "std.asm"
;
SLACK .EQU ($8000-BAS_SIZ-TBC_SIZ-FTH_SIZ)
SLACK .EQU ($8000-BAS_SIZ-TBC_SIZ-FTH_SIZ-GAM_SIZ)
.FILL SLACK,00H
;
MON_STACK .EQU $

299
Source/HBIOS/ppide.asm

@ -29,11 +29,6 @@ PPIDE_IO_BASE .EQU $80
PPIDE_IO_BASE .EQU $4C
#ENDIF
;
PPIDE_IO_DATALO .EQU PPIDE_IO_BASE + 0 ; IDE DATA BUS LSB (8255 PORT A)
PPIDE_IO_DATAHI .EQU PPIDE_IO_BASE + 1 ; IDE DATA BUS MSB (8255 PORT B)
PPIDE_IO_CTL .EQU PPIDE_IO_BASE + 2 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)
PPIDE_IO_PPI .EQU PPIDE_IO_BASE + 3 ; 8255 CONTROL PORT
;
; THE CONTROL PORT OF THE 8255 IS PROGRAMMED AS NEEDED TO READ OR WRITE
; DATA ON THE IDE BUS. PORT C OF THE 8255 IS ALWAYS IN OUTPUT MODE BECAUSE
; IT IS DRIVING THE ADDRESS BUS AND CONTROL SIGNALS. PORTS A & B WILL BE
@ -173,7 +168,12 @@ PPIDE_REG_DRVADR .EQU PPIDE_CTL_CS3FX | $07 ; DRIVE ADDRESS REGISTER (R)
; PPIDE2: SECONDARY MASTER
; PPIDE3: SECONDARY SLAVE
;
PPIDE_DEVCNT .EQU 2 ; ASSUME ONLY PRIMARY INTERFACE
PPIDE0IO .EQU PPIDE_IO_BASE
PPIDE1IO .EQU 20H
PPIDE2IO .EQU 44H
PPIDE3IO .EQU 00H
;
PPIDE_DEVCNT .EQU PPICNT*2
;
; COMMAND BYTES
;
@ -213,7 +213,7 @@ PPIDE_DRVSLAVE .DB %11110000 ; LBA, SLAVE DEVICE
;
; PPIDE DEVICE CONFIGURATION
;
PPIDE_CFGSIZ .EQU 12 ; SIZE OF CFG TBL ENTRIES
PPIDE_CFGSIZ .EQU 15 ; SIZE OF CFG TBL ENTRIES
;
; PER DEVICE DATA OFFSETS
;
@ -223,6 +223,9 @@ PPIDE_TYPE .EQU 2 ; DEVICE TYPE (BYTE)
PPIDE_FLAGS .EQU 3 ; FLAG BITS BIT 0=CF, 1=LBA (BYTE)
PPIDE_MEDCAP .EQU 4 ; MEDIA CAPACITY (DWORD)
PPIDE_LBA .EQU 8 ; OFFSET OF LBA (DWORD)
PPIDE_DATALO .EQU 12 ; BASE PORT AND IDE DATA BUS LSB (8255 PORT A) (BYTE)
PPIDE_CTL .EQU 13 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE)
PPIDE_PPI .EQU 14 ; 8255 CONTROL PORT(BYTE)
;
PPIDE_CFGTBL:
; DEVICE 0, PRIMARY MASTER
@ -232,6 +235,9 @@ PPIDE_CFGTBL:
.DB 0 ; FLAGS BYTE
.DW 0,0 ; DEVICE CAPACITY
.DW 0,0 ; CURRENT LBA
.DB PPIDE0IO ; DATALO
.DB PPIDE0IO+2 ; CTL
.DB PPIDE0IO+3 ; PPI
; DEVICE 1, PRIMARY SLAVE
.DB 1 ; DRIVER DEVICE NUMBER
.DB 0 ; DEVICE STATUS
@ -239,6 +245,31 @@ PPIDE_CFGTBL:
.DB 0 ; FLAGS BYTE
.DW 0,0 ; DEVICE CAPACITY
.DW 0,0 ; CURRENT LBA
.DB PPIDE0IO ; DATALO
.DB PPIDE0IO+2 ; CTL
.DB PPIDE0IO+3 ; PPI
#IF (PPICNT> 1)
; DEVICE 2, PRIMARY MASTER
.DB 2 ; DRIVER DEVICE NUMBER
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB 0 ; FLAGS BYTE
.DW 0,0 ; DEVICE CAPACITY
.DW 0,0 ; CURRENT LBA
.DB PPIDE1IO ; DATALO
.DB PPIDE1IO+2 ; CTL
.DB PPIDE1IO+3 ; PPI
; DEVICE 3, PRIMARY SLAVE
.DB 3 ; DRIVER DEVICE NUMBER
.DB 0 ; DEVICE STATUS
.DB 0 ; DEVICE TYPE
.DB 0 ; FLAGS BYTE
.DW 0,0 ; DEVICE CAPACITY
.DW 0,0 ; CURRENT LBA
.DB PPIDE1IO ; DATALO
.DB PPIDE1IO+2 ; CTL
.DB PPIDE1IO+3 ; PPI
#ENDIF
;
#IF ($ - PPIDE_CFGTBL) != (PPIDE_DEVCNT * PPIDE_CFGSIZ)
.ECHO "*** INVALID PPIDE CONFIG TABLE ***\n"
@ -273,14 +304,11 @@ PPIDE_INIT:
LD A,(CB_CPUMHZ) ; LOAD CPU SPEED IN MHZ
CALL MULT8X16 ; HL := DE * A
LD (PPIDE_TOSCALER),HL ; SAVE IT
;
PRTS(" IO=0x$") ; LABEL FOR IO ADDRESS
LD A,PPIDE_IO_BASE
CALL PRTHEXBYTE
;
#IF (PPIDE8BIT)
PRTS(" 8BIT$")
#ENDIF
LD IY,PPIDE_CFGTBL
CALL PPIDE_DETECT ; CHECK FOR HARDWARE
JR Z,PPIDE_INIT00 ; CONTINUE IF PRESENT
;
@ -333,6 +361,11 @@ PPIDE_INIT2:
;
CALL PPIDE_PRTPREFIX ; PRINT DEVICE PREFIX
;
;
PRTS(" IO=0x$") ; LABEL FOR IO ADDRESS
LD A,(IY+PPIDE_DATALO)
CALL PRTHEXBYTE
;
#IF (PPIDE8BIT)
PRTS(" 8BIT$")
#ENDIF
@ -375,11 +408,20 @@ PPIDE_DETECT:
; THEN THE BUS HOLD CIRCUITRY WILL READ BACK THE ZERO. SINCE
; WE ARE IN WRITE MODE, AN IDE CONTROLLER WILL NOT BE ABLE TO
; INTERFERE WITH THE VALUE BEING READ.
LD C,(IY+PPIDE_PPI)
LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
OUT (PPIDE_IO_PPI),A ; OUTPUT TO CONTROL WORD
LD C,PPIDE_IO_DATALO ; PPI PORT A
OUT (C),A ; OUTPUT TO CONTROL WORD
;
LD C,(IY+PPIDE_DATALO) ; PPI PORT A
;
#IF USEZ80OPT
;; OUT (C),0
.DB $ED,$71
#ELSE
XOR A ; VALUE ZERO
OUT (C),A ; PUSH VALUE TO PORT
#ENDIF
;
IN A,(C) ; GET PORT VALUE
DCALL PC_SPACE
DCALL PRTHEXBYTE
@ -717,7 +759,7 @@ PPIDE_RUNCMD:
JP NZ,PPIDE_CMDERR
RET
;
;
; READ IDE DATA INTO BUFFER POINTED TO BY HL
;
PPIDE_GETBUF:
#IF (PPIDETRACE >= 3)
@ -729,22 +771,25 @@ PPIDE_GETBUF:
RET NZ ; BAIL OUT IF TIMEOUT
;
; SETUP PPI TO READ
LD C,(IY+PPIDE_PPI) ;
LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
OUT (PPIDE_IO_PPI),A ; DO IT
OUT (C),A ; DO IT
;
; SELECT READ/WRITE IDE REGISTER
DEC C ; LD C,(IY+PPIDE_CTL)
LD A,PPIDE_REG_DATA ; DATA REGISTER
OUT (PPIDE_IO_CTL),A ; DO IT
OUT (C),A ; DO IT
LD E,A ; E := READ UNASSERTED
XOR PPIDE_CTL_DIOR ; SWAP THE READ LINE BIT
LD D,A ; D := READ ASSERTED
;
; LOOP SETUP
LD B,0 ; 256 ITERATIONS
LD C,PPIDE_IO_DATALO ; SETUP C WITH IO PORT (LSB)
;
#IF (!PPIDE8BIT)
INC C ; PRE-INCREMENT C
LD B,0 ; LOOP SETUP - 256 ITERATIONS
; SETUP C WITH IO PORT
DEC C ; C = IY+PPIDE_DATAHI
#IF (PPIDE8BIT) ;
DEC C ; C = IY+PPIDE_DATALO
#ENDIF
;
CALL PPIDE_GETBUF1 ; FIRST PASS (FIRST 256 BYTES)
@ -760,18 +805,36 @@ PPIDE_GETBUF:
JP NZ,PPIDE_IOERR
RET
;
PPIDE_GETBUF1: ; START OF READ LOOP
LD A,D ; ASSERT READ
OUT (PPIDE_IO_CTL),A ; DO IT
#IF (!PPIDE8BIT)
PPIDE_GETBUF1: ; START OF READ LOOP
;
#IF (PPIDE8BIT)
INC C
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),D ; ASSERT READ
DEC C
DEC C
INI ; GET AND SAVE NEXT BYTE
PUSH AF
INC C
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),E ; DEASSERT READ
DEC C
DEC C
POP AF
#ELSE
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),D ; ASSERT READ
DEC C
DEC C
INI ; GET AND SAVE NEXT BYTE
INC C ; LSB -> MSB
#ENDIF
INI ; GET AND SAVE NEXT BYTE
LD A,E ; DEASSERT READ
OUT (PPIDE_IO_CTL),A ; DO IT
;
PUSH AF
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),E ; DEASSERT READ
DEC C
POP AF
#ENDIF
JR NZ,PPIDE_GETBUF1 ; LOOP UNTIL DONE
RET
;
@ -787,22 +850,26 @@ PPIDE_PUTBUF:
RET NZ ; BAIL OUT IF TIMEOUT
;
; SETUP PPI TO WRITE
LD C,(IY+PPIDE_PPI)
LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
OUT (PPIDE_IO_PPI),A ; DO IT
OUT (C),A ; DO IT
;
; SELECT READ/WRITE IDE REGISTER
DEC C ; LD C,(IY+PPIDE_CTL)
LD A,PPIDE_REG_DATA ; DATA REGISTER
OUT (PPIDE_IO_CTL),A ; DO IT
OUT (C),A ;
LD E,A ; E := WRITE UNASSERTED
XOR PPIDE_CTL_DIOW ; SWAP THE READ LINE BIT
LD D,A ; D := WRITE ASSERTED
;
; LOOP SETUP
LD B,0 ; 256 ITERATIONS
LD C,PPIDE_IO_DATALO ; SETUP C WITH IO PORT (LSB)
;
#IF (!PPIDE8BIT)
INC C ; PRE-INCREMENT C
; LOOP SETUP ; 256 ITERATIONS
LD B,0 ; SETUP C WITH IO PORT (LSB)
DEC C ; LD C,(IY+PPIDE_DATAHI)
#IF (PPIDE8BIT)
DEC C ; LD C,(IY+PPIDE_DATALO)
#ENDIF
;
CALL PPIDE_PUTBUF1 ; FIRST PASS (FIRST 256 BYTES)
@ -819,17 +886,28 @@ PPIDE_PUTBUF:
RET
;
PPIDE_PUTBUF1: ; START OF READ LOOP
#IF (!PPIDE8BIT)
#IF (PPIDE8BIT)
OUTI ; PUT NEXT BYTE ON THE BUS
PUSH AF
INC C ; LD C,(IY+PPIDE_CTL)
INC C
OUT (C),D ; ASSERT WRITE
OUT (C),E ; DEASSERT WRITE
DEC C
DEC C
POP AF
#ELSE
DEC C
OUTI ; PUT NEXT BYTE ON THE BUS (LSB)
INC C
OUTI ; PUT NEXT BYTE ON THE BUS (MSB)
PUSH AF
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),D ; ASSERT WRITE
OUT (C),E ; DEASSERT WRITE
DEC C
POP AF
#ENDIF
OUTI
LD A,D ; ASSERT WRITE
OUT (PPIDE_IO_CTL),A ; DO IT
LD A,E ; DEASSERT WRITE
OUT (PPIDE_IO_CTL),A ; DO IT
;
JR NZ,PPIDE_PUTBUF1 ; LOOP UNTIL DONE
RET
;
@ -860,17 +938,29 @@ PPIDE_GETRES:
;
PPIDE_RESET:
;
PUSH BC
; SETUP PPI TO READ
LD C,(IY+PPIDE_PPI) ;;
LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
OUT (PPIDE_IO_PPI),A ; DO IT
;
OUT (C),A ; DO IT
; PULSE IDE RESET LINE
LD C,(IY+PPIDE_CTL)
LD A,PPIDE_CTL_RESET
OUT (PPIDE_IO_CTL),A
OUT (C),A
;
LD DE,20
CALL VDELAY
XOR A
OUT (PPIDE_IO_CTL),A
;
#IF USEZ80OPT
;; OUT (C),0
.DB $ED,$71
#ELSE
XOR A ; VALUE ZERO
OUT (C),A ; PUSH VALUE TO PORT
#ENDIF
;
LD DE,20
CALL VDELAY
;
@ -909,6 +999,7 @@ PPIDE_RESET1:
DJNZ PPIDE_RESET1 ; LOOP AS NEEDED
;
POP IY ; RECOVER DEVICE CFG PTR
POP BC
;
XOR A ; SIGNAL SUCCESS
RET ; AND DONE
@ -973,9 +1064,16 @@ PPIDE_PROBE:
; RETURN SOMETHING OTHER THAN ZERO. IF AN IDE CONTROLLER IS
; THERE, THEN THE VALUE WRITTEN TO PPI PORT A IS IGNORED
; BECAUSE THE WRITE SIGNAL IS NEVER PULSED.
XOR A
OUT (PPIDE_IO_DATALO),A
; IN A,(PPIDE_REG_STAT) ; GET STATUS
;
LD C,(IY+PPIDE_DATALO)
#IF USEZ80OPT
;; OUT (C),0
.DB $ED,$71
#ELSE
XOR A ; VALUE ZERO
OUT (C),A ; PUSH VALUE TO PORT
#ENDIF
;
CALL PPIDE_IN
.DB PPIDE_REG_STAT
DCALL PC_SPACE
@ -1193,7 +1291,7 @@ PPIDE_WAITBSY1:
LD DE,(PPIDE_TOSCALER) ; CPU SPEED SCALER TO INNER LOOP VAR
PPIDE_WAITBSY2:
;IN A,(PPIDE_REG_STAT) ; READ STATUS
CALL PPIDE_IN ; 17TS + 170TS
CALL PPIDE_IN ; 17TS + 204TS
.DB PPIDE_REG_STAT ; 0TS
LD C,A ; SAVE IT ; 4TS
AND %10000000 ; TO FILL (OR READY TO FILL) ; 7TS
@ -1203,52 +1301,60 @@ PPIDE_WAITBSY2:
OR E ; 4TS
JR NZ,PPIDE_WAITBSY2 ; 12TS
DJNZ PPIDE_WAITBSY1 ; -----
JP PPIDE_BSYTO ; EXIT WITH BSYTO ERR ; 229TS
JP PPIDE_BSYTO ; EXIT WITH BSYTO ERR ; 246TS
;
;
;
PPIDE_IN:
LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ; 7TS
OUT (PPIDE_IO_PPI),A ; DO IT ; 11TS
EX (SP),HL ; GET PARM POINTER ; 19TS
; READ A VALUE FROM THE DEVICE POINTED TO BY IY AND RETURN IT IN A
;
PPIDE_IN: ; IY POINT TO CURRENT CFG TABLE
EX (SP),HL ; GET PARM POINTER ; 19TS
PUSH BC ; SAVE INCOMING BC ; 11TS
LD C,(IY+PPIDE_PPI) ; ; 19TS
LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ; 7TS
OUT (C),A ; DO IT ; 12TS
;
LD B,(HL) ; GET CTL PORT VALUE ; 7TS
LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE ; 7TS
DEC C ; LD C,(IY+PPIDE_CTL) ; 4TS
OUT (C),B ; SET ADDRESS LINES ; 12TS
SET 6,B ; TURN ON WRITE BIT ; 8TS
OUT (C),B ; ASSERT WRITE LINE ; 12TS
;NOP
;NOP
IN A,(PPIDE_IO_DATALO) ; GET DATA VALUE FROM DEVICE ; 11TS
;NOP
;NOP
;
DEC C ; 4TS
DEC C ; LD C,(IY+PPIDE_DATALO) ; 4TS
IN A,(C) ; GET DATA VALUE FROM DEVICE ; 12TS
;
RES 6,B ; CLEAR WRITE BIT ; 8TS
INC C ; 4TS
INC C ; LD C,(IY+PPIDE_CTL) ; 4TS
OUT (C),B ; DEASSERT WRITE LINE ; 12TS
POP BC ; RECOVER INCOMING BC ; 10TS
INC HL ; POINT PAST PARM ; 6TS
EX (SP),HL ; RESTORE STACK ; 19TS
RET ; 10TS
; ; -----
; ; 170TS
; ; 204TS
; ; -----
; OUTPUT A TO 3 2 0 2
;
PPIDE_OUT:
PUSH AF ; PRESERVE INCOMING VALUE
LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
OUT (PPIDE_IO_PPI),A ; DO IT
POP AF ; RECOVER VALUE TO WRITE
PPIDE_OUT: ; IY POINT TO CURRENT CFG TABLE
EX (SP),HL ; GET PARM POINTER
PUSH BC ; SAVE INCOMING BC
LD C,(IY+PPIDE_PPI)
LD B,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
OUT (C),B ; DO IT
LD B,(HL) ; GET IDE ADDRESS VALUE
LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE
DEC C ; LD C,(IY+PPIDE_CTL)
OUT (C),B ; SET ADDRESS LINES
SET 5,B ; TURN ON WRITE BIT
OUT (C),B ; ASSERT WRITE LINE
;NOP
;NOP
OUT (PPIDE_IO_DATALO),A ; SEND DATA VALUE TO DEVICE
;NOP
;NOP
;
DEC C
DEC C ; LD C,(IY+PPIDE_DATALO)
OUT (C),A ; SEND DATA VALUE TO DEVICE
;
RES 5,B ; CLEAR WRITE BIT
INC C
INC C ; LD C,(IY+PPIDE_CTL)
OUT (C),B ; DEASSERT WRITE LINE
POP BC ; RECOVER INCOMING BC
INC HL ; POINT PAST PARM
@ -1354,29 +1460,42 @@ PPIDE_PRTSTAT3:
; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
; DEVICE MUST BE SELECTED PRIOR TO CALL
;
;
; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
; DEVICE MUST BE SELECTED PRIOR TO CALL
;
PPIDE_REGDUMP:
PUSH AF
PUSH BC
PUSH DE
CALL PC_SPACE
CALL PC_LBKT
LD C,(IY+PPIDE_PPI) ;
LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
OUT (PPIDE_IO_PPI),A ; DO IT
LD C,PPIDE_REG_CMD
LD B,7
OUT (C),A ; DO IT
LD E,PPIDE_REG_CMD
LD D,7
PPIDE_REGDUMP1:
LD A,C ; REGISTER ADDRESS
OUT (PPIDE_IO_CTL),A ; SET IT
LD A,E ; REGISTER ADDRESS
LD C,(IY+PPIDE_CTL)
OUT (C),A ; SET IT
XOR PPIDE_CTL_DIOR ; SET BIT TO ASSERT READ LINE
OUT (PPIDE_IO_CTL),A ; ASSERT READ
IN A,(PPIDE_IO_DATALO) ; GET VALUE
OUT (C),A ; ASSERT READ
;
LD C,(IY+PPIDE_DATALO)
IN A,(C) ; GET VALUE
CALL PRTHEXBYTE ; DISPLAY IT
LD A,C ; RELOAD ADDRESS W/ READ UNASSERTED
OUT (PPIDE_IO_CTL),A ; AND SET IT
DEC C ; NEXT LOWER REGISTER
DEC B ; DEC LOOP COUNTER
;
LD A,E ;
LD C,(IY+PPIDE_CTL) ; RELOAD ADDRESS W/ READ UNASSERTED
OUT (C),E
;
DEC E ; NEXT LOWER REGISTER
DEC D ; DEC LOOP COUNTER
CALL NZ,PC_SPACE ; FORMATTING
JR NZ,PPIDE_REGDUMP1 ; LOOP AS NEEDED
CALL PC_RBKT ; FORMATTING
POP DE
POP BC
POP AF
RET

1
Source/HBIOS/romldr.asm

@ -368,6 +368,7 @@ MENU_1: MENU_L("~CP/M$ ", "C", KY_BK, CPM_ENT, 2000h, CPM_LOC, CPM_SIZ
MENU_L("~Forth$ ", "F", KY_EX, FTH_LOC, 0000h, FTH_LOC, FTH_SIZ, BID_IMG1, BID_USR, "Camel Forth$ ")
MENU_L("~BASIC$ ", "B", KY_DE, BAS_LOC, 1700h, BAS_LOC, BAS_SIZ, BID_IMG1, BID_USR, "Nascom BASIC$")
MENU_L("~T-BASIC$ ", "T", KY_EN, TBC_LOC, 3700h, TBC_LOC, TBC_SIZ, BID_IMG1, BID_USR, "Tasty BASIC$ ")
MENU_L("~PLAY$ ", "P", $FF, GAM_LOC, 4000h, GAM_LOC, GAM_SIZ, BID_IMG1, BID_USR, "Game$ ")
#ENDIF
#IF (DSKYENABLE)
MENU_L("~DSKY$ ", "D", KY_GO, MON_DSKY, 1000h, MON_LOC, MON_SIZ, BID_CUR, BID_USR, "DSKY Monitor$")

5
Source/HBIOS/std.asm

@ -28,6 +28,7 @@ TRUE .EQU ~FALSE
USENONE .EQU 0 ; NO DEBUG
USEXIO .EQU 1 ; BASIC SERIAL DRIVER
USEMIO .EQU 2 ; MEMORY BUFFER DRIVER
USEZ80OPT .EQU FALSE ; USE UNOFFICIAL OP CODES
WBWDEBUG .EQU USENONE
;
; PRIMARY HARDWARE PLATFORMS
@ -421,6 +422,10 @@ FTH_LOC .EQU $0200 ; CAMEL FORTH
FTH_SIZ .EQU $1700
FTH_END .EQU FTH_LOC + FTH_SIZ
GAM_LOC .EQU $0200 ; GAME 2048
GAM_SIZ .EQU $0900
GAM_END .EQU GAM_LOC + GAM_SIZ
MON_DSKY .EQU MON_LOC + (0 * 3) ; MONITOR ENTRY (DSKY)
MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
;

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