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dma updates

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b1ackmai1er
2021-10-21 23:14:35 +08:00
parent 711bf1c877
commit be1fb0836f
6 changed files with 46 additions and 25 deletions
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56
Source/Apps/Test/DMAmon/std.asm
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@@ -384,6 +384,17 @@ WDOG_NONE .EQU 0 ; NONE
WDOG_EZZ80 .EQU 1 ; EASY Z80 WATCHDOG
WDOG_SKZ .EQU 2 ; SK Z80 CPU W/ 512K
;
; SYSTEM SPEED CAPABILITIES
;
SPD_FIXED .EQU 0 ; PLATFORM SPEED FIXED AND CANNOT CHANGE SPEEDS
SPD_HILO .EQU 1 ; PLATFORM CAN CHANGE BETWEEN TWO SPEEDS
;
; SYSTEM SPEED CHARACTERISTICS
;
SPD_UNSUP .EQU 0 ; PLATFORM CAN CHANGE SPEEDS BUT IS UNSUPPORTED
SPD_HIGH .EQU 1 ; PLATFORM CAN CHANGE SPEED, STARTS HIGH
SPD_LOW .EQU 2 ; PLATFORM CAN CHANGE SPEED, STARTS LOW
;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;
#IF (BIOS == BIOS_WBW)
@@ -488,33 +499,40 @@ SYSTIM .SET TM_Z280
;
; MEMORY BANK CONFIGURATION
;
WBW_ROM_R .EQU 128 ; 128K ; RESERVED ROM REQUIRED FOR ROMWBW
WBW_RAM_R .EQU 256 ; 256K ; RESERVED RAM REQUIRED FOR ROMWBW
TOT_ROM_RB .EQU (PLT_ROM_R + WBW_ROM_R)/32 ; TOTAL ROM BANKS RESERVED
TOT_RAM_RB .EQU (PLT_RAM_R + WBW_RAM_R)/32 ; TOTAL RAM BANKS RESERVED
;
#IF (BIOS == BIOS_UNA)
BID_ROM0 .EQU $0000 + (ROM_RESERVE / 32)
BID_RAM0 .EQU $8000 + (RAM_RESERVE / 32)
BID_ROM0 .EQU $0000 + (PLT_ROM_R / 32)
BID_RAM0 .EQU $8000 + (PLT_RAM_R / 32)
#ENDIF
;
#IF (BIOS == BIOS_WBW)
BID_ROM0 .EQU $00 + (ROM_RESERVE / 32)
BID_RAM0 .EQU $80 + (RAM_RESERVE / 32)
BID_ROM0 .EQU $00 + (PLT_ROM_R / 32)
BID_RAM0 .EQU $80 + (PLT_RAM_R / 32)
#ENDIF
BID_ROMN .EQU (BID_ROM0 + ((ROMSIZE / 32) - 1))
BID_RAMN .EQU (BID_RAM0 + ((RAMSIZE / 32) - 1))
BID_BOOT .EQU BID_ROM0 ; BOOT BANK
BID_IMG0 .EQU BID_ROM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK
BID_IMG1 .EQU BID_ROM0 + 2 ; SECOND IMAGES BANK
;BID_FSFAT .EQU BID_ROM0 + 3 ; FAT FILESYSTEM DRIVER BANK
BID_IMG2 .EQU BID_ROM0 + 3 ; NETWORK BOOT
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK
BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK
BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK
BID_RAMDN .EQU BID_RAMN - 4 ; LAST RAM DRIVE BANK
BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.)
BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.)
BID_COM .EQU BID_RAMN ; COMMON BANK, UPPER 32K
;
BID_RAMD0 .EQU BID_RAM0 ; FIRST RAM DRIVE BANK ^ RAM
BID_RAMDN .EQU BID_RAMN - TOT_RAM_RB ; LAST RAM DRIVE BANK | DRIVE
; ; OS BUFFERS CP/M3? -+ THESE
; ; OS BUFFERS CP/M3? | MAKE
; ; OS BUFFERS CP/M3? | UP
; ; OS BUFFERS CP/M3? | THE
BID_AUX .EQU BID_RAMN - 3 ; AUX BANK (BPBIOS, ETC.) | 256KB
BID_BIOS .EQU BID_RAMN - 2 ; BIOS BANK | RESERVED
BID_USR .EQU BID_RAMN - 1 ; USER BANK (CP/M TPA, ETC.) | RAM
BID_COM .EQU BID_RAMN - 0 ; COMMON BANK, UPPER 32K -+ BANKS
BID_BOOT .EQU BID_ROM0 + 0 ; BOOT BANK -+ THESE MAKE
BID_IMG0 .EQU BID_ROM0 + 1 ; ROM LOADER AND FIRST IMAGES BANK | UP THE 128KB
BID_IMG1 .EQU BID_ROM0 + 2 ; SECOND IMAGES BANK | RESERVED
BID_IMG2 .EQU BID_ROM0 + 3 ; NETWORK BOOT -+ ROM BANKS
BID_ROMD0 .EQU BID_ROM0 + 4 ; FIRST ROM DRIVE BANK | ROM
BID_ROMDN .EQU BID_ROMN ; LAST ROM DRIVE BANK V DRIVE
;
; MEMORY LAYOUT
;

4
Source/Apps/Test/DMAmon/ver.inc
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@@ -1,5 +1,5 @@
#DEFINE RMJ 3
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 03
#DEFINE BIOSVER "3.1.1-pre.111"
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.128"

39
Source/HBIOS/PPI_Bus.txt
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@@ -1,39 +0,0 @@
PPI Signal PPIDE PPISD DSKY DSKYNG (PROTO) DSKYNG (FINAL)
---------- ----- ----- ----- ----- -----
PA0 <>D0 >ID0 <>D0 <>D0
PA1 <>D1 >ID1 <>D1 <>D1
PA2 <>D2 >ID2 <>D2 <>D2
PA3 <>D3 >ID3 <>D3 <>D3
PA4 <>D4 >ID4 /SHUTDOWN <>D4 <>D4
PA5 <>D5 >ID5 /DECODE <>D5 <>D5
PA6 <>D6 >ID6 HEXA/CODEB <>D6 <>D6
PA7 <>D7 >ID7 DAT_COMING <>D7 <>D7
PB0 <>D8 +<ROW5
PB1 <>D9 +<ROW4
PB2 <>D10 +<ROW3
PB3 <>D11 +<ROW2
PB4 <>D12 +<ROW1
PB5 <>D13 +<ROW0
PB6 <>D14 +
PB7 <>D15 <MISO +
PC0 >DA0 >MOSI >COL0 >A0 >A0
PC1 >DA1 >CLK >COL1 >/WR
PC2 >DA2 >COL2 >/RD
PC3 >CS0* >COL3 >CS&* >CS&*
PC4 >CS1* >/CS >CS&* >CS&*
PC5 >DIOW* >/WR
PC6 >DIOR* >/WR >/RD
PC7 >RESET* >MODE >RESET >RESET
* Inverted by adapter
+ Pullup
& Both signals must be asserted
Compatibility:
- PPISD & DSKY
- PPIDE & DSKYNG
- PPISD & DSKYNG

3
Source/HBIOS/dma.asm
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@@ -165,6 +165,7 @@ DMACode_Len .equ $-DMACode
DMALDIR:
ld (DMASource),hl ; populate the dma
ld (DMADest),de ; register template
dec bc
ld (DMALength),bc
;
ld hl,DMACopy ; program the
@@ -211,6 +212,7 @@ DMACopy_Len .equ $-DMACopy
DMAOTIR:
ld (DMAOutSource),hl ; populate the dma
ld (DMAOutDest),a ; register template
dec bc
ld (DMAOutLength),bc
;
ld hl,DMAOutCode ; program the
@@ -262,6 +264,7 @@ DMAOut_Len .equ $-DMAOutCode
DMAINIR:
ld (DMAInDest),hl ; populate the dma
ld (DMAInSource),a ; register template
dec bc
ld (DMAInLength),bc
;
ld hl,DMAInCode ; program the

4
Source/HBIOS/md.asm
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@@ -382,7 +382,7 @@ MD_SECM:
OR A
JR NZ,MD_NODMA
#ENDIF
LD BC,512-1 ; COPY ONE 512B SECTOR FROM THE
LD BC,512 ; COPY ONE 512B SECTOR FROM THE
JP DMALDIR ; 4K SECTOR TO THE DISK BUFFER
#ENDIF
MD_NODMA:
@@ -516,7 +516,7 @@ MD_SECM1: ; DESIRED SECTOR IS IN BUFFER
OR A
JR NZ,MD_NODMA1
#ENDIF
LD BC,512-1 ; COPY ONE 512B SECTOR FROM THE
LD BC,512 ; COPY ONE 512B SECTOR FROM THE
CALL DMALDIR ; THE DISK BUFFER TO 4K SECTOR
RET NZ ; EXIT IF DMA COPY ERROR
JR MD_NODMAERR

4
Source/HBIOS/rf.asm
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@@ -273,7 +273,7 @@ RF_RDSEC:
LD HL,(RF_DSKBUF) ; HL := DISK BUFFER ADDRESS
LD A,(RF_IO) ; GET IO PORT BASE
#IF (DMAENABLE & (DMAMODE=DMAMODE_ECB))
LD BC,512-1 ; READ 512 BYTES
LD BC,512 ; READ 512 BYTES
CALL DMAINIR ; USING DMA
#ELSE
OR RF_DAT ; OFFSET TO DAT PORT
@@ -293,7 +293,7 @@ RF_WRSEC:
LD A,(RF_IO) ; GET IO PORT BASE
OR RF_DAT ; OFFSET TO DAT PORT
#IF (DMAENABLE & (DMAMODE=DMAMODE_ECB))
LD BC,512-1 ; WRITE 512 BYTES
LD BC,512 ; WRITE 512 BYTES
CALL DMAOTIR ; USING DMA
#ELSE
LD C,A ; PUT IN C FOR PORT IO