diff --git a/.gitignore b/.gitignore index 289ddcd4..2f933740 100644 --- a/.gitignore +++ b/.gitignore @@ -110,4 +110,142 @@ Source/ZPM3/zccp.com Source/ZPM3/zpmldr.com Source/ZPM3/genbnk.dat -Source/ZSDOS/zsdos.err \ No newline at end of file +Source/ZSDOS/zsdos.err + +# Lets explicit list all generate untracked binary files +Binary/Apps/Tunes/bgm.vgm +Binary/Apps/Tunes/ending.vgm +Binary/Apps/Tunes/inchina.vgm +Binary/Apps/Tunes/shirakaw.vgm +Binary/Apps/Tunes/startdem.vgm +Binary/Apps/Tunes/wonder01.vgm +Binary/Apps/fdu.doc +Binary/Apps/zmconfig.ovr +Binary/Apps/zminit.ovr +Binary/Apps/zmp.doc +Binary/Apps/zmp.hlp +Binary/Apps/zmterm.ovr +Binary/Apps/zmxfer.ovr +Binary/CPM3/bdos3.spr +Binary/CPM3/bios3.spr +Binary/CPM3/bnkbdos3.spr +Binary/CPM3/bnkbios3.spr +Binary/CPM3/cpm3fix.pat +Binary/CPM3/genbnk.dat +Binary/CPM3/gencpm.dat +Binary/CPM3/genres.dat +Binary/CPM3/readme.1st +Binary/CPM3/resbdos3.spr +Binary/CPNET/cpn12duo.lbr +Binary/CPNET/cpn12mt.lbr +Binary/CPNET/cpn12ser.lbr +Binary/CPNET/cpn3duo.lbr +Binary/CPNET/cpn3mt.lbr +Binary/CPNET/cpn3ser.lbr +Binary/RCEZ80_std.upd +Binary/RCZ80_std.upd +Binary/ZPM3/bnkbdos3.spr +Binary/ZPM3/bnkbios3.spr +Binary/ZPM3/gencpm.dat +Binary/ZPM3/resbdos3.spr +Binary/ZPM3/zinstal.zpm +Binary/hd1k_prefix.dat +Source/BPBIOS/def-ww.lib +Source/CPNET/cpn12duo.lbr +Source/CPNET/cpn12mt.lbr +Source/CPNET/cpn12ser.lbr +Source/CPNET/cpn3duo.lbr +Source/CPNET/cpn3mt.lbr +Source/CPNET/cpn3ser.lbr +Source/Fonts/font8x11c.asm +Source/Fonts/font8x11c.bin +Source/Fonts/font8x11u.asm +Source/Fonts/font8x16c.asm +Source/Fonts/font8x16c.bin +Source/Fonts/font8x16u.asm +Source/Fonts/font8x8c.asm +Source/Fonts/font8x8c.bin +Source/Fonts/font8x8u.asm +Source/Fonts/fontcgac.asm +Source/Fonts/fontcgac.bin +Source/Fonts/fontcgau.asm +Source/Fonts/fontvgarcc.asm +Source/Fonts/fontvgarcc.bin +Source/Fonts/fontvgarcu.asm +Source/HBIOS/RCEZ80_std.upd +Source/HBIOS/RCZ80_std.upd +Source/HBIOS/build_env.cmd +Source/HBIOS/hbios_env.sh +Source/Images/blank144 +Source/Images/blankhd1k +Source/Images/blankhd512 +Source/Images/fd144_aztecc.img +Source/Images/fd144_bascomp.img +Source/Images/fd144_cowgol.img +Source/Images/fd144_cpm22.img +Source/Images/fd144_cpm3.img +Source/Images/fd144_fortran.img +Source/Images/fd144_games.img +Source/Images/fd144_hitechc.img +Source/Images/fd144_nzcom.img +Source/Images/fd144_qpm.img +Source/Images/fd144_tpascal.img +Source/Images/fd144_ws4.img +Source/Images/fd144_z80asm.img +Source/Images/fd144_zpm3.img +Source/Images/fd144_zsdos.img +Source/Images/hd1k_aztecc.img +Source/Images/hd1k_bascomp.img +Source/Images/hd1k_blank.img +Source/Images/hd1k_bp.img +Source/Images/hd1k_combo.img +Source/Images/hd1k_cowgol.img +Source/Images/hd1k_cpm22.img +Source/Images/hd1k_cpm3.img +Source/Images/hd1k_fortran.img +Source/Images/hd1k_games.img +Source/Images/hd1k_hitechc.img +Source/Images/hd1k_nzcom.img +Source/Images/hd1k_qpm.img +Source/Images/hd1k_tpascal.img +Source/Images/hd1k_ws4.img +Source/Images/hd1k_z80asm.img +Source/Images/hd1k_zpm3.img +Source/Images/hd1k_zsdos.img +Source/Images/hd512_aztecc.img +Source/Images/hd512_bascomp.img +Source/Images/hd512_blank.img +Source/Images/hd512_combo.img +Source/Images/hd512_cowgol.img +Source/Images/hd512_cpm22.img +Source/Images/hd512_cpm3.img +Source/Images/hd512_dos65.img +Source/Images/hd512_fortran.img +Source/Images/hd512_games.img +Source/Images/hd512_hitechc.img +Source/Images/hd512_nzcom.img +Source/Images/hd512_qpm.img +Source/Images/hd512_tpascal.img +Source/Images/hd512_ws4.img +Source/Images/hd512_z80asm.img +Source/Images/hd512_zpm3.img +Source/Images/hd512_zsdos.img +Source/RomDsk/rom0_una.dat +Source/RomDsk/rom0_wbw.dat +Source/RomDsk/rom128_una.dat +Source/RomDsk/rom128_wbw.dat +Source/RomDsk/rom256_una.dat +Source/RomDsk/rom256_wbw.dat +Source/RomDsk/rom384_una.dat +Source/RomDsk/rom384_wbw.dat +Source/RomDsk/rom896_una.dat +Source/RomDsk/rom896_wbw.dat +Source/ZCPR-DJ/zcprdemo.com +Source/ZPM3/autotog.com +Source/ZPM3/clrhist.com +Source/ZPM3/cpmldr.com +Source/ZPM3/setz3.com +Tools/unix/OpenSpin/build/ +Tools/unix/zxcc/config.h +Tools/unix/zxcc/zxcc +Binary/Apps/bbcbasic.txt diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 00000000..7c12e6b0 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,4 @@ +{ + "files.trimTrailingWhitespace": false, + "files.eol": "\r\n" +} diff --git a/Dockerfile b/Dockerfile new file mode 100644 index 00000000..d2e716e1 --- /dev/null +++ b/Dockerfile @@ -0,0 +1,48 @@ +FROM ubuntu:jammy-20240111 as basebuilder + +# This docker file can be used to build a tool chain docker image for building RomWBW images. + +# Tested on a ubuntu host and on Windows un WSL (with docker desktop) + +# First build the docker image (will b) +# docker build --progress plain -t romwbw-chain . + +# After you have built the above image (called romwbw-chain), you can use it to compile and build the RomWBW images +# as per the standard make scripts within RomWBW. +# Start a new terminal, cd to where you have clone RomWBW, and then run this command: +# docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it romwbw-chain:latest + +# you can now compile and build the required images: + +# cd Tools && make +# cd Source && make # at least once to build many common units +# cd Source && make rom ROM_PLATFORM=RCEZ80 ROM_CONFIG=std + +# when finish, type 'exit' to return to back to your standard terminal session + +LABEL Maintainer="Dean Netherton" \ + Description="spike to use clang for ez80 target" + +ENV DEBIAN_FRONTEND=noninteractive + + +RUN dpkg --add-architecture i386 +RUN sed -i 's/http:\/\/archive\.ubuntu\.com\/ubuntu/http:\/\/au.archive.ubuntu.com\/ubuntu/g' /etc/apt/sources.list +RUN apt update -y +RUN apt dist-upgrade -y +RUN apt install -y --no-install-recommends cmake lzip ca-certificates mtools build-essential dos2unix libboost-all-dev texinfo texi2html libxml2-dev subversion bison flex zlib1g-dev m4 git wget dosfstools curl + +RUN mkdir work +WORKDIR /work + +FROM basebuilder as main + +LABEL Maintainer="Dean Netherton" \ + Description="spike to build RomWBW" + +RUN mkdir /src +WORKDIR /src/ + +RUN apt install -y --no-install-recommends build-essential libncurses-dev srecord bsdmainutils + +RUN adduser --disabled-password --gecos "" builder diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md index cacd3439..cd8fbc98 100644 --- a/Source/Doc/SystemGuide.md +++ b/Source/Doc/SystemGuide.md @@ -630,23 +630,24 @@ All character units are assigned a Device Type ID which indicates the specific hardware device driver that handles the unit. The table below enumerates these values. -| **Device Type** | **ID** | **Description** | **Driver** | -|-----------------|-------:|------------------------------------------|------------| -| CIODEV_UART | 0x00 | 16C550 Family Serial Interface | uart.asm | -| CIODEV_ASCI | 0x01 | Z180 Built-in Serial Ports | asci.asm | -| CIODEV_TERM | 0x02 | Terminal | ansi.asm | -| CIODEV_PRPCON | 0x03 | PropIO Serial Console Interface | prp.asm | -| CIODEV_PPPCON | 0x04 | ParPortProp Serial Console Interface | ppp.asm | -| CIODEV_SIO | 0x05 | Zilog Serial Port Interface | sio.asm | -| CIODEV_ACIA | 0x06 | MC68B50 Asynchronous Interface | acia.asm | -| CIODEV_PIO | 0x07 | Zilog Parallel Interface Controller | pio.asm | -| CIODEV_UF | 0x08 | FT232H-based ECB USB FIFO | uf.asm | -| CIODEV_DUART | 0x09 | SCC2681 Family Dual UART | duart.asm | -| CIODEV_Z2U | 0x0A | Zilog Z280 Built-in Serial Ports | z2u.asm | -| CIODEV_LPT | 0x0B | Parallel I/O Controller | lpt.asm | -| CIODEV_ESPCON | 0x0B | ESP32 VGA Console | esp.asm | -| CIODEV_ESPSER | 0x0B | ESP32 Serial Port | esp.asm | -| CIODEV_SCON | 0x0B | S100 Console | scon.asm | +| **Device Type** | **ID** | **Description** | **Driver** | +|-----------------|-------:|------------------------------------------|--------------| +| CIODEV_UART | 0x00 | 16C550 Family Serial Interface | uart.asm | +| CIODEV_ASCI | 0x01 | Z180 Built-in Serial Ports | asci.asm | +| CIODEV_TERM | 0x02 | Terminal | ansi.asm | +| CIODEV_PRPCON | 0x03 | PropIO Serial Console Interface | prp.asm | +| CIODEV_PPPCON | 0x04 | ParPortProp Serial Console Interface | ppp.asm | +| CIODEV_SIO | 0x05 | Zilog Serial Port Interface | sio.asm | +| CIODEV_ACIA | 0x06 | MC68B50 Asynchronous Interface | acia.asm | +| CIODEV_PIO | 0x07 | Zilog Parallel Interface Controller | pio.asm | +| CIODEV_UF | 0x08 | FT232H-based ECB USB FIFO | uf.asm | +| CIODEV_DUART | 0x09 | SCC2681 Family Dual UART | duart.asm | +| CIODEV_Z2U | 0x0A | Zilog Z280 Built-in Serial Ports | z2u.asm | +| CIODEV_LPT | 0x0B | Parallel I/O Controller | lpt.asm | +| CIODEV_ESPCON | 0x0B | ESP32 VGA Console | esp.asm | +| CIODEV_ESPSER | 0x0B | ESP32 Serial Port | esp.asm | +| CIODEV_SCON | 0x0B | S100 Console | scon.asm | +| CIODEV_EZ80UART | 0x11 | eZ80 Built-in UART0 Interface | ez80uart.asm | Character devices can usually be configured with line characteristics such as speed, framing, etc. A word value (16 bit) is used to describe @@ -1142,14 +1143,15 @@ more than one at a time. The RTC unit is assigned a Device Type ID which indicates the specific hardware device driver that handles the unit. The table below enumerates these values. -| **Device Type** | **ID** | **Description** | **Driver** | -|-----------------|-------:|------------------------------------------|------------| -| RTCDEV_DS | 0x00 | Maxim DS1302 Real-Time Clock w/ NVRAM | dsrtc.asm | -| RTCDEV_BQ | 0x01 | BQ4845P Real Time Clock | bqrtc.asm | -| RTCDEV_SIMH | 0x02 | SIMH Simulator Real-Time Clock | simrtc.asm | -| RTCDEV_INT | 0x03 | Interrupt-based Real Time Clock | intrtc.asm | -| RTCDEV_DS7 | 0x04 | Maxim DS1307 PCF I2C RTC w/ NVRAM | ds7rtc.asm | -| RTCDEV_RP5 | 0x05 | Ricoh RPC01A Real-Time Clock w/ NVRAM | rp5rtc.asm | +| **Device Type** | **ID** | **Description** | **Driver** | +|-----------------|-------:|------------------------------------------|-------------| +| RTCDEV_DS | 0x00 | Maxim DS1302 Real-Time Clock w/ NVRAM | dsrtc.asm | +| RTCDEV_BQ | 0x01 | BQ4845P Real Time Clock | bqrtc.asm | +| RTCDEV_SIMH | 0x02 | SIMH Simulator Real-Time Clock | simrtc.asm | +| RTCDEV_INT | 0x03 | Interrupt-based Real Time Clock | intrtc.asm | +| RTCDEV_DS7 | 0x04 | Maxim DS1307 PCF I2C RTC w/ NVRAM | ds7rtc.asm | +| RTCDEV_RP5 | 0x05 | Ricoh RPC01A Real-Time Clock w/ NVRAM | rp5rtc.asm | +| RTCDEV_EZ80 | 0x07 | eZ80 on-chip RTC | ez80rtc.asm | The time functions to get and set the time (RTCGTM and RTCSTM) require a 6 byte date/time buffer in the following format. Each byte is BCD @@ -2237,6 +2239,7 @@ The hardware Platform (L) is identified as follows: | PLT_Z80RETRO |15 | Z80 RETRO COMPUTER | | PLT_S100 |16 | S100 COMPUTERS Z180 | | PLT_DUO |17 | DUODYNE Z80 SYSTEM | +| PLT_RCEZ80 |24 | RCBUS W/ eZ80 | ### Function 0xF2 -- System Set Bank (SYSSETBNK) diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm new file mode 100644 index 00000000..93129cff --- /dev/null +++ b/Source/HBIOS/Config/RCEZ80_std.asm @@ -0,0 +1,82 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS EZ80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCEZ80.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +;; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_easy_std.asm b/Source/HBIOS/Config/RCZ80_easy_std.asm index c9a526a1..d77c57dc 100644 --- a/Source/HBIOS/Config/RCZ80_easy_std.asm +++ b/Source/HBIOS/Config/RCZ80_easy_std.asm @@ -48,7 +48,7 @@ ; #INCLUDE "cfg_RCZ80.asm" ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] ; CPUOSC .SET 10000000 ; CPU OSC FREQ IN MHZ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) diff --git a/Source/HBIOS/Config/RCZ80_tiny_std.asm b/Source/HBIOS/Config/RCZ80_tiny_std.asm index 1e6f2cab..d03c28be 100644 --- a/Source/HBIOS/Config/RCZ80_tiny_std.asm +++ b/Source/HBIOS/Config/RCZ80_tiny_std.asm @@ -48,7 +48,7 @@ ; #INCLUDE "cfg_RCZ80.asm" ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] ; CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile index d684aa1f..97910740 100644 --- a/Source/HBIOS/Makefile +++ b/Source/HBIOS/Makefile @@ -18,7 +18,7 @@ endif ifeq ($(OBJECTS),) start: - chmod +x Build.sh + @chmod +x Build.sh bash Build.sh $(DIFFBUILD) endif @@ -59,7 +59,7 @@ ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG} # $(info TASM=$(TASM)) $(OBJECTS) : $(ROMDEPS) - cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin + @cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >osimg_small.bin if [ $(ROM_PLATFORM) != UNA ] ; then \ cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin usrrom.bin >osimg1.bin ; \ @@ -104,19 +104,19 @@ tastybasic.bin: cp ../TastyBasic/src/$@ . hbios_rom.bin: hbios.asm build.inc $(DEPS) - $(TASM) -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst + @$(TASM) -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst hbios_app.bin: hbios.asm build.inc $(DEPS) - $(TASM) -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst + @$(TASM) -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst hbios_img.bin: hbios.asm build.inc $(DEPS) - $(TASM) -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst + @$(TASM) -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst hbios_env.com: hbios_env.asm build.inc - $(TASM) -dBASH hbios_env.asm hbios_env.com hbios_env.lst + @$(TASM) -dBASH hbios_env.asm hbios_env.com hbios_env.lst hbios_env.sh: hbios_env.com - $(ZXCC) hbios_env.com >hbios_env.sh + @$(ZXCC) hbios_env.com >hbios_env.sh romldr.bin: build.inc dbgmon.bin: build.inc diff --git a/Source/HBIOS/ay38910.asm b/Source/HBIOS/ay38910.asm index c357b0d9..6006b2a9 100644 --- a/Source/HBIOS/ay38910.asm +++ b/Source/HBIOS/ay38910.asm @@ -489,8 +489,10 @@ AY_WRTPSG: OUT0 (Z180_DCNTL),A ; AND UPDATE DCNTL #ENDIF LD A,D ; SELECT THE REGISTER WE + EZ80_IO OUT (AY_RSEL),A ; WANT TO WRITE TO LD A,E ; WRITE THE VALUE TO + EZ80_IO OUT (AY_RDAT),A ; THE SELECTED REGISTER #IF (CPUFAM == CPU_Z180) POP AF ; GET SAVED DCNTL VALUE @@ -519,7 +521,9 @@ AY_RDPSG: OUT0 (Z180_DCNTL),A ; AND UPDATE DCNTL #ENDIF LD A,D ; SELECT THE REGISTER WE + EZ80_IO OUT (AY_RSEL),A ; WANT TO READ + EZ80_IO IN A,(AY_RIN) ; READ SELECTED REGISTER LD E,A #IF (CPUFAM == CPU_Z180) diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index 80d62dcd..8a2dfe92 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index 29e533c7..b73e8d52 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index f9ba6fb3..7442aa60 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_FZ80.asm b/Source/HBIOS/cfg_FZ80.asm index 1b5d2bf5..dc5c7848 100644 --- a/Source/HBIOS/cfg_FZ80.asm +++ b/Source/HBIOS/cfg_FZ80.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index fbee4244..02d10263 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 0bc354ed..d5b38754 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm index 62d0ac5a..f5a89051 100644 --- a/Source/HBIOS/cfg_MASTER.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -46,8 +46,8 @@ ; #INCLUDE "hbios.inc" ; -PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) @@ -439,6 +439,7 @@ UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR ; SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER +SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index 83fefef7..48bf0f40 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index 8f51dcaa..ba3674a3 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index 885fcf07..b786e4c3 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index ae3b6df9..8c6c06ca 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index 01174339..14e77dfd 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm new file mode 100644 index 00000000..e9ed81c1 --- /dev/null +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -0,0 +1,428 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZE80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) + +; EZ80 SETTINGS +; +EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS +EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS +EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) + +EZ80UARTENABLE .SET TRUE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) +EZ80RTCENABLE .SET TRUE ; EZ80 ON CHIP RTC +EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] +EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO + +; BUS TIMING FOR PAGED MEMORY ACCESS (CS3) +EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES +EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_MEM_WS .SET 5 ; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT +EZ80_MEM_MIN_WS .SET 0 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC + +; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2) +EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES +EZ80_IO_WS .SET 5 ; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT +EZ80_IO_MIN_NS .SET 320 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_IO_MIN_WS .SET 6 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC + +; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD +EZ80_WSMD_TYP .EQU EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT] +; +; BUS TIMING FOR ON CHIP ROM +; +EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7) +EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED) diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index b90567fb..e6ea12cb 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index e9e6e629..3b803233 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index 56279490..3fb1e537 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index 41021e1b..bb5f3e7e 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm index fbffdab6..a5a3b380 100644 --- a/Source/HBIOS/cfg_S100.asm +++ b/Source/HBIOS/cfg_S100.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index fc569260..9a539be0 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index 38416754..8234fbc9 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_UNA.asm b/Source/HBIOS/cfg_UNA.asm index 3b6e30f2..4fe90615 100644 --- a/Source/HBIOS/cfg_UNA.asm +++ b/Source/HBIOS/cfg_UNA.asm @@ -15,8 +15,8 @@ ; #INCLUDE "../UBIOS/ubios.inc" ; -;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] ; FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index b2640ee3..99356548 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index e832496a..a57b02e6 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index caaa9bbe..44f12023 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -46,8 +46,8 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) diff --git a/Source/HBIOS/ch.asm b/Source/HBIOS/ch.asm index 0bfb877d..b7f52caa 100644 --- a/Source/HBIOS/ch.asm +++ b/Source/HBIOS/ch.asm @@ -236,6 +236,7 @@ CH_INIT4: CH_CMD: LD C,(IY+CH_IOBASE) ; BASE PORT INC C ; BUMP TO CMD PORT + EZ80_IO OUT (C),A ; SEND COMMAND CALL CH_NAP ; *DEBUG* RET @@ -245,6 +246,7 @@ CH_CMD: CH_STAT: LD C,(IY+CH_IOBASE) ; BASE PORT INC C ; BUMP TO CMD PORT + EZ80_IO IN A,(C) ; READ STATUS RET ; @@ -252,6 +254,7 @@ CH_STAT: ; CH_RD: LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO IN A,(C) ; READ BYTE RET ; @@ -259,6 +262,7 @@ CH_RD: ; CH_WR: LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO OUT (C),A ; READ BYTE RET ; diff --git a/Source/HBIOS/chsd.asm b/Source/HBIOS/chsd.asm index c4b38194..2b217b80 100644 --- a/Source/HBIOS/chsd.asm +++ b/Source/HBIOS/chsd.asm @@ -19,7 +19,7 @@ ; #DEFINE CHSD_IMGFILE "DISK.IMG" ; -CHSD_FASTIO .EQU TRUE ; USE INIR/OTIR? +CHSD_FASTIO .EQU FALSE ; USE INIR/OTIR? ; ; CHUSB DEVICE STATUS ; @@ -196,6 +196,7 @@ CHSD_READ1: #IF (CHSD_FASTIO) LD B,A ; BYTE COUNT TO READ LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO ;!! NOT SUPPORT INIR YET INIR ; DO IT FAST #ELSE LD B,A ; SAVE IT @@ -263,6 +264,7 @@ CHSD_WRITE1: #IF (CHSD_FASTIO) LD B,A ; BYTE COUNT TO WRITE LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO ;!! NOT SUPPORT OTIR YET OTIR ; DO IT FAST #ELSE LD B,A ; SAVE IT diff --git a/Source/HBIOS/chusb.asm b/Source/HBIOS/chusb.asm index 175a00b2..d77f3f64 100644 --- a/Source/HBIOS/chusb.asm +++ b/Source/HBIOS/chusb.asm @@ -196,6 +196,7 @@ CHUSB_READ1: PUSH BC ; SAVE LOOP CONTROL LD B,64 ; READ 64 BYTES LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO INIR ; DO IT FAST POP BC ; RESTORE LOOP CONTROL #ELSE @@ -260,6 +261,7 @@ CHUSB_WRITE1: PUSH BC ; SAVE LOOP CONTROL LD B,64 ; WRITE 64 BYTES LD C,(IY+CH_IOBASE) ; BASE PORT + EZ80_IO OTIR ; DO IT FAST POP BC ; RESTORE LOOP CONTROL #ELSE diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm new file mode 100644 index 00000000..b972e272 --- /dev/null +++ b/Source/HBIOS/ez80cpudrv.asm @@ -0,0 +1,256 @@ +; +;================================================================================================== +; RCBUS EZ80 CPU DRIVER +;================================================================================================== +; +; Driver code designed for the RCBus eZ80 CPU Module. +; The driver expects the eZ80 firmware to manage the initial booting of the system. +; Details for the platform and the software for the on-chip firmware can be found at: +; https://github.com/dinoboards/rc2014-ez80 +; +; Although the eZ80 firmware is booted before HBIOS, the eZ80 CPU driver is still required +; to communicate with the firmware to perform a number of initialisation tasks. +; See also the associated ez80 platform drivers (ez80rtc, ez80systmr, ez80uart). +; +; The driver 'exports' two key functions: +; 1. EZ80_PREINIT - This function is called by the HBIOS boot code to initialise the eZ80 firmware. +; 2. EZ80_RPT_TIMINGS - This function is called by the HBIOS boot code to report the platform timings. +; +; EZ80_PREINIT performs the following: +; 1. Exchange platform version numbers +; 2. Retrieve CPU Frequency +; 3. Set Memory and I/O Bus Timings +; 4. Set Timer Tick Frequency +; + +EZ80_PREINIT: + EZ80_TMR_INT_DISABLE() + + ; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS + LD C, 1 ; RomWBW'S ASSIGNED CODE + LD D, RMJ + LD E, RMN + LD H, RUP + LD L, RTP + + EZ80_UTIL_VER_EXCH() + ; TODO: MAP THE FIRMWARE CPU TO HBIOS (eZ80 ONLY HAS ONE CPU TYPE AS OF NOW) + LD A, 5 + LD (HB_CPUTYPE),A + + ; DETECT IF USING ALT-FIRMWARE + LD A, C + AND $80 + LD (EZ80_ALT_FIRM), A + LD (EZ80_PLT_VERSION), HL + LD (EZ80_PLT_VERSION+2), DE + + EXX + LD A, C + LD (EZ80_BUILD_DATE), A ; DAY + LD A, D + LD (EZ80_BUILD_DATE+1), A ; MONTH + LD A, E + LD (EZ80_BUILD_DATE+2), A ; YEAR + + EZ80_UTIL_GET_CPU_FQ() + LD A, E + LD (CB_CPUMHZ), A + LD (CB_CPUKHZ), HL + LD (HB_CPUOSC), HL + +#IF (EZ80_FWSMD_TYP == EZ80WSMD_WAIT) + LD L, EZ80_FLSH_WS + EZ80_UTIL_FLSHWS_SET() + LD A, L + LD (EZ80_PLT_FLSHWS), A +#ENDIF + +#IF (EZ80_FWSMD_TYP == EZ80WSMD_CALC) + LD HL, EZ80_FLSH_MIN_NS + LD E, 0 + EZ80_CPY_EHL_TO_UHL + EZ80_UTIL_FLSHFQ_SET() + LD A, L + LD (EZ80_PLT_FLSHWS), A +#ENDIF + + +#IF (EZ80_WSMD_TYP == EZ80WSMD_CYCLES) + LD L, EZ80_MEM_CYCLES + OR $80 + EZ80_UTIL_MEMTM_SET() + LD A, L + LD (EZ80_PLT_MEMWS), A + + LD L, EZ80_IO_CYCLES + OR $80 + EZ80_UTIL_IOTM_SET() + LD A, L + LD (EZ80_PLT_IOWS), A + + RET +#ENDIF + +#IF (EZ80_WSMD_TYP == EZ80WSMD_CALC) + LD HL, EZ80_MEM_MIN_NS + LD E, 0 + EZ80_CPY_EHL_TO_UHL + LD E, EZ80_MEM_MIN_WS + EZ80_UTIL_MEMTMFQ_SET + LD A, L + LD (EZ80_PLT_MEMWS), A + + LD HL, EZ80_IO_MIN_NS + LD E, 0 + EZ80_CPY_EHL_TO_UHL + LD E, EZ80_IO_MIN_WS + EZ80_UTIL_IOTMFQ_SET + + LD A, L + LD (EZ80_PLT_IOWS), A +#ENDIF +#IF (EZ80_WSMD_TYP == EZ80WSMD_WAIT) + LD L, EZ80_MEM_WS + EZ80_UTIL_MEMTM_SET() + LD A, L + LD (EZ80_PLT_MEMWS), A + + LD L, EZ80_IO_WS + EZ80_UTIL_IOTM_SET() + LD A, L + LD (EZ80_PLT_IOWS), A +#ENDIF + + LD C, TICKFREQ + EZ80_TMR_SET_FREQTICK + + RET + +EZ80_RPT_TIMINGS: + LD A, (EZ80_PLT_MEMWS) + BIT 7, A + JR NZ, EZ80_RPT_MCYC + + CALL PRTDECB + CALL PRTSTRD + .TEXT " MEM W/S, $" + JR EZ80_RPT_IOTIMING + +EZ80_RPT_MCYC: + AND $7F + CALL PRTDECB + CALL PRTSTRD + .TEXT " MEM B/C, $" + +EZ80_RPT_IOTIMING: + LD A, (EZ80_PLT_IOWS) + BIT 7, A + JR NZ, EZ80_RPT_ICYC + + CALL PRTDECB + CALL PRTSTRD + .TEXT " I/O W/S, $" + JR EZ80_RPT_FSH_TIMINGS + +EZ80_RPT_ICYC: + AND $7F + CALL PRTDECB + CALL PRTSTRD + .TEXT " I/O B/C, $" + +EZ80_RPT_FSH_TIMINGS: + LD A, (EZ80_PLT_FLSHWS) + CALL PRTDECB + CALL PRTSTRD + .TEXT " FSH W/S$" + RET + +EZ80_RPT_FIRMWARE: + CALL PRTSTRD + .TEXT "\r\neZ80 Firmware: $" + + LD A, (EZ80_PLT_VERSION+3) ; MAJOR VERSION NUMBER + CALL PRTDECB + CALL PC_PERIOD + LD A, (EZ80_PLT_VERSION+2) ; MINOR VERSION NUMBER + CALL PRTDECB + CALL PC_PERIOD + LD A, (EZ80_PLT_VERSION+1) ; REVISION NUMBER + CALL PRTDECB + CALL PC_PERIOD + LD A, (EZ80_PLT_VERSION) ; PATCH NUMBER + CALL PRTDECB + + CALL PRTSTRD + .TEXT " 20$" + LD A, (EZ80_BUILD_DATE+2) ; YEAR + CALL PRTDECB + CALL PC_DASH + LD A, (EZ80_BUILD_DATE+1) ; MONTH + CALL PC_LEADING_ZERO + CALL PRTDECB + CALL PC_DASH + LD A, (EZ80_BUILD_DATE) ; DAY + CALL PC_LEADING_ZERO + CALL PRTDECB + + LD A, (EZ80_ALT_FIRM) + OR A + RET Z + CALL PRTSTRD + .TEXT " (ALT)$" + RET + +PC_LEADING_ZERO: + CP 10 + RET NC + + PUSH AF + LD A, '0' + JP PC_PRTCHR + +PC_DASH: + PUSH AF + LD A, '-' + JP PC_PRTCHR + +EZ80_PLT_MEMWS: + .DB EZ80_MEM_WS +EZ80_PLT_IOWS: + .DB EZ80_IO_WS +EZ80_PLT_FLSHWS: + .DB EZ80_FLSH_WS + +EZ80_PLT_VERSION: + .DB 0, 0, 0, 0 + +EZ80_ALT_FIRM: + .DB 0 + +EZ80_BUILD_DATE: + .DB 0, 0, 0 ; DAY, MONTH, YEAR + +; ez80 helper functions/instructions + +_EZ80_CPY_EHL_TO_UHL: + PUSH IX + PUSH AF + .DB $5B, $DD, $21, $00, $00, $00 ; LD.LIL IX, 0 + .DB $49, $DD, $39 ; ADD.L IX, SP + .DB $49, $E5 ; PUSH.L HL + .DB $5B, $DD, $73, $FF ; LD.LIL (IX-1), E + .DB $49, $E1 ; POP.L HL + POP AF + POP IX + RET + +_EZ80_CPY_UHL_TO_EHL: + PUSH IX + .DB $5B, $DD, $21, $00, $00, $00 ; LD.LIL IX, 0 + .DB $49, $DD, $39 ; ADD.L IX, SP + .DB $49, $E5 ; PUSH.L HL + .DB $5B, $DD, $5E, $FF ; LD.LIL E, (IX-1) + .DB $49, $E1 ; POP.L HL + POP IX + RET diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc new file mode 100644 index 00000000..d52d744a --- /dev/null +++ b/Source/HBIOS/ez80instr.inc @@ -0,0 +1,138 @@ +; +;================================================================================================== +; HELPER MACROS FOR TARGETING EZ80 CPU INSTRUCTIONS +;================================================================================================== + +; +; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION +; +#IF (CPUFAM == CPU_EZ80) + ; RST.L $08 + #DEFINE EZ80_IO .DB $49, $CF + ; RST.L $10 + #DEFINE EZ80_FN .DB $49, $D7 + + #DEFINE EZ80_UTIL_VER_EXCH XOR A \ LD B, 0 \ EZ80_FN + #DEFINE EZ80_UTIL_SET_BUSTM XOR A \ LD B, 3 \ EZ80_FN + #DEFINE EZ80_UTIL_SET_BUSFQ XOR A \ LD B, 4 \ EZ80_FN + #DEFINE EZ80_UTIL_GET_CPU_FQ XOR A \ LD B, 5 \ EZ80_FN + #DEFINE EZ80_UTIL_DEBUG XOR A \ LD B, 7 \ EZ80_FN + #DEFINE EZ80_UTIL_MEMTM_SET XOR A \ LD B, 8 \ EZ80_FN + #DEFINE EZ80_UTIL_IOTM_SET XOR A \ LD B, 9 \ EZ80_FN + #DEFINE EZ80_UTIL_MEMTM_GET XOR A \ LD B, 10 \ EZ80_FN + #DEFINE EZ80_UTIL_IOTM_GET XOR A \ LD B, 11 \ EZ80_FN + #DEFINE EZ80_UTIL_MEMTMFQ_SET XOR A \ LD B, 12 \ EZ80_FN + #DEFINE EZ80_UTIL_IOTMFQ_SET XOR A \ LD B, 13 \ EZ80_FN + #DEFINE EZ80_UTIL_FLSHWS_SET XOR A \ LD B, 14 \ EZ80_FN + #DEFINE EZ80_UTIL_FLSHWS_GET XOR A \ LD B, 15 \ EZ80_FN + #DEFINE EZ80_UTIL_FLSHFQ_SET XOR A \ LD B, 16 \ EZ80_FN + + #DEFINE EZ80_RTC_INIT LD A, 1 \ LD B, 0 \ EZ80_FN + #DEFINE EZ80_RTC_GET_TIME LD A, 1 \ LD B, 1 \ EZ80_FN + #DEFINE EZ80_RTC_SET_TIME LD A, 1 \ LD B, 2 \ EZ80_FN + + #DEFINE EZ80_TMR_GET_TICKS LD A, 2 \ LD B, 0 \ EZ80_FN + #DEFINE EZ80_TMR_GET_SECONDS LD A, 2 \ LD B, 1 \ EZ80_FN + #DEFINE EZ80_TMR_SET_TICKS LD A, 2 \ LD B, 2 \ EZ80_FN + #DEFINE EZ80_TMR_SET_SECONDS LD A, 2 \ LD B, 3 \ EZ80_FN + #DEFINE EZ80_TMR_GET_FREQTICK LD A, 2 \ LD B, 4 \ EZ80_FN + #DEFINE EZ80_TMR_SET_FREQTICK LD A, 2 \ LD B, 5 \ EZ80_FN + #DEFINE EZ80_TMR_THROTTLE_START LD A, 2 \ LD B, 6 \ EZ80_FN + #DEFINE EZ80_TMR_THROTTLE_WAIT LD A, 2 \ LD B, 7 \ EZ80_FN + #DEFINE EZ80_TMR_INT_DISABLE LD A, 2 \ LD B, 8 \ EZ80_FN + #DEFINE EZ80_TMR_INT_ENABLE LD A, 2 \ LD B, 9 \ EZ80_FN + #DEFINE EZ80_TMR_IS_TICK_ISR LD A, 2 \ LD B, 10 \ EZ80_FN + #DEFINE EZ80_TMR_DELAY LD A, 2 \ LD B, 11 \ EZ80_FN + + #DEFINE EZ80_THROTTLE_START(p,store) \ + #DEFCONT \ PUSH AF + #DEFCONT \ PUSH BC + #DEFCONT \ PUSH HL + #DEFCONT \ LD A, 2 + #DEFCONT \ LD BC, (6 * 256) + p + #DEFCONT \ EZ80_FN + #DEFCONT \ LD (store), HL + #DEFCONT \ POP HL + #DEFCONT \ POP BC + #DEFCONT \ POP AF + + #DEFINE EZ80_THROTTLE_WAIT(p,store) \ + #DEFCONT \ PUSH AF + #DEFCONT \ PUSH BC + #DEFCONT \ PUSH HL + #DEFCONT \ LD A, 2 + #DEFCONT \ LD BC, (7 * 256) + p + #DEFCONT \ LD HL, (store) + #DEFCONT \ EZ80_FN + #DEFCONT \ LD (store), HL + #DEFCONT \ POP HL + #DEFCONT \ POP BC + #DEFCONT \ POP AF + + #DEFINE EZ80_UART_IN LD A, 3 \ LD B, 0 \ EZ80_FN + #DEFINE EZ80_UART_OUT LD A, 3 \ LD B, 1 \ EZ80_FN + #DEFINE EZ80_UART_IN_STAT LD A, 3 \ LD B, 2 \ EZ80_FN + #DEFINE EZ80_UART_OUT_STAT LD A, 3 \ LD B, 3 \ EZ80_FN + #DEFINE EZ80_UART_CONFIG LD A, 3 \ LD B, 4 \ EZ80_FN + #DEFINE EZ80_UART_QUERY LD A, 3 \ LD B, 5 \ EZ80_FN + #DEFINE EZ80_UART_RESET LD A, 3 \ LD B, 6 \ EZ80_FN + + #DEFINE RET.L .DB $49 \ RET + + #DEFINE IN0_A(p) .DB $ED,$38,p + #DEFINE IN0_B(p) .DB $ED,$00,p + #DEFINE IN0_C(p) .DB $ED,$08,p + #DEFINE IN0_D(p) .DB $ED,$10,p + #DEFINE IN0_E(p) .DB $ED,$18,p + #DEFINE IN0_H(p) .DB $ED,$20,p + #DEFINE IN0_L(p) .DB $ED,$28,p + + #DEFINE OUT0_A(p) .DB $ED,$39,p + #DEFINE OUT0_B(p) .DB $ED,$01,p + #DEFINE OUT0_C(p) .DB $ED,$09,p + #DEFINE OUT0_D(p) .DB $ED,$11,p + #DEFINE OUT0_E(p) .DB $ED,$19,p + #DEFINE OUT0_H(p) .DB $ED,$21,p + #DEFINE OUT0_L(p) .DB $ED,$29,p + + #DEFINE LDHLMM.LIL(Mmn) \ + #defcont \ .DB $5B + #defcont \ LD HL, Mmn + #defcont \ .DB (Mmn >> 16) & $FF + + #DEFINE LDBCMM.LIL(Mmn) \ + #defcont \ .DB $5B + #defcont \ LD BC, Mmn + #defcont \ .DB (Mmn >> 16) & $FF + + #DEFINE SBCHLBC.LIL \ + #defcont \ .DB $49 + #defcont \ SBC HL, BC + +IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O + + #DEFINE OUT_NN_A(addr) \ + #DEFCONT \ PUSH BC + #DEFCONT \ LD BC, IO_SEGMENT << 8 | addr + #DEFCONT \ OUT (C), A + #DEFCONT \ POP BC + + #DEFINE IN_A_NN(addr) \ + #DEFCONT \ LD A, IO_SEGMENT + #DEFCONT \ IN A, (addr) + +#define EZ80_CPY_EHL_TO_UHL CALL _EZ80_CPY_EHL_TO_UHL +#define EZ80_CPY_UHL_TO_EHL CALL _EZ80_CPY_UHL_TO_EHL + +#ELSE + #DEFINE EZ80_IO + + #DEFINE EZ80_THROTTLE_START(p,store) + #DEFINE EZ80_THROTTLE_WAIT(p,store) + +IO_SEGMENT .EQU $FF ; THE UPPER 8-BIT ADDRESS FOR I/O + + #DEFINE OUT_NN_A(addr) OUT (addr), A + #DEFINE IN_A_NN(addr) IN A, (addr) + +#ENDIF diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm new file mode 100644 index 00000000..8576962f --- /dev/null +++ b/Source/HBIOS/ez80rtc.asm @@ -0,0 +1,168 @@ +; +;================================================================================================== +; EZ80 ON-CHIP RTC DRIVER +;================================================================================================== +; +EZ80RTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) +; +; RTC DEVICE INITIALIZATION ENTRY + +EZ80RTC_INIT: + ; display driver install message + ; delegate init function to firmware + ; install dispatcher + ; dispatch local routine that delgates to firmware routines + + LD A, (RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? + OR A ; SET FLAGS + RET NZ ; IF ALREADY ACTIVE, ABORT + + CALL NEWLINE ; FORMATTING + PRTS("EZ80 RTC: POWERED $") + + EZ80_RTC_INIT() + JR Z, RTC_POWERED + + PUSH AF + PRTS("NOT POWERED$") + POP AF + RET + +RTC_POWERED: + ; DISPLAY CURRENT TIME + LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED + EZ80_RTC_GET_TIME() + + LD HL, EZ80RTC_BCDBUF ; POINT TO BCD BUF + CALL PRTDT ; DISPLAY THIS TIME +; + LD BC, EZ80RTC_DISPATCH + CALL RTC_SETDISP +; + XOR A ; SIGNAL SUCCESS + RET + +; +; RTC DEVICE FUNCTION DISPATCH ENTRY +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; B: FUNCTION (IN) +; +EZ80RTC_DISPATCH: + LD A,B ; GET REQUESTED FUNCTION + AND $0F ; ISOLATE SUB-FUNCTION + JP Z,EZ80RTC_GETTIM ; GET TIME + DEC A + JP Z,EZ80RTC_SETTIM ; SET TIME + DEC A + JP Z,EZ80RTC_GETBYT ; GET NVRAM BYTE VALUE + DEC A + JP Z,EZ80RTC_SETBYT ; SET NVRAM BYTE VALUE + DEC A + JP Z,EZ80RTC_GETBLK ; GET NVRAM DATA BLOCK VALUES + DEC A + JP Z,EZ80RTC_SETBLK ; SET NVRAM DATA BLOCK VALUES + DEC A + JP Z,EZ80RTC_GETALM ; GET ALARM + DEC A + JP Z,EZ80RTC_SETALM ; SET ALARM + DEC A + JP Z,EZ80RTC_DEVICE ; REPORT RTC DEVICE INFO + SYSCHKERR(ERR_NOFUNC) + RET +; +; RTC GET TIME +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: DATE/TIME BUFFER (OUT) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSS +; 24 HOUR TIME FORMAT IS ASSUMED +; +EZ80RTC_GETTIM: + PUSH HL + LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED + EZ80_RTC_GET_TIME() ; (HL) <- TIME + + LD A, BID_BIOS ; COPY FROM BIOS BANK + LD (HB_SRCBNK), A ; SET IT + LD A, (HB_INVBNK) ; COPY TO CURRENT USER BANK + LD (HB_DSTBNK), A ; SET IT + LD HL, EZ80RTC_BCDBUF ; SOURCE ADR + POP DE ; DEST ADR + LD BC, EZ80RTC_BUFSIZ ; LENGTH + CALL HB_BNKCPY ; COPY THE CLOCK DATA + + XOR A ; SIGNAL SUCCESS + RET +; +; +; RTC SET TIME +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: DATE/TIME BUFFER (IN) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSSWW +; 24 HOUR TIME FORMAT IS ASSUMED +; +EZ80RTC_SETTIM: + ; COPY TO BCD BUF + LD A,(HB_INVBNK) ; COPY FROM CURRENT USER BANK + LD (HB_SRCBNK),A ; SET IT + LD A,BID_BIOS ; COPY TO BIOS BANK + LD (HB_DSTBNK),A ; SET IT + LD DE,EZ80RTC_BCDBUF ; DEST ADR + LD BC,EZ80RTC_BUFSIZ ; LENGTH + CALL HB_BNKCPY ; COPY THE RPC DATA + + LD HL, EZ80RTC_BCDBUF_EXT ; POINT TO BCD BUF EXTENDED + LD (HL), $20 ; CENTURY NOT SUPPORT BY HBIOS + EZ80_RTC_SET_TIME() ; (HL) -> SYSTEM TIME + + XOR A ; SIGNAL SUCCESS + RET +; +; RTC GET NVRAM BYTE +; C: INDEX +; E: VALUE (OUTPUT) +; A:0 IF OK, ERR_RANGE IF OUT OF RANGE +; +EZ80RTC_GETBYT: + SYSCHKERR(ERR_NOTIMPL) + ; XOR A ; SIGNAL SUCCESS + RET ; AND RETURN + + +; RTC SET NVRAM BYTE +; C: INDEX +; E: VALUE +; A:0 IF OK, ERR_RANGE IF OUT OF RANGE +; +EZ80RTC_SETBYT: + SYSCHKERR(ERR_NOTIMPL) + ; XOR A ; SIGNAL SUCCESS + RET + +EZ80RTC_GETBLK: +EZ80RTC_SETBLK: +EZ80RTC_GETALM: +EZ80RTC_SETALM: + SYSCHKERR(ERR_NOTIMPL) + RET +; +; REPORT RTC DEVICE INFO +; +EZ80RTC_DEVICE: + LD D, RTCDEV_EZ80 ; D := DEVICE TYPE + LD E, 0 ; E := PHYSICAL DEVICE NUMBER + LD HL, 00 ; H := 0, DRIVER HAS NO MODES, L := 0, NO I/O ADDRESS + XOR A ; SIGNAL SUCCESS + RET + + +; REGISTER EXTRACTED VALUES +; +EZ80RTC_BCDBUF_EXT: +EZ80RTC_CN .DB 20 ; CENTURY +EZ80RTC_BCDBUF: +EZ80RTC_YR .DB 24 +EZ80RTC_MO .DB 01 +EZ80RTC_DT .DB 01 +EZ80RTC_HH .DB 00 +EZ80RTC_MM .DB 00 +EZ80RTC_SS .DB 00 diff --git a/Source/HBIOS/ez80systmr.asm b/Source/HBIOS/ez80systmr.asm new file mode 100644 index 00000000..00f1b6f6 --- /dev/null +++ b/Source/HBIOS/ez80systmr.asm @@ -0,0 +1,86 @@ +; +;================================================================================================== +; EZ80 50/60HZ TIMER TICK DRIVER +;================================================================================================== +; +; Configuration options: +; EZ80TIMER: +; 0 -> No timer tick interrupts MARSHALLED to HBIOS. +; HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented here and DELEGATED to eZ80 firmware functions +; 1 -> Timer tick interrupts MARSHALLED to HBIOS. +; HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented within HBIOS +; + +#IF (EZ80TIMER == EZ80TMR_INT) +EZ80_TMR_INIT: + CALL NEWLINE ; FORMATTING + PRTS("EZ80 TIMER: INTERRUPTS ENABLED$") + + LD HL,EZ80_TMR_INT ; GET INT VECTOR + CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST + + EZ80_TMR_INT_ENABLE() ; INSTALL TIMER HOOK + RET + +EZ80_TMR_INT: + EZ80_TMR_IS_TICK_ISR() + RET Z ; NOT A EZ80 TIMER TICK + + CALL HB_TIMINT ; RETURN NZ - HANDLED + OR $FF + RET +#ENDIF +#IF (EZ80TIMER == EZ80TMR_FIRM) + +EZ80_TMR_INIT: + CALL NEWLINE ; FORMATTING + PRTS("EZ80 TIMER: FIRMWARE$") + RET +; ----------------------------------------------- +; Implementation of HBIOS SYS TIMER functions to +; delegate to eZ80 firmware functions + +; GET TIMER +; RETURNS: +; DE:HL: TIMER VALUE (32 BIT) +; +SYS_GETTIMER: + EZ80_TMR_GET_TICKS() + RET +; +; GET SECONDS +; RETURNS: +; DE:HL: SECONDS VALUE (32 BIT) +; C: NUM TICKS WITHIN CURRENT SECOND +; +SYS_GETSECS: + EZ80_TMR_GET_SECONDS() + + EZ80_CPY_UHL_TO_EHL ; E:HL{15:0} <- HL{23:0} + LD D, 0 + RET +; +; SET TIMER +; ON ENTRY: +; DE:HL: TIMER VALUE (32 BIT) +; +SYS_SETTIMER: + EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} + EZ80_TMR_SET_TICKS() + RET +; +; SET SECS +; ON ENTRY: +; DE:HL: SECONDS VALUE (32 BIT) +; +SYS_SETSECS: + EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} + + EZ80_TMR_SET_SECONDS() + RET + +#ENDIF +#IF (EZ80TIMER == EZ80TMR_NONE) +EZ80_TMR_INIT: + RET +#ENDIF diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm new file mode 100644 index 00000000..c113c577 --- /dev/null +++ b/Source/HBIOS/ez80uart.asm @@ -0,0 +1,323 @@ +; +;================================================================================================== +; eZ80 UART DRIVER (SERIAL PORT) +;================================================================================================== +; +; +; Supported Line Characteristics are encoded as follows in the DE register pair: +; +; | **Bits** | **Characteristic** | +; |---------:|----------------------------------------| +; | 15-14 | Reserved (set to 0) | +; | 13 | RTS (Not implemented) | +; | 12-8 | Baud Rate* (see below) | +; | 7 | DTR (Not implemented) | +; | 6 | XON/XOFF Flow Control (not implemented)| +; | 5 | Stick Parity (not implemented) | +; | 4 | Even Parity (set for true) | +; | 3 | Parity Enable (set for true) | +; | 2 | Stop Bits (0-> 1 BIT, 1-> 2 BITS) | +; | 1-0 | Data Bits (5-8 encoded as 0-3) | +; +; * The 5-bit Baud Rate value (V) is encoded as V = 75 * 2^X * 3^Y. The +; bits are defined as YXXXX. +; +; STICK & EVEN & PARITY -> MARK PARITY -> NOT SUPPORTED +; STICK & !EVEN & PARITY -> SPACE PARITY -> NOT SUPPORTED +; THEREFORE, MARK PARITY WILL BE INTERPRETED AS EVEN PARITY +; AND SPACE PARITY WILL BE INTERPRETED AS ODD PARITY + +UART0_LSR .EQU $C5 +UART0_THR .EQU $C0 +UART0_RBR .EQU $C0 + +LSR_THRE .EQU $20 +LSR_DR .EQU $01 + +EZUART_PREINIT: + LD BC, EZUART_FNTBL + LD DE, EZUART_CFG + CALL CIO_ADDENT + LD (EZUART_ID), A + + XOR A + RET + +EZUART_INIT: + CALL NEWLINE ; FORMATTING + PRTS("EZ80 UART: UART0$") + + XOR A + RET +; +; ### Function 0x00 -- Character Input (CIOIN) +; +; Read and return a Character (E). If no character(s) are available in the +; input buffer, this function will wait indefinitely. The returned Status +; (A) is a standard HBIOS result code. +; +; Outputs: +; E: Character +; A: Status (0-OK, else error) +; +EZUART_IN: + EZ80_UART_IN() ; CHAR RETURNED IN E + RET +; +; ### Function 0x01 -- Character Output (CIOOUT) +; +; Send the Character (E). If there is no space available in the unit's output +; buffer, the function will wait indefinitely. The returned Status (A) is a +; standard HBIOS result code. +; +; Inputs: +; E: Character +; +; Outputs: +; A: Status (0-OK, else error) +; +EZUART_OUT: + EZ80_UART_OUT() + RET +; +; ### Function 0x02 -- Character Input Status (CIOIST) +; +; Return the count of Characters Pending (A) in the input buffer. +; +; The value returned in register A is used as both a Status (A) code and +; the return value. Negative values (bit 7 set) indicate a standard HBIOS +; result (error) code. Otherwise, the return value represents the number +; of characters in the input buffer. +; +; Outputs: +; A: Status / Characters Pending +; +EZUART_IST: + EZ80_UART_IN_STAT() + RET +; +; ### Function 0x03 -- Character Output Status (CIOOST) +; +; Return the status of the output FIFO. 0 means the output FIFO is full and +; no more characters can be sent. 1 means the output FIFO is not full and at +; least one character can be sent. Negative values (bit 7 set) indicate a +; standard HBIOS result (error) code. +; +; Outputs +; A: Status (0 -> Full, 1 -> OK to send, < 0 -> HBIOS error code) +; +EZUART_OST: + EZ80_UART_OUT_STAT() + RET + +BAUD_RATE .EQU 115200 +; +; ### Function 0x04 -- Character I/O Initialization (CIOINIT) +; +; Apply the requested line Characteristics in (DE). The definition of the +; line characteristics value is described above. If DE contains -1 (0xFFFF), +; then the input and output buffers will be flushed and reset. +; The Status (A) is a standard HBIOS result code. +; +; Inputs: +; DE: Line Characteristics +; +; Outputs: +; A: Status (0-OK, else error) +; +EZUART_INITDEV: + LD A, D + CP E + JR NZ, NOT_RESET + CP $FF + JR NZ, NOT_RESET + + EZ80_UART_RESET() + RET + +NOT_RESET: + PUSH DE ; SAVE LINE CHARACTERISTICS + LD A, D + AND $1F ; ISOLATE ENCODED BAUD RATE + LD L, A ; PUT IN L + LD H, 0 ; H IS ALWAYS ZERO + LD DE, 75 ; BAUD RATE DECODE CONSTANT + CALL DECODE ; DE:HL := BAUD RATE + + EZ80_CPY_EHL_TO_UHL ; HL{23:0} <- E:HL{15:0} + + POP DE ; RESTORE REQUESTED LINE CHARACTERISTICS + LD A, E + AND 3 ; MASK FOR DATA BITS + RLCA + RLCA + RLCA ; SHIFT TO BITS 4:3 + LD D, A ; SAVE INTO D + + BIT 2, E ; STOP BITS (1 OR 2) + JR Z, ISKIP1 + SET 2, D ; APPLY TO D +ISKIP1: + + BIT 3, E ; PARITY ENABLE + JR Z, ISKIP2 + SET 1, D ; APPLY TO D +ISKIP2: + + BIT 4, E ; EVEN PARITY + JR Z, ISKIP3 + SET 0, D ; APPLY TO D +ISKIP3: + + ; D NOW CONTAINS THE LINE CONTROL BITS AS PER EZ80 FUNCTION + + EZ80_UART_CONFIG() + RET + +#DEFINE TRANSLATE(nnn,rrr) \ +#defcont \ LDBCMM.LIL(nnn) +#defcont \ SBCHLBC.LIL +#defcont \ JR NC, $+7 +#defcont \ LD D, rrr +#defcont \ JP uart_query_end +; +; ### Function 0x05 -- Character I/O Query (CIOQUERY) +; +; Returns the current Line Characteristics (DE). The definition of the line +; characteristics value is described above. The returned status (A) is a +; standard HBIOS result code. +; +; As the eZ80 UART driver supports more than the defined HBIOS baud rates, the +; returned baud rate may be an approximation of the actual baud rate. +; +; Outputs: +; DE: Line Characteristics +; A: Status (0-OK, else error) +; +EZUART_QUERY: + EZ80_UART_QUERY() + ; HL{23:0} := BAUD RATE + ; D = LINE CONTROL BITS + PUSH DE ; SAVE D + + OR A + ; HL24 bit has the baud rate, we need to convert to the 5 bit representation? + TRANSLATE(112, 00000b) ; BAUDRATE=75 (BETWEEN 0 AND 112) + TRANSLATE(187-112, 00001b) ; BAUDRATE=150 (BETWEEN 113 AND 187) + TRANSLATE(262-187, 10000b) ; BAUDRATE=225 (BETWEEN 188 AND 262) + TRANSLATE(375-262, 00010b) ; BAUDRATE=300 (BETWEEN 263 AND 375) + TRANSLATE(525-375, 10001b) ; BAUDRATE=450 (BETWEEN 376 AND 525) + TRANSLATE(750-525, 00011b) ; BAUDRATE=600 (BETWEEN 526 AND 750) + TRANSLATE(1050-750, 10010b) ; BAUDRATE=900 (BETWEEN 751 AND 1050) + TRANSLATE(1500-1050, 00100b) ; BAUDRATE=1200 (BETWEEN 1051 AND 1500) + TRANSLATE(2100-1500, 10011b) ; BAUDRATE=1800 (BETWEEN 1501 AND 2100) + TRANSLATE(3000-2100, 00101b) ; BAUDRATE=2400 (BETWEEN 2101 AND 3000) + TRANSLATE(4200-3000, 10100b) ; BAUDRATE=3600 (BETWEEN 3001 AND 4200) + TRANSLATE(6000-4200, 00110b) ; BAUDRATE=4800 (BETWEEN 4201 AND 6000) + TRANSLATE(8400-6000, 10101b) ; BAUDRATE=7200 (BETWEEN 6001 AND 8400) + TRANSLATE(12000-8400, 00111b) ; BAUDRATE=9600 (BETWEEN 8401 AND 12000) + TRANSLATE(16800-12000, 10110b) ; BAUDRATE=14400 (BETWEEN 12001 AND 16800) + TRANSLATE(24000-16800, 01000b) ; BAUDRATE=19200 (BETWEEN 16801 AND 24000) + TRANSLATE(33600-24000, 10111b) ; BAUDRATE=28800 (BETWEEN 24001 AND 33600) + TRANSLATE(48000-33600, 01001b) ; BAUDRATE=38400 (BETWEEN 33601 AND 48000) + TRANSLATE(67200-48000, 11000b) ; BAUDRATE=57600 (BETWEEN 48001 AND 67200) + TRANSLATE(96000-67200, 01010b) ; BAUDRATE=76800 (BETWEEN 67201 AND 96000) + TRANSLATE(134400-96000, 11001b) ; BAUDRATE=115200 (BETWEEN 96001 AND 134400) + TRANSLATE(192000-134400, 01011b) ; BAUDRATE=153600 (BETWEEN 134401 AND 192000) + TRANSLATE(268800-192000, 11010b) ; BAUDRATE=230400 (BETWEEN 192001 AND 268800) + TRANSLATE(384000-268800, 01100b) ; BAUDRATE=307200 (BETWEEN 268801 AND 384000) + TRANSLATE(537600-384000, 11011b) ; BAUDRATE=460800 (BETWEEN 384001 AND 537600) + TRANSLATE(768000-537600, 01101b) ; BAUDRATE=614400 (BETWEEN 537601 AND 768000) + TRANSLATE(1075200-768000, 11100b) ; BAUDRATE=921600 (BETWEEN 768001 AND 1075200) + TRANSLATE(1536000-1075200, 01110b) ; BAUDRATE=1228800 (BETWEEN 1075201 AND 1536000) + TRANSLATE(2150400-1536000, 11101b) ; BAUDRATE=1843200 (BETWEEN 1536001 AND 2150400) + TRANSLATE(3072000-2150400, 01111b) ; BAUDRATE=2457600 (BETWEEN 2150401 AND 3072000) + TRANSLATE(5529600-3072000, 11110b) ; BAUDRATE=3686400 (BETWEEN 3072001 AND 5529600) + + LD D, 11111b ; BAUDRATE=7372800 (>=5529601) +uart_query_end: + + POP BC ; B = LINE CONTROL BITS + +; Convert from line control settings from: +; +; B{0:1} = Parity (00 -> NONE, 01 -> NONE, 10 -> ODD, 11 -> EVEN) +; B{2} = Stop Bits (0 -> 1, 1 -> 2) +; B{3:4} = Data Bits (00 -> 5, 01 -> 6, 10 -> 7, 11 -> 8) +; B{5:5} = Hardware Flow Control CTS (0 -> OFF, 1 -> ON) +; +; to +; +; E{7} = TODO: DTR +; E{6} = NOT IMPLEMENTED: XON/XOFF Flow Control +; E{5} = NOT SUPPORTED: Stick Parity (set for true) +; E{4} = Even Parity (set for true) +; E{3} = Parity Enable (set for true) +; E{2} = Stop Bits (set for true) +; E{1:0} = Data Bits (5-8 encoded as 0-3) + + XOR A + OR 3 << 3 ; ISOLATE DATA BITS + AND B ; MASK IN DATA BITS + + RRCA ; SHIFT TO BITS 1:0 + RRCA + RRCA + LD H, A ; H{1:0} DATA BITS + + BIT 2, B ; STOP BITS + JR Z, SKIP1 + SET 2, H ; APPLY TO H + +SKIP1: + BIT 1, B ; PARITY ENABLE + JR Z, SKIP2 + SET 3, H ; APPLY TO H + +SKIP2: + BIT 0, B ; EVEN PARITY + JR Z, SKIP3 + SET 4, H ; APPLY TO H + +SKIP3: + LD E, H + XOR A + RET +; +; ### Function 0x06 -- Character I/O Device (CIODEVICE) +; +; Returns device information. The status (A) is a standard HBIOS result +; code. +; +; Outputs +; A: Status (0 - OK) +; C: Device Attribute (0 - RS/232) +; D: Device Type (CIODEV_EZ80UART) +; E: Physical Device Number +; H: Device Mode (0) +; L: Device I/O Base Address - Not Supported (0) +; +EZUART_DEVICE: + LD D, CIODEV_EZ80UART ; D := DEVICE TYPE + LD E, (IY) ; E := PHYSICAL UNIT + LD C, 0 ; C := DEVICE TYPE, 0x00 IS RS-232 + LD HL, 0 ; H := MODE, L := BASE I/O ADDRESS + + XOR A ; SIGNAL SUCCESS + RET + +EZUART_CFG: +EZUART_ID: .DB 0 + + +EZUART_FNTBL: + .DW EZUART_IN + .DW EZUART_OUT + .DW EZUART_IST + .DW EZUART_OST + .DW EZUART_INITDEV + .DW EZUART_QUERY + .DW EZUART_DEVICE +#IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2)) + .ECHO "*** INVALID EZUART FUNCTION TABLE ***\n" +#ENDIF diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm index d129c678..467b79bd 100644 --- a/Source/HBIOS/fd.asm +++ b/Source/HBIOS/fd.asm @@ -883,15 +883,15 @@ FD_DETECT: LD (FST_DOR),A ; AND PUT IN SHADOW REGISTER CALL FC_RESETFDC ; RESET FDC - IN A,(FDC_MSR) ; READ MSR + IN_A_NN(FDC_MSR) ; READ MSR ;CALL PC_SPACE ; *DEBUG* ;CALL PRTHEXBYTE ; *DEBUG* CP $D0 ; SPECIAL CASE: DATA PENDING? JR NZ,FD_DETECT1 ; NOPE, MOVE ALONG - IN A,(FDC_DATA) ; SWALLOW THE PENDING DATA + IN_A_NN(FDC_DATA) ; SWALLOW THE PENDING DATA CALL DLY32 ; SETTLE - IN A,(FDC_MSR) ; ... AND REREAD THE STATUS + IN_A_NN(FDC_MSR) ; ... AND REREAD THE STATUS ;CALL PC_SPACE ; *DEBUG* ;CALL PRTHEXBYTE ; *DEBUG* ; @@ -902,7 +902,7 @@ FD_DETECT1: ; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET ; DESIRED VALUE, SO TRY ONE MORE TIME CALL DLY32 ; WAIT A BIT - IN A,(FDC_MSR) ; ... AND REREAD THE STATUS + IN_A_NN(FDC_MSR) ; ... AND REREAD THE STATUS ;CALL PC_SPACE ; *DEBUG* ;CALL PRTHEXBYTE ; *DEBUG* CP $80 ; CHECK FOR CORRECT VALUE @@ -1464,7 +1464,7 @@ FC_SETUPSPECIFY: ; FC_SETDOR: LD (FST_DOR),A - OUT (FDC_DOR),A + OUT_NN_A(FDC_DOR) #IF (FDTRACE >= 3) CALL NEWLINE LD DE,FDSTR_DOR @@ -1483,7 +1483,7 @@ FC_SETDOR: ; FC_SETDCR LD (FST_DCR),A - OUT (FDC_DCR),A + OUT_NN_A(FDC_DCR) #IF (FDTRACE >= 3) CALL NEWLINE LD DE,FDSTR_DCR @@ -1656,11 +1656,11 @@ FOP: LD B,0 ; B IS LOOP COUNTER FOP_CLR1: CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR - IN A,(FDC_MSR) ; GET STATUS + IN_A_NN(FDC_MSR) ; GET STATUS AND 0C0H ; ISOLATE HIGH NIBBLE, RQM/DIO/NDM/CB CP 0C0H ; LOOKING FOR RQM=1, DIO=1, BYTES PENDING JR NZ,FOP_CMD1 ; NO BYTES PENDING, GO TO NEXT PHASE - IN A,(FDC_DATA) ; GET THE PENDING BYTE AND DISCARD + IN_A_NN(FDC_DATA) ; GET THE PENDING BYTE AND DISCARD DJNZ FOP_CLR1 JP FOP_TOFDCRDY ; OTHERWISE, TIMEOUT ; @@ -1676,7 +1676,7 @@ FOP_CMD2: ; START OF LOOP TO SEND NEXT BYTE FOP_CMD4: ; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR - IN A,(FDC_MSR) ; READ MAIN STATUS REGISTER + IN_A_NN(FDC_MSR) ; READ MAIN STATUS REGISTER AND 0C0H ; ISOLATE RQM/DIO CP 080H ; LOOKING FOR RQM=1, DIO=0 (FDC READY FOR A BYTE) JR Z,FOP_CMD6 ; GOOD, GO TO SEND BYTE @@ -1687,7 +1687,7 @@ FOP_CMD4: ; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE FOP_CMD6: ; SEND NEXT BYTE LD A,(HL) ; POINT TO NEXT BYTE TO SEND - OUT (FDC_DATA),A ; PUSH IT TO FDC + OUT_NN_A(FDC_DATA) ; PUSH IT TO FDC INC HL ; INCREMENT POINTER FOR NEXT TIME DEC D ; DECREMENT NUM BYTES LEFT TO SEND JR NZ,FOP_CMD2 ; DO NEXT BYTE @@ -1718,7 +1718,7 @@ FXR_NULL: LD BC,$7000 ; LOOP COUNTER, $7000 * 16us = ~485ms FXR_NULL1: CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR - IN A,(FDC_MSR) ; GET MSR + IN_A_NN(FDC_MSR) ; GET MSR AND 0E0H ; ISOLATE RQM/DIO/NDM CP 0C0H ; WE WANT RQM=1,DIO=1,NDM=0 (READY TO READ A BYTE W/ EXEC INACTIVE) JP Z,FOP_RES ; EXEC DONE, EXIT CLEAN W/O PULSING TC @@ -1749,13 +1749,13 @@ FXR_READ: LD (FCD_TO),A ; INIT TIMEOUT COUNTER FXRR1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER FXRR2: LD B,0 ; SETUP FOR 256 ITERATIONS -FXRR3: IN A,(FDC_MSR) ; GET MSR +FXRR3: IN_A_NN(FDC_MSR) ; GET MSR CP 0F0H ; WE WANT RQM=1,DIO=1,NDM=1,BUSY=1 (READY TO RECEIVE A BYTE W/ EXEC ACTIVE) JR Z,FXRR4 ; GOT IT, DO BYTE READ DJNZ FXRR3 ; NOT READY, LOOP IF COUNTER NOT ZERO JR FXRR5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC -FXRR4: IN A,(FDC_DATA) ; GET PENDING BYTE +FXRR4: IN_A_NN(FDC_DATA) ; GET PENDING BYTE LD (HL),A ; STORE IT IN BUFFER INC HL ; INCREMENT THE BUFFER POINTER DEC DE ; DECREMENT BYTE COUNT @@ -1792,13 +1792,13 @@ FXR_WRITE: LD (FCD_TO),A FXRW1 LD C,0 ; OUTER LOOP TIMEOUT COUNTER FXRW2: LD B,0 ; SETUP FOR 256 ITERATIONS -FXRW3: IN A,(FDC_MSR) ; GET MSR +FXRW3: IN_A_NN(FDC_MSR) ; GET MSR CP 0B0H ; WE WANT RQM=1,DIO=0,NDM=1,BUSY=1 (READY TO SEND A BYTE W/ EXEC ACTIVE) JR Z,FXRW4 ; GOT IT, DO BYTE WRITE DJNZ FXRW3 ; NOT READY, LOOP IF COUNTER NOT ZERO JR FXRW5 ; COUNTER ZERO, GO TO OUTER LOOP LOGIC FXRW4: LD A,(HL) ; GET NEXT BYTE TO WRITE - OUT (FDC_DATA),A ; WRITE IT + OUT_NN_A(FDC_DATA) ; WRITE IT INC HL ; INCREMENT THE BUFFER POINTER DEC DE ; DECREMENT LOOP COUNTER LD A,D @@ -1842,7 +1842,7 @@ FOP_RES0: FOP_RES1: CALL DELAY ; FDC MAY TAKE UP TO 12us TO UPDATE MSR - IN A,(FDC_MSR) ; READ MAIN STATUS REGISTER + IN_A_NN(FDC_MSR) ; READ MAIN STATUS REGISTER AND 0F0H ; ISOLATE RQM/DIO/EXEC/BUSY CP 0D0H ; LOOKING FOR RQM/DIO/BUSY JR Z,FOP_RES2 ; GOOD, GO TO RECEIVE BYTE @@ -1860,7 +1860,7 @@ FOP_RES2: ; PROCESS NEXT PENDING BYTE LD A,FRB_SIZ ; GET BUF SIZE CP D ; REACHED MAX? JR Z,FOP_BUFMAX ; HANDLE BUF MAX/EXIT - IN A,(FDC_DATA) ; GET THE BYTE + IN_A_NN(FDC_DATA) ; GET THE BYTE LD (HL),A ; SAVE VALUE INC HL ; INCREMENT BUF POS INC D ; INCREMENT BYTES RECEIVED @@ -2237,4 +2237,4 @@ FCD_FDCRDY .DB 0 ; FALSE MEANS FDC RESET NEEDED FD_DSKBUF .DW 0 FD_CURGEOM .EQU $ ; TWO BYTES BELOW FD_CURSPT .DB 0 ; CURRENT SECTORS PER TRACK -FD_CURHDS .DB 0 ; CURRENT HEADS \ No newline at end of file +FD_CURHDS .DB 0 ; CURRENT HEADS diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index bc70d828..fd9109a8 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -354,6 +354,9 @@ RTCDEF .SET RTCDEF | %00001000 ; INITIAL SPEED LOW #ENDIF DEVECHO "\n" #ENDIF + +#include "ez80instr.inc" + ; ;================================================================================================== ; Z80 PAGE ZERO, VECTORS, ETC. @@ -616,6 +619,22 @@ HBX_ROM: #ENDIF ; #IF (MEMMGR == MM_Z2) + +#IF (CPUFAM == CPU_EZ80) + BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE + JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE + RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT + ADD A,16 ; ADD 16 x 32K - RAM STARTS FROM 512K +; +HBX_ROM: + RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K + OUT_NN_A(MPGSEL_0) ; BANK_0: 0K - 16K + INC A ; + OUT_NN_A(MPGSEL_1) ; BANK_1: 16K - 32K + RET ; DONE + +#ELSE + BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT @@ -627,14 +646,17 @@ HBX_ROM: ; HBX_ROM: RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K + EZ80_IO() OUT (MPGSEL_0),A ; BANK_0: 0K - 16K INC A ; + EZ80_IO() OUT (MPGSEL_1),A ; BANK_1: 16K - 32K #IF (CPUFAM == CPU_Z280) PCACHE #ENDIF RET ; DONE #ENDIF +#ENDIF ; #IF (MEMMGR == MM_N8) BIT 7,A ; TEST BIT 7 FOR RAM VS. ROM @@ -1223,8 +1245,15 @@ HBX_INT_SP .EQU $ - 2 ; POP HL ; RESTORE HL ; + +#IF (CPUFAM == CPU_EZ80) + RET.L ; INTERRUPTS WILL BE ENABLED BY BY EZ80 FIRMWARE + ; CAN THEY BE ENABLED HERE - DOES THAT RISK RE-ENTRANT OF THE HANDLER? +#ELSE HB_EI ; ENABLE INTERRUPTS RETI ; AND RETURN +#ENDIF + ; #ENDIF ; @@ -1384,7 +1413,9 @@ HB_START: HB_RESTART: ; DI ; NO INTERRUPTS +#IF (CPUFAM != CPU_EZ80) IM 1 ; INTERRUPT MODE 1 +#ENDIF ; #IFDEF APPBOOT ; @@ -1423,6 +1454,7 @@ BOOTWAIT: ; ;LD A,(RTCDEFVAL) ; GET DEFAULT VALUE LD A,RTCDEF ; DEFAULT VALUE + EZ80_IO() OUT (RTCIO),A ; SET IT ; #IF (PLATFORM == PLT_N8) @@ -1434,6 +1466,7 @@ BOOTWAIT: LD A,RPH_DEFACR ; ENSURE RPH ACR OUT0 (RPH_ACR),A ; ... REGISTER IS INITIALIZED #ENDIF + ; ; INITIALIZE DIAGNOSTIC AND/OR FRONT PANEL LED(S) TO INDICATE THE ; SYSTEM IS ALIVE. WE HAVE NO RAM AT THIS TIME, SO WE CANNOT USE @@ -1447,9 +1480,12 @@ BOOTWAIT: LD A,DIAG_01 #ENDIF ; + EZ80_IO() OUT (FPLED_IO),A + #ENDIF ; + #IF (LEDENABLE) #IF ((LEDMODE == LEDMODE_STD) | (LEDMODE == LEDMODE_SC)) XOR A ; LED IS INVERTED, TURN IT ON @@ -1729,12 +1765,15 @@ ROMRESUME: ; REDUNDANT BECAUSE WE ARE ALREADY RUNNING IN THIS AREA. THE ; MAPPING OF THE SECOND 16K IS CRITICAL BECAUSE ALL ZETA 2 ; MMU REGISTERS WILL BE 0 AT RESET! + XOR A + EZ80_IO() OUT (MPGSEL_0),A ; PROG FIRST 16K MMU REGISTER INC A + EZ80_IO() OUT (MPGSEL_1),A ; PROG SECOND 16K MMU REGISTER #ENDIF -; +; #IF (PLATFORM == PLT_DUO) ; DUO HAS VARIABLE RAM SIZE. RAM ALWAYS STARTS AT 2048K. ; SETUP COMMON RAM FOR HIGHEST 32K OF RAM BASED ON TOTAL RAM. @@ -1746,11 +1785,14 @@ ROMRESUME: LD A,((ROMSIZE + RAMSIZE) / 16) - 2 #ENDIF ; + EZ80_IO() OUT (MPGSEL_2),A ; PROG THIRD 16K MMU REGISTER INC A + EZ80_IO() OUT (MPGSEL_3),A ; PROG FOURTH 16K MMU REGISTER ; ENABLE PAGING LD A,1 + EZ80_IO() OUT (MPGENA),A ; ENABLE MMU NOW ; #IF (PLATFORM == PLT_FZ80) @@ -1759,6 +1801,7 @@ ROMRESUME: OUT ($07),A #ENDIF #ENDIF + ; ;-------------------------------------------------------------------------------------------------- ; PROXY INSTALLATION @@ -1849,8 +1892,10 @@ S100MON_SKIP: ; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS ; CREATED. ; + LD A,(RTCDEFVAL) LD (HB_RTCVAL),A + EZ80_IO() OUT (RTCIO),A ; SET IT DIAG(1) ; REAPPLY CURRENT DIAG LED SETUP ; @@ -1998,7 +2043,7 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK ; ; NOTIFY THAT WE MADE THE TRANSITION! FPLEDS(DIAG_03) - DIAG(2) + DIAG(2) ; ; RECOVER DATA PASSED PRIOR TO RAM TRANSITION ; (HBX_LOC - 1) = BATCOND @@ -2047,6 +2092,7 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM ; OPERATING INTERRUPT MODE. NOTE THAT INTERRUPTS REMAIN ; DISABLED AT THIS POINT. ; +#IF (CPUFAM != CPU_EZ80) #IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180))) ; SETUP Z80 IVT AND INT MODE 2 LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS @@ -2083,6 +2129,7 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM IM 3 ; #ENDIF +#ENDIF ; ;-------------------------------------------------------------------------------------------------- ; APPLICATION BOOT INITIALIZATION @@ -2223,6 +2270,7 @@ HB_CLRIVT_Z: ; 2: Z8S180 - ORIGINAL S-CLASS, REV. K, AKA SL1960, NO ASCI BRG ; 3: Z8S180 - REVISED S-CLASS, REV. N, W/ ASCI BRG ; 4: Z8280 +; 5: eZ80 ; LD HL,0 ; L = 0 MEANS Z80 ; @@ -2276,6 +2324,10 @@ HB_CPU1: ; SOME DRIVERS NEED TO BE CALLED AS EARLY AS WE CAN ONE AN OPERATING ; ENVIRONMENT IS ESTABLISHED. ; +#IF (CPUFAM == CPU_EZ80) + ; THIS WILL RE-ASSIGN HB_CPUTYPE + CALL EZ80_PREINIT +#ENDIF #IF (SN76489ENABLE) ; SN76489 CHIP GENERATES UGLY NOISE AFTER HARDWARE RESET. ; WE CALL THIS DRIVER'S PREINIT ASAP TO SHUT OFF THE NOISE. @@ -2329,6 +2381,7 @@ HB_CPU1: ; ; INIT OSCILLATOR SPEED FROM CONFIG ; +#IF (CPUFAM != CPU_EZ80) LD HL,CPUOSC / 1000 ; OSC SPD IN KHZ LD (HB_CPUOSC),HL ; INIT HB_CPUOSC DEFAULT ; @@ -2353,6 +2406,7 @@ HB_CPU1: LD (HB_CPUOSC),HL ; RECORD MEASURED SPEED ; HB_CPU2: +#ENDIF ; ;-------------------------------------------------------------------------------------------------- ; FINALIZE OPERATING CPU SPEED @@ -2888,6 +2942,42 @@ PSCNX .EQU $ + 1 DJNZ PSCN1 ; #ENDIF + +#IF (CPUFAM == CPU_EZ80) +; +;-------------------------------------------------------------------------------------------------- +; DELAY LOOP TEST CALIBRATION +;-------------------------------------------------------------------------------------------------- +; +; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE +; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS +; AND BUS CYCLES +; +#IF FALSE + +PC_DR: .equ $009E +PC_DDR: .equ $009F + + ; ENABLE PC5 GPIO AS OUTPUT + LD BC, PC_DDR + XOR A + OUT (C), A + PUSH AF + + LD BC, PC_DR + LD D, 0 +LOOP: + POP AF + OUT (C), A + CPL + PUSH AF + + LD DE, 2 + CALL VDELAY + JR LOOP +#ENDIF +#ENDIF + ; ;-------------------------------------------------------------------------------------------------- ; CPU SPEED DETECTION ALIGNMENT TEST @@ -2960,13 +3050,24 @@ HB_Z280BUS: HB_Z280BUS1: PRTS("MHz$") ; SUFFIX #ENDIF + +#IF (CPUFAM == CPU_EZ80) + CALL EZ80_RPT_FIRMWARE +#ENDIF + ; ;-------------------------------------------------------------------------------------------------- ; DISPLAY CPU CONFIGURATION ;-------------------------------------------------------------------------------------------------- ; CALL NEWLINE +; +; DISPLAY MEMORY TIMINGS +; +#IF (CPUFAM == CPU_EZ80) + CALL EZ80_RPT_TIMINGS +#ELSE #IF (CPUFAM == CPU_Z280) LD A,Z280_MEMLOWAIT CALL PRTDECB @@ -2985,6 +3086,13 @@ HB_Z280BUS1: CALL PRTSTRD .TEXT " MEM W/S, $" #ENDIF +#ENDIF ; CPUFAM = CPU_EZ80 +; +; DISPLAY I/O TIMINGS +; +#IF (CPUFAM == CPU_EZ80) + ; ALREADY REPORTED BY DRIVER +#ELSE LD A,1 #IF (CPUFAM == CPU_Z180) LD A,Z180_IOWAIT + 1 @@ -3003,6 +3111,10 @@ HB_Z280BUS1: CALL PRTSTRD .TEXT " INT W/S$" #ENDIF +#ENDIF //CPUFAM = CPU_EZ80 +; +; DISPLAY INTERRUPT MODE +; #IF (INTMODE > 0) CALL PRTSTRD .TEXT ", INT MODE $" @@ -3693,6 +3805,9 @@ HB_PCINITTBL: #IF (SIOENABLE) .DW SIO_PREINIT #ENDIF +#IF (EZ80UARTENABLE) + .DW EZUART_PREINIT +#ENDIF #IF (ACIAENABLE) .DW ACIA_PREINIT #ENDIF @@ -3777,6 +3892,9 @@ HB_INITTBL: #IF (SIOENABLE) .DW SIO_INIT #ENDIF +#IF (EZ80UARTENABLE) + .DW EZUART_INIT +#ENDIF #IF (ACIAENABLE) .DW ACIA_INIT #ENDIF @@ -3807,6 +3925,13 @@ HB_INITTBL: #IF (RP5RTCENABLE) .DW RP5RTC_INIT #ENDIF +#IF (EZ80RTCENABLE) + .DW EZ80RTC_INIT +#ENDIF +#IF (CPUFAM == CPU_EZ80) + ; INITALISE ONE OF THE SUPPORTED SYSTEM TIMER TICKS DRIVERS + .DW EZ80_TMR_INIT +#ENDIF #IF (VDUENABLE) .DW VDU_INIT #ENDIF @@ -5122,6 +5247,11 @@ SYS_GETFN: POP DE ; ... TO DE RET ; AF STILL HAS RESULT OF CALC ; +#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM)) +; IMPLEMENTED IN EZ80DRV.ASM +; +#ELSE +; ; GET TIMER ; RETURNS: ; DE:HL: TIMER VALUE (32 BIT) @@ -5134,6 +5264,12 @@ SYS_GETTIMER: LD C, TICKFREQ XOR A RET +#ENDIF +; +#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM)) +; IMPLEMENTED IN EZ80DRV.ASM +; +#ELSE ; ; GET SECONDS ; RETURNS: @@ -5146,11 +5282,12 @@ SYS_GETSECS: CALL LD32 LD A,(HB_SECTCK) HB_EI - NEG ; CONVERT DOWNCOUNTER TO UPCOUNTER + NEG ; CONVERT DOWNCOUNTER TO UPCOUNTER ADD A,TICKFREQ LD C,A XOR A RET +#ENDIF ; ; GET BOOT INFORMATION ; RETURNS: @@ -5363,6 +5500,11 @@ SYS_SETBOOTINFO: XOR A RET ; +#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM)) +; IMPLEMENTED IN EZ80DRV.ASM +; +#ELSE +; ; SET TIMER ; ON ENTRY: ; DE:HL: TIMER VALUE (32 BIT) @@ -5374,6 +5516,11 @@ SYS_SETTIMER: HB_EI XOR A RET +#ENDIF +#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM)) +; IMPLEMENTED IN EZ80DRV.ASM +; +#ELSE ; ; SET SECS ; ON ENTRY: @@ -5386,6 +5533,7 @@ SYS_SETSECS: HB_EI XOR A RET +#ENDIF ; ; SET SYSTEM CPU SPEED ATTRIBUTES ; ON ENTRY: @@ -7329,7 +7477,9 @@ FP_SETLEDS: #IF (FPLED_INV) XOR $FF ; INVERT BITS IF NEEDED #ENDIF - OUT (FPLED_IO),A ; WRITE + + EZ80_IO + OUT (FPLED_IO),A ; WRITE FP_SETLEDS1: POP HL ; RESTORE HL RET ; DONE @@ -7356,6 +7506,8 @@ FP_GETSWITCHES: FP_ACTIVE: FPSW_ACTIVE .DB TRUE FPLED_ACTIVE .DB TRUE + +#IF (CPUFAM != CPU_EZ80) ; eZ80 WILL RETURNED ITS MEASURED CPUOSC - SO NO NEED FOR DETECTION HERE ; ;================================================================================================== ; CPU SPEED DETECTION USING DS-1302 RTC @@ -7474,6 +7626,7 @@ HB_CPUSPD2: ; HANDLE NO RTC OR NOT TICKING OR $FF ; SIGNAL ERROR RET ; AND DONE +#ENDIF ; CPUFAM != CPU_EZ80 ; HB_UTIL_END .EQU $ ; @@ -7943,6 +8096,7 @@ HB_CPU_STR: .TEXT " Z80$" .TEXT " Z8S180-K$" .TEXT " Z8S180-N$" .TEXT " Z80280$" + .TEXT " eZ80$" ; PS_STRNUL .TEXT "--$" ; DISPLAY STRING FOR NUL VALUE ; @@ -8605,6 +8759,50 @@ SIZ_YM2612 .EQU $ - ORG_YM2612 MEMECHO " bytes.\n" #ENDIF ; +; +#IF (CPUFAM == CPU_EZ80) + MEMECHO "EZ80 DRIVERS\n" +ORG_EZ80DRVS .EQU $ +; +ORG_EZ80CPUDRV .EQU $ + #INCLUDE "ez80cpudrv.asm" +SIZ_EZ80CPUDRV .EQU $ - ORG_EZ80CPUDRV + MEMECHO " EZ80 CPU DRIVER occupies " + MEMECHO SIZ_EZ80CPUDRV + MEMECHO " bytes.\n" +; +ORG_EZ80SYSTMR .EQU $ + #INCLUDE "ez80systmr.asm" +SIZ_EZ80SYSTMR .EQU $ - ORG_EZ80SYSTMR + MEMECHO " EZ80 SYS TIMER occupies " + MEMECHO SIZ_EZ80SYSTMR + MEMECHO " bytes.\n" +; +#IF (EZ80RTCENABLE) +ORG_EZ80RTC .EQU $ + #INCLUDE "ez80rtc.asm" +SIZ_EZ80RTC .EQU $ - ORG_EZ80RTC + MEMECHO " EZ80 RTC occupies " + MEMECHO SIZ_EZ80RTC + MEMECHO " bytes.\n" +#ENDIF +; +#IF (EZ80UARTENABLE) +ORG_EZU .EQU $ + #INCLUDE "ez80uart.asm" +SIZ_EZU .EQU $ - ORG_EZU + MEMECHO " EZ80 UART occupies " + MEMECHO SIZ_EZU + MEMECHO " bytes.\n" +#ENDIF + +SIZ_EZ80DRVS .EQU $ - ORG_EZ80DRVS + MEMECHO " Total " + MEMECHO SIZ_EZ80DRVS + MEMECHO " bytes.\n" + +#ENDIF + MEMECHO "RTCDEF=" MEMECHO RTCDEF MEMECHO "\n" diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index caecfc9e..7c27b975 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -161,6 +161,7 @@ PLT_MON .EQU 20 ; MONSPUTER PLT_GMZ180 .EQU 21 ; GENESIS Z180 SYSTEM PLT_NABU .EQU 22 ; NABU PERSONAL COMPUTER PLT_FZ80 .EQU 23 ; S100 FPGA Z80 +PLT_RCEZ80 .EQU 24 ; RCBUS W/ eZ80 ; ; HBIOS GLOBAL ERROR RETURN VALUES ; @@ -327,6 +328,7 @@ CIODEV_ESPSER .EQU $0D CIODEV_SCON .EQU $0E CIODEV_EF .EQU $0F CIODEV_SSER .EQU $10 +CIODEV_EZ80UART .EQU $11 ; ; SUB TYPES OF CHAR DEVICES ; @@ -362,6 +364,7 @@ RTCDEV_INT .EQU $03 ; PERIODIC INT TIMER RTCDEV_DS7 .EQU $04 ; DS1307 (I2C) RTCDEV_RP5 .EQU $05 ; RP5C01 RTCDEV_DS5 .EQU $06 ; DS1305 (SPI) +RTCDEV_EZ80 .EQU $07 ; EZ80 ON-CHIP RTC ; ; DSKY DEVICE IDS ; diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm index 5cc77a0d..8056a120 100644 --- a/Source/HBIOS/ide.asm +++ b/Source/HBIOS/ide.asm @@ -1261,8 +1261,10 @@ IDE_GET8: ;LD C,IDE_REG_DATA LD C,(IY+IDE_IOBASE) LD B,A + EZ80_IO INIR LD B,A + EZ80_IO INIR RET ; @@ -1282,8 +1284,10 @@ IDE_GET16A: INI ; GET IT, SAVE IT, AND DEC B #ELSE LD C,D ; PORT FOR LSB + EZ80_IO INI ; GET IT, SAVE IT, AND DEC B LD C,E ; PORT FOR MSB + EZ80_IO INI ; GET IT, SAVE IT, AND DEC B #ENDIF DEC A @@ -1333,8 +1337,10 @@ IDE_PUT8: ;LD C,IDE_REG_DATA LD C,(IY+IDE_IOBASE) LD B,A + EZ80_IO OTIR LD B,A + EZ80_IO OTIR RET ; @@ -1354,8 +1360,10 @@ IDE_PUT16A: OUTI ; PUT IT AND DEC B #ELSE LD C,D ; PORT FOR LSB + EZ80_IO OUTI ; PUT IT AND DEC B LD C,E ; PORT FOR MSB + EZ80_IO OUTI ; PUT IT AND DEC B DEC A #ENDIF @@ -1590,6 +1598,7 @@ IDE_WAIT001: LD C,(IY+IDE_IOBASE) LD B,8 ; NUMBER OF REGISTERS TO CHECK IDE_WAIT002: + EZ80_IO IN A,(C) ; GET REGISTER VALUE ;CALL PC_SPACE ;CALL PRTHEXBYTE @@ -2015,6 +2024,7 @@ IDE_IN: LD C,(IY+IDE_IOBASE) ; 19TS ADD A,C ; 4TS LD C,A ; 4TS + EZ80_IO IN A,(C) ; 12TS POP BC ; 10TS EX (SP),HL ; RESTORE STACK ; 19TS @@ -2042,6 +2052,7 @@ IDE_OUT: ADD A,C LD C,A POP AF + EZ80_IO OUT (C),A POP BC EX (SP),HL ; RESTORE STACK @@ -2185,6 +2196,7 @@ IDE_REGDUMP: LD C,A LD B,7 IDE_REGDUMP1: + EZ80_IO IN A,(C) CALL PRTHEXBYTE DEC C diff --git a/Source/HBIOS/mky.asm b/Source/HBIOS/mky.asm index 34650e82..5cddbcfb 100644 --- a/Source/HBIOS/mky.asm +++ b/Source/HBIOS/mky.asm @@ -211,8 +211,10 @@ MKY_INIT: ; C - OUTPUT (ROW LINE SELECTION) LD A, PPICMD_COMMAND | PPICMD_GA_MODE_0 | PPICMD_GB_MODE_0 | PPICMD_A_IN | PPICMD_B_IN | PPICMD_CLOW_OUT | PPICMD_CHIGH_OUT + EZ80_IO OUT (MKY_REGCMD), A LD A, 64 ; CAPS OFF + EZ80_IO OUT (MKY_REGC), A RET ; @@ -368,8 +370,10 @@ MKY_SETLEDS: ; TURN THE CAPS LED LIGHT ON ; MKY_LEDCAPSON: + EZ80_IO IN A, (MKY_REGC) RES 6, A + EZ80_IO OUT (MKY_REGC), A RET ; @@ -378,8 +382,10 @@ MKY_LEDCAPSON: ; TURN THE CAPS LED LIGHT OFF ; MKY_LEDCAPSOFF: + EZ80_IO IN A, (MKY_REGC) SET 6, A + EZ80_IO OUT (MKY_REGC), A RET @@ -740,6 +746,7 @@ MKY_INTSCAN1: ; SCAN KEYBOARD AND STORE ALL COLUMN RESULTS PER ROW AT MKY_NEWKEY ; + EZ80_IO IN A, (MKY_REGC) ; READ AND MASK THE CURRENT STATE OF PPI PORT C AND $F0 LD D, A @@ -747,7 +754,9 @@ MKY_INTSCAN1: LD HL, MKY_NEWKEY LD C, MKY_REGC MKY_SCAN_LP: + EZ80_IO OUT (C), D ; SET ACTIVE ROW + EZ80_IO IN A, (MKY_REGB) ; READ ACTIVE COLUMN DATA LD (HL), A ; STORE COLUMN READ VALUE INC HL diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index 28a3bb99..7ab1cdbc 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -488,11 +488,14 @@ PPIDE_DETECT: ; LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT ; LD C,(IY+PPIDE_DATALO) ; PPI PORT A, DATALO LD A,$A5 ; TEST VALUE + EZ80_IO OUT (C),A ; PUSH VALUE TO PORT + EZ80_IO IN A,(C) ; GET PORT VALUE #IF (PPIDETRACE >= 3) CALL PC_SPACE @@ -1132,12 +1135,14 @@ PPIDE_GET: LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT ; ; SELECT READ/WRITE IDE REGISTER LD A,PPIDE_REG_DATA ; DATA REGISTER ;OUT (PPIDE_REG_CTL),A ; DO IT LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + EZ80_IO OUT (C),A ; DO IT LD E,A ; E := READ UNASSERTED XOR PPIDE_CTL_DIOR ; SWAP THE READ LINE BIT @@ -1160,19 +1165,25 @@ PPIDE_GET2: ; PPIDE_GET8: ; 8 BIT WIDE READ LOOP ; ENTER W/ C = PPIDE_REG_CTL + EZ80_IO OUT (C),D ; ASSERT READ DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO INI ; READ FROM LSB INC C ; LSB -> MSB INC C ; MSB -> CTL + EZ80_IO OUT (C),E ; DEASSERT READ + EZ80_IO OUT (C),D ; ASSERT READ DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO INI ; READ FROM LSB INC C ; LSB -> MSB INC C ; MSB -> CTL + EZ80_IO OUT (C),E ; DEASSERT READ DEC A JR NZ,PPIDE_GET8 ; LOOP UNTIL DONE @@ -1180,13 +1191,17 @@ PPIDE_GET8: ; 8 BIT WIDE READ LOOP ; PPIDE_GET16: ; 16 BIT WIDE READ LOOP ; ENTER W/ C = PPIDE_REG_CTL + EZ80_IO OUT (C),D ; ASSERT READ DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO INI ; READ FROM LSB INC C ; LSB -> MSB + EZ80_IO INI ; READ MSB FOR 16 BIT INC C ; MSB -> CTL + EZ80_IO OUT (C),E ; DEASSERT READ DEC A JR NZ,PPIDE_GET16 ; LOOP UNTIL DONE @@ -1218,12 +1233,14 @@ PPIDE_PUT: LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT ; ; SELECT READ/WRITE IDE REGISTER LD A,PPIDE_REG_DATA ; DATA REGISTER ;OUT (PPIDE_REG_CTL),A ; DO IT LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + EZ80_IO OUT (C),A ; DO IT LD E,A ; E := WRITE UNASSERTED XOR PPIDE_CTL_DIOW ; SWAP THE READ LINE BIT @@ -1248,17 +1265,23 @@ PPIDE_PUT2: PPIDE_PUT8: ; 8 BIT WIDE WRITE LOOP DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO OUTI ; WRITE NEXT BYTE (LSB) INC C ; LSB -> MSB INC C ; MSB -> CTL + EZ80_IO OUT (C),D ; ASSERT WRITE + EZ80_IO OUT (C),E ; DEASSERT WRITE DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO OUTI ; WRITE NEXT BYTE (LSB) INC C ; LSB -> MSB INC C ; MSB -> CTL + EZ80_IO OUT (C),D ; ASSERT WRITE + EZ80_IO OUT (C),E ; DEASSERT WRITE DEC A JR NZ,PPIDE_PUT8 ; LOOP UNTIL DONE @@ -1267,11 +1290,15 @@ PPIDE_PUT8: ; 8 BIT WIDE WRITE LOOP PPIDE_PUT16: ; 16 BIT WIDE WRITE LOOP DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO OUTI ; WRITE NEXT BYTE (LSB) INC C ; LSB -> MSB + EZ80_IO OUTI ; WRITE NEXT BYTE (MSB) INC C ; MSB -> CTL + EZ80_IO OUT (C),D ; ASSERT WRITE + EZ80_IO OUT (C),E ; DEASSERT WRITE DEC A JR NZ,PPIDE_PUT16 ; LOOP UNTIL DONE @@ -1321,6 +1348,7 @@ PPIDE_RESET: LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT ; ; IF A DSKYNG IS ACTIVE AND IS ON THE SAME PPI PORT AS THE PPIDE BEING @@ -1349,11 +1377,13 @@ PPIDE_RESET: LD A,PPIDE_CTL_RESET ;OUT (PPIDE_REG_CTL),A LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS + EZ80_IO OUT (C),A LD DE,20 ; DELAY 320US (SPEC IS >= 25US) CALL VDELAY XOR A ;OUT (PPIDE_REG_CTL),A + EZ80_IO OUT (C),A LD DE,20 CALL VDELAY @@ -1897,24 +1927,29 @@ PPIDE_IN: LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ; 7TS ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD ; 19TS + EZ80_IO OUT (C),A ; WRITE IT ; 12TS ; LD B,(HL) ; GET CTL PORT VALUE ; 7TS ;LD C,PPIDE_REG_CTL ; SETUP PORT TO WRITE ;LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS DEC C ; SET IDE ADDRESS ; 4TS + EZ80_IO OUT (C),B ; SET ADDRESS LINES ; 12TS SET 6,B ; TURN ON READ BIT ; 8TS + EZ80_IO OUT (C),B ; ASSERT READ LINE ; 12TS ; ;IN A,(PPIDE_REG_DATALO) ; GET DATA VALUE FROM DEVICE DEC C ; 4TS DEC C ; 4TS + EZ80_IO IN A,(C) ; GET DATA VALUE FROM DEVICE ; 12 INC C ; 4TS INC C ; 4TS ; RES 6,B ; CLEAR READ BIT ; 8TS + EZ80_IO OUT (C),B ; DEASSERT READ LINE ; 12TS POP BC ; RECOVER INCOMING BC ; 10TS INC HL ; POINT PAST PARM ; 6TS @@ -1931,6 +1966,7 @@ PPIDE_OUT: LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT POP AF ; RECOVER VALUE TO WRITE ; @@ -1938,18 +1974,22 @@ PPIDE_OUT: ;LD C,PPIDE_REG_CTL ; SETUP PORT TO WRITE ;LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS DEC C ; SET IDE ADDRESS + EZ80_IO OUT (C),B ; SET ADDRESS LINES SET 5,B ; TURN ON WRITE BIT + EZ80_IO OUT (C),B ; ASSERT WRITE LINE ; DEC C DEC C ;OUT (PPIDE_REG_DATALO),A ; SEND DATA VALUE TO DEVICE + EZ80_IO OUT (C),A ; SEND DATA VALUE TO DEVICE INC C INC C ; RES 5,B ; CLEAR WRITE BIT + EZ80_IO OUT (C),B ; DEASSERT WRITE LINE POP BC ; RECOVER INCOMING BC INC HL ; POINT PAST PARM @@ -2092,6 +2132,7 @@ PPIDE_REGDUMP: LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ;OUT (PPIDE_REG_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD + EZ80_IO OUT (C),A ; WRITE IT LD C,(IY+PPIDE_CTL) ; SET IDE ADDRESS LD E,PPIDE_REG_CMD @@ -2099,19 +2140,23 @@ PPIDE_REGDUMP: PPIDE_REGDUMP1: LD A,E ; REGISTER ADDRESS ;OUT (PPIDE_REG_CTL),A ; SET IT + EZ80_IO OUT (C),A ; REGISTER ADDRESS XOR PPIDE_CTL_DIOR ; SET BIT TO ASSERT READ LINE ;OUT (PPIDE_REG_CTL),A ; ASSERT READ + EZ80_IO OUT (C),A ; ASSERT READ ;IN A,(PPIDE_REG_DATALO) ; GET VALUE DEC C ; CTL -> MSB DEC C ; MSB -> LSB + EZ80_IO IN A,(C) ; GET VALUE INC C ; LSB -> MSB INC C ; MSB -> CTL CALL PRTHEXBYTE ; DISPLAY IT ;LD A,C ; RELOAD ADDRESS W/ READ UNASSERTED ;OUT (PPIDE_REG_CTL),A ; AND SET IT + EZ80_IO OUT (C),E ; RELOAD ADDRESS W/ READ UNASSERTED ;DEC C ; NEXT LOWER REGISTER DEC E ; NEXT LOWER REGISTER diff --git a/Source/HBIOS/rp5rtc.asm b/Source/HBIOS/rp5rtc.asm index 66753fcc..2a7b99a6 100644 --- a/Source/HBIOS/rp5rtc.asm +++ b/Source/HBIOS/rp5rtc.asm @@ -83,9 +83,11 @@ RP5RTC_INIT: RP5RTC_INIT1: ; ENSURE DEVICE IS RESET AND NOT IN TEST MODE LD A, REG_TEST ; SELECT TEST REGISTER + EZ80_IO OUT (RP5RTC_REG), A CALL DLY16 XOR A + EZ80_IO OUT (RP5RTC_DAT), A ; TURN OFF ALL TEST MODE BITS LD B, MODE_ALRMST @@ -94,8 +96,10 @@ RP5RTC_INIT1: CALL RP5RTC_ENTIME LD A, REG_12_24 ; SET TO 24 HOUR CLOCK + EZ80_IO OUT (RP5RTC_REG), A LD A, 1 + EZ80_IO OUT (RP5RTC_DAT), A CALL RP5RTC_RDTIM @@ -179,7 +183,9 @@ RP5RTC_GETBYT: LD B, MODE_RAM0 CALL RP5RTC_SETMD LD A, C ; SELECT NVRAM INDEX + EZ80_IO OUT (RP5RTC_REG), A + EZ80_IO IN A, (RP5RTC_DAT) AND $0F ; RETRIEVE UNIT NIBBLE LD E, A @@ -187,7 +193,9 @@ RP5RTC_GETBYT: LD B, MODE_RAM1 CALL RP5RTC_SETMD LD A, C ; SELECT NVRAM INDEX + EZ80_IO OUT (RP5RTC_REG), A + EZ80_IO IN A, (RP5RTC_DAT) AND $0F ; RETRIEVE UNIT NIBBLE RLCA @@ -218,14 +226,17 @@ RP5RTC_SETBYT: LD B, MODE_RAM0 CALL RP5RTC_SETMD LD A, C ; SELECT NVRAM INDEX + EZ80_IO OUT (RP5RTC_REG), A LD A, E AND $0F + EZ80_IO OUT (RP5RTC_DAT), A LD B, MODE_RAM1 CALL RP5RTC_SETMD LD A, C ; SELECT NVRAM INDEX + EZ80_IO OUT (RP5RTC_REG), A LD A, E AND $F0 @@ -233,6 +244,7 @@ RP5RTC_SETBYT: RRCA RRCA RRCA + EZ80_IO OUT (RP5RTC_DAT), A XOR A ; SIGNAL SUCCESS @@ -285,7 +297,7 @@ RP5RTC_SETTIM: LD (HB_DSTBNK),A ; SET IT LD DE,RP5RTC_BCDBUF ; DEST ADR LD BC,RP5RTC_BUFSIZ ; LENGTH - CALL HB_BNKCPY ; COPY THE CLOCK DATA + CALL HB_BNKCPY ; COPY THE RPC DATA ; LD B, MODE_TIMEST CALL RP5RTC_SETMD @@ -374,11 +386,14 @@ RP5RTC_RDTIM: ; MODE IN B (MODE_TIMEST, MODE_ALRMST, MODE_RAM0, MODE_RAM1) RP5RTC_SETMD: LD A, REG_MODE ; SELECT MODE REGISTER + EZ80_IO OUT (RP5RTC_REG), A + EZ80_IO IN A, (RP5RTC_DAT) AND MD_TIME | MD_ALRM OR B + EZ80_IO OUT (RP5RTC_DAT), A ; ASSIGN MODE RET @@ -391,14 +406,18 @@ RP5RTC_ENTIME: ; REGISTER IN B RP5RTC_RDVL: LD A, B ; SELECT UNIT REGISTER + EZ80_IO OUT (RP5RTC_REG), A + EZ80_IO IN A, (RP5RTC_DAT) AND $0F ; RETRIEVE UNIT NIBBLE LD L, A INC B LD A, B ; SELECT TENS REGISTER + EZ80_IO OUT (RP5RTC_REG), A + EZ80_IO IN A, (RP5RTC_DAT) AND $0F RLCA @@ -416,13 +435,16 @@ RP5RTC_RDVL: RP5RTC_WRVL: LD C, A LD A, B ; SELECT UNIT REGISTER + EZ80_IO OUT (RP5RTC_REG), A LD A, C ; WRITE C (ONLY LOW NIBBLE WILL BE USED) + EZ80_IO OUT (RP5RTC_DAT), A INC B LD A, B ; SELECT TENS REGISTER + EZ80_IO OUT (RP5RTC_REG), A LD A, C ; SHIFT TOP NIBBLE TO LOW NIBBLE @@ -430,6 +452,7 @@ RP5RTC_WRVL: RRCA RRCA RRCA + EZ80_IO OUT (RP5RTC_DAT), A ; WRITE IT RET diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 729bcf4d..dc3935e0 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -65,6 +65,7 @@ CPU_NONE .EQU 0 ; NO CPU TYPE DEFINED CPU_Z80 .EQU 1 ; Z80 FAMILY CPU_Z180 .EQU 2 ; Z180 FAMILY CPU_Z280 .EQU 3 ; Z280 FAMILY +CPU_EZ80 .EQU 4 ; eZ280 FAMILY ; ; BIOS MODE ; @@ -246,6 +247,12 @@ SNMODE_RC .EQU 1 ; RCBUS SOUND MODULE SNMODE_VGM .EQU 2 ; VGM ECB BOARD SNMODE_DUO .EQU 3 ; DUODYNE MEDIA-IO BOARD ; +; SN SOUND MODULE CHANNEL SELECTION +; +SNCHAN_BOTH .EQU 0 ; BOTH LEFT & RIGHT CHANNELS GET SAME OUTPUT +SNCHAN_LEFT .EQU 1 ; LEFT CHANNEL ONLY +SNCHAN_RIGHT .EQU 2 ; RIGHT CHANNEL ONLY +; ; TMS VIDEO MODE SELECTIONS ; TMSMODE_NONE .EQU 0 @@ -549,6 +556,12 @@ SCSI_CMD_RDCAP .EQU $25 SCSI_CMD_READ10 .EQU $28 SCSI_CMD_WRITE10 .EQU $2A ; +; EZ80 BUS MODES +; +EZ80WSMD_CALC .EQU 0 +EZ80WSMD_CYCLES .EQU 1 +EZ80WSMD_WAIT .EQU 2 +; #INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE ; ; INCLUDE Z180 REGISTER DEFINITIONS @@ -610,6 +623,7 @@ TM_TMS .EQU 2 TM_SIMH .EQU 3 TM_Z180 .EQU 4 TM_Z280 .EQU 5 +TM_EZ80 .EQU 6 ; SYSECHO "SYSTEM TIMER:" SYSTIM .EQU TM_NONE @@ -648,6 +662,11 @@ SYSTIM .SET TM_Z280 SYSECHO " Z280" #ENDIF #ENDIF +; + #IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_INT)) +SYSTIM .SET TM_EZ80 + SYSECHO " EZ80" + #ENDIF ; #IF SYSTIM == TM_NONE SYSECHO " NONE" diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm index cee4e578..00998e9a 100644 --- a/Source/HBIOS/tms.asm +++ b/Source/HBIOS/tms.asm @@ -220,6 +220,7 @@ TMS_INIT: ; #IF ((TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO)) LD A,$FF + EZ80_IO OUT (TMS_ACR),A ; INIT AUX CONTROL REG #ENDIF ; @@ -228,6 +229,7 @@ TMS_INIT: #IF ((TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO)) LD A,$FE + EZ80_IO OUT (TMS_ACR),A ; CLEAR VDP RESET #ENDIF ; @@ -273,6 +275,10 @@ TMS_INIT: RET ; TMS_INIT1: +#IF (TMSTIMENABLE) + PRTS(" INTERRUPT ENABLED$") + +#ENDIF CALL PC_SPACE LD A,TMS_COLS CALL PRTDEC8 @@ -582,10 +588,12 @@ TMS_READ: ; TMS_SET: HB_DI + EZ80_IO OUT (TMS_CMDREG),A ; WRITE IT TMS_IODELAY LD A,C ; GET THE DESIRED REGISTER OR $80 ; SET BIT 7 + EZ80_IO OUT (TMS_CMDREG),A ; SELECT THE DESIRED REGISTER TMS_IODELAY HB_EI @@ -601,11 +609,13 @@ TMS_WR: #IF (TMS80COLS) ; CLEAR R#14 FOR V9958 HB_DI - XOR A - OUT (TMS_CMDREG), A + XOR A + EZ80_IO + OUT (TMS_CMDREG), A TMS_IODELAY - LD A, $80 | 14 - OUT (TMS_CMDREG), A + LD A, $80 | 14 + EZ80_IO + OUT (TMS_CMDREG), A TMS_IODELAY HB_EI #ENDIF @@ -619,9 +629,11 @@ TMS_WR: TMS_RD: HB_DI LD A,L + EZ80_IO OUT (TMS_CMDREG),A TMS_IODELAY LD A,H + EZ80_IO OUT (TMS_CMDREG),A TMS_IODELAY HB_EI @@ -639,10 +651,12 @@ TMS_PROBE: CALL TMS_WR ; WRITE TEST PATTERN TO FIRST TWO BYTES LD A,$A5 ; FIRST BYTE + EZ80_IO OUT (TMS_DATREG),A ; OUTPUT ;TMS_IODELAY ; DELAY CALL DLY64 ; DELAY CPL ; COMPLEMENT ACCUM + EZ80_IO OUT (TMS_DATREG),A ; SECOND BYTE ;TMS_IODELAY ; DELAY CALL DLY64 ; DELAY @@ -652,11 +666,13 @@ TMS_PROBE: CALL TMS_RD ; READ TEST PATTERN LD C,$A5 ; VALUE TO EXPECT + EZ80_IO IN A,(TMS_DATREG) ; READ FIRST BYTE ;TMS_IODELAY ; DELAY CALL DLY64 ; DELAY CP C ; COMPARE RET NZ ; RETURN ON MISCOMPARE + EZ80_IO IN A,(TMS_DATREG) ; READ SECOND BYTE ;TMS_IODELAY ; DELAY CALL DLY64 ; DELAY @@ -677,6 +693,7 @@ TMS_CRTINIT: LD DE,$4000 ; 16KB TMS_CRTINIT1: XOR A + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY ; DELAY DEC DE @@ -703,7 +720,7 @@ TMS_CRTINIT2: LD A,%00000100 ; ONLY WTE BIT SET CALL TMS_SET ; DO IT #ENDIF - RET + RET ; ;---------------------------------------------------------------------- ; CLEAR SCREEN AND HOME CURSOR @@ -761,6 +778,7 @@ TMS_LOADFONT: LD DE,TMS_FNTSIZE TMS_LOADFONT1: LD A,(HL) + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY ; DELAY INC HL @@ -797,11 +815,13 @@ TMS_SETCUR: PUSH DE ; PRESERVE DE LD HL,(TMS_POS) ; GET CURSOR POSITION CALL TMS_RD ; SETUP TO READ VDU BUF + EZ80_IO IN A,(TMS_DATREG) ; GET REAL CHAR UNDER CURSOR TMS_IODELAY ; DELAY PUSH AF ; SAVE THE CHARACTER CALL TMS_WR ; SETUP TO WRITE TO THE SAME PLACE LD A,$FF ; REPLACE REAL CHAR WITH 255 + EZ80_IO OUT (TMS_DATREG),A ; DO IT TMS_IODELAY ; DELAY POP AF ; RECOVER THE REAL CHARACTER @@ -825,10 +845,11 @@ TMS_SETCUR0: ; MULT BY 8 FOR FONT INDEX LD B,8 ; 8 BYTES LD HL,TMS_BUF ; INTO BUFFER TMS_SETCUR1: ; READ GLYPH LOOP + EZ80_IO IN A,(TMS_DATREG) ; GET NEXT BYTE TMS_IODELAY ; IO DELAY LD (HL),A ; SAVE VALUE IN BUF - INC HL ; BUMP BUF POINTER + INC HL ; BUMP BUF POINTER DJNZ TMS_SETCUR1 ; LOOP FOR 8 BYTES ; ; NOW WRITE INVERTED GLYPH INTO FONT INDEX 255 @@ -840,6 +861,7 @@ TMS_SETCUR2: ; WRITE INVERTED GLYPH LOOP LD A,(HL) ; GET THE BYTE INC HL ; BUMP THE BUF POINTER XOR $FF ; INVERT THE VALUE + EZ80_IO OUT (TMS_DATREG),A ; WRITE IT TO VDU TMS_IODELAY ; IO DELAY DJNZ TMS_SETCUR2 ; LOOP FOR ALL 8 BYTES OF GLYPH @@ -856,6 +878,7 @@ TMS_CLRCUR: ; REMOVE VIRTUAL CURSOR FROM SCREEN LD HL,(TMS_POS) ; POINT TO CURRENT CURSOR POS CALL TMS_WR ; SET UP TO WRITE TO VDU LD A,(TMS_CURSAV) ; GET THE REAL CHARACTER + EZ80_IO OUT (TMS_DATREG),A ; WRITE IT TMS_IODELAY ; IO DELAY POP HL ; RECOVER HL @@ -895,6 +918,7 @@ TMS_PUTCHAR: LD HL,(TMS_POS) ; LOAD CURRENT POSITION INTO HL CALL TMS_WR ; SET THE WRITE ADDRESS POP AF ; RECOVER CHARACTER TO WRITE + EZ80_IO OUT (TMS_DATREG),A ; WRITE THE CHARACTER TMS_IODELAY LD HL,(TMS_POS) ; LOAD CURRENT POSITION INTO HL @@ -916,6 +940,7 @@ TMS_FILL: ; TMS_FILL1: LD A,C ; RECOVER CHARACTER TO WRITE + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY DEC DE @@ -941,6 +966,7 @@ TMS_SCROLL0: ; READ LINE THAT IS ONE PAST CURRENT DESTINATION LD DE,TMS_BUF LD B,TMS_COLS TMS_SCROLL1: + EZ80_IO IN A,(TMS_DATREG) TMS_IODELAY LD (DE),A @@ -954,6 +980,7 @@ TMS_SCROLL1: LD B,TMS_COLS TMS_SCROLL2: LD A,(DE) + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY INC DE @@ -970,6 +997,7 @@ TMS_SCROLL2: LD A,' ' LD B,TMS_COLS TMS_SCROLL3: + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY DJNZ TMS_SCROLL3 @@ -994,6 +1022,7 @@ TMS_RSCROLL0: ; READ THE LINE THAT IS ONE PRIOR TO CURRENT DESTINATION LD DE,TMS_BUF ; POINT TO BUFFER LD B,TMS_COLS ; LOOP FOR EACH COLUMN TMS_RSCROLL1: + EZ80_IO IN A,(TMS_DATREG) ; GET THE CHAR TMS_IODELAY ; RECOVER LD (DE),A ; SAVE IN BUFFER @@ -1007,6 +1036,7 @@ TMS_RSCROLL1: LD B,TMS_COLS ; INIT LOOP COUNTER TMS_RSCROLL2: LD A,(DE) ; LOAD THE CHAR + EZ80_IO OUT (TMS_DATREG),A ; WRITE TO SCREEN TMS_IODELAY ; DELAY INC DE ; BUMP BUF POINTER @@ -1023,6 +1053,7 @@ TMS_RSCROLL2: LD A,' ' LD B,TMS_COLS TMS_RSCROLL3: + EZ80_IO OUT (TMS_DATREG),A TMS_IODELAY DJNZ TMS_RSCROLL3 @@ -1044,6 +1075,7 @@ TMS_BLKCPY1: LD DE,TMS_BUF ; POINT TO BUFFER LD B,C TMS_BLKCPY2: + EZ80_IO IN A,(TMS_DATREG) ; GET THE NEXT BYTE TMS_IODELAY ; DELAY LD (DE),A ; SAVE IN BUFFER @@ -1058,6 +1090,7 @@ TMS_BLKCPY2: LD B,C TMS_BLKCPY3: LD A,(DE) ; GET THE CHAR FROM BUFFER + EZ80_IO OUT (TMS_DATREG),A ; WRITE TO VDU TMS_IODELAY ; DELAY INC DE ; BUMP BUF PTR @@ -1100,7 +1133,7 @@ TMS_Z180IOX: #IF (TMSTIMENABLE & (INTMODE > 0)) TMS_TSTINT: - IN A,(TMS_CMDREG) ; TEST FOR INT FLAG + IN_A_NN(TMS_CMDREG) AND $80 JR NZ,TMS_INTHNDL AND $00 ; RETURN Z - NOT HANDLED @@ -1217,7 +1250,11 @@ TMS_INITVDU_REG_1: .DB $00 ; REG 6 - NO SPRITE GENERATOR TABLE .DB $F0 ; REG 7 - WHITE ON BLACK .DB $88 ; REG 8 - COLOUR BUS INPUT, DRAM 64K +#IF (TICKFREQ == 50) + .DB $02 ; REG 9 +#ELSE .DB $00 ; REG 9 +#ENDIF .DB $00 ; REG 10 - COLOUR TABLE A14-A16 (TMS_FNTVADDR - $1000) ; #ELSE ; _______TMS9918 REGISTER SET_______ diff --git a/Source/Makefile b/Source/Makefile index 9b060384..e741cc4c 100644 --- a/Source/Makefile +++ b/Source/Makefile @@ -5,7 +5,7 @@ .PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 .ONESHELL: -.SHELLFLAGS = -cex +.SHELLFLAGS = -ce all: prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 @@ -40,7 +40,7 @@ images: $(MAKE) --directory Images $(ACTION) rom: - $(MAKE) --directory HBIOS $(ACTION) + @$(MAKE) --directory HBIOS $(ACTION) zrc: $(MAKE) --directory ZRC $(ACTION) diff --git a/Source/RomDsk/Makefile b/Source/RomDsk/Makefile index 1f067db1..57e5ff7c 100644 --- a/Source/RomDsk/Makefile +++ b/Source/RomDsk/Makefile @@ -7,7 +7,7 @@ include $(TOOLS)/Makefile.inc .SHELLFLAGS = -ce ROMAPPS1 := assign mode rtc syscopy xm -ROMAPPS2 := fdu format survey sysgen talk timer cpuspd +ROMAPPS2 := fdu format survey sysgen talk cpuspd rom128_%.dat: DISKDEF=wbw_rom128 rom256_%.dat: DISKDEF=wbw_rom256 diff --git a/Tools/Makefile b/Tools/Makefile index 74baac9a..a4bbdb71 100644 --- a/Tools/Makefile +++ b/Tools/Makefile @@ -3,7 +3,7 @@ # .ONESHELL: -.SHELLFLAGS = -cex +.SHELLFLAGS = -ce UNAME := $(shell uname) diff --git a/Tools/Makefile.inc b/Tools/Makefile.inc index 10be67c5..a541305c 100644 --- a/Tools/Makefile.inc +++ b/Tools/Makefile.inc @@ -56,7 +56,7 @@ CPM=$(TOOLS)/cpm/bin80/ # exit if any command returns a non-zero result ("x"). # .ONESHELL: -.SHELLFLAGS = -cex +.SHELLFLAGS = -ce %.com: %.asm @if [ "$(USETASM)" = 1 ] ; then \ @@ -70,52 +70,52 @@ CPM=$(TOOLS)/cpm/bin80/ fi %.rom: %.asm - $(TASM) $(TASMFLAGS) $< $@ $*.lst + @$(TASM) $(TASMFLAGS) $< $@ $*.lst %.hex: %.asm - $(ZXCC) $(CPM)/MAC -$< -$$PO + @$(ZXCC) $(CPM)/MAC -$< -$$PO %.bin: %.ASM - $(ZXCC) $(CPM)/MAC -$< -$$PO + @$(ZXCC) $(CPM)/MAC -$< -$$PO $(ZXCC) $(CPM)/MLOAD25 -tmp.bin=$*.hex mv tmp.bin $@ rm -f /tmp/casefn.cache rm -f $$($(CASEFN) $*.hex) %.com: %.z80 - $(ZXCC) $(CPM)/Z80ASM -$(basename $<)/F + @$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/F rm -f /tmp/casefn.cache mv $$($(CASEFN) $@) tmp.com ; mv tmp.com $@ %.bin: %.asm - $(TASM) $(TASMFLAGS) $< $@ $(basename $<).lst + @$(TASM) $(TASMFLAGS) $< $@ $(basename $<).lst %.rel: %.asm - $(ZXCC) $(CPM)/RMAC -$< + @$(ZXCC) $(CPM)/RMAC -$< %.rel: %.z80 - $(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF + @$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF #%.hex: %.z80 -# $(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF +# @$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF %.hex: %.z80 - $(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF + @$(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF %.rel: %.azm - $(ZXCC) $(CPM)/ZSM =$< -/L + @$(ZXCC) $(CPM)/ZSM =$< -/L %.bin: %.rel - $(ZXCC) $(CPM)/LINK -$@=$< + @$(ZXCC) $(CPM)/LINK -$@=$< %.rel: %.mac - $(ZXCC) $(CPM)/M80 -=$(basename $<) + @$(ZXCC) $(CPM)/M80 -=$(basename $<) %.com: %.rel - $(ZXCC) $(CPM)/L80 -$(basename $<),$(basename $<).com/n/e + @$(ZXCC) $(CPM)/L80 -$(basename $<),$(basename $<).com/n/e %.eeprom: %.spin - $(OPENSPIN) -e $< + @$(OPENSPIN) -e $< # # first target is default diff --git a/Tools/unix/Makefile b/Tools/unix/Makefile index ebdecfb5..7cefdb27 100644 --- a/Tools/unix/Makefile +++ b/Tools/unix/Makefile @@ -3,7 +3,7 @@ # .ONESHELL: -.SHELLFLAGS = -cex +.SHELLFLAGS = -ce UNAME := $(shell uname) ifeq ($(UNAME), Linux) @@ -20,4 +20,4 @@ all: @$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) all;) clean: - @$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) clean;) \ No newline at end of file + @$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) clean;)