From 76cb52eb1436cf1b1033444787c9c1c110233de8 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 1 Jun 2024 13:20:43 +1000
Subject: [PATCH 01/62] Adding new target/config for eZ80 RC2014 builds

---
 Dockerfile                         |  34 +++
 Source/HBIOS/Config/RCEZ80_std.asm |  67 ++++++
 Source/HBIOS/cfg_rcez80.asm        | 338 +++++++++++++++++++++++++++++
 3 files changed, 439 insertions(+)
 create mode 100644 Dockerfile
 create mode 100644 Source/HBIOS/Config/RCEZ80_std.asm
 create mode 100644 Source/HBIOS/cfg_rcez80.asm

diff --git a/Dockerfile b/Dockerfile
new file mode 100644
index 00000000..52b07835
--- /dev/null
+++ b/Dockerfile
@@ -0,0 +1,34 @@
+FROM ubuntu:jammy-20240111 as basebuilder
+
+# docker build --progress plain -t vipoo/romwbw .
+
+# docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it vipoo/romwbw:latest
+
+# cd Source && make ROM_PLATFORM=RCZ80 ROM_CONFIG=std
+LABEL Maintainer="Dean Netherton" \
+      Description="spike to use clang for ez80 target"
+
+ENV DEBIAN_FRONTEND=noninteractive
+
+
+RUN dpkg --add-architecture i386
+RUN sed -i 's/http:\/\/archive\.ubuntu\.com\/ubuntu/http:\/\/au.archive.ubuntu.com\/ubuntu/g' /etc/apt/sources.list
+RUN apt update -y
+RUN apt dist-upgrade -y
+RUN apt install -y --no-install-recommends cmake lzip ca-certificates mtools build-essential dos2unix libboost-all-dev texinfo texi2html libxml2-dev subversion bison flex zlib1g-dev m4 git wget dosfstools curl
+
+RUN mkdir work
+WORKDIR /work
+
+FROM basebuilder as main
+
+LABEL Maintainer="Dean Netherton" \
+      Description="spike to build RomWBW"
+
+RUN mkdir /src
+WORKDIR /src/
+
+RUN apt install -y --no-install-recommends build-essential libncurses-dev srecord bsdmainutils
+
+RUN adduser --disabled-password --gecos "" builder
+
diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
new file mode 100644
index 00000000..923c2b32
--- /dev/null
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -0,0 +1,67 @@
+;
+;==================================================================================================
+;   RCBUS Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcez80.asm"
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
new file mode 100644
index 00000000..2e7c2c91
--- /dev/null
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -0,0 +1,338 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80|]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
+UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

From 8b63b32580581de2eaea73c4eab97945059ef166 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 1 Jun 2024 13:23:38 +1000
Subject: [PATCH 02/62] gitignored some more untracked generated files

---
 .gitignore                    | 140 +++++++++++++++++++++++++++++++++-
 .vscode/settings.json         |   4 +
 Dockerfile                    |   4 +-
 Source/HBIOS/cfg_duo.asm      |   4 +-
 Source/HBIOS/cfg_dyno.asm     |   4 +-
 Source/HBIOS/cfg_epitx.asm    |   4 +-
 Source/HBIOS/cfg_heath.asm    |   4 +-
 Source/HBIOS/cfg_master.asm   |   4 +-
 Source/HBIOS/cfg_mbc.asm      |   4 +-
 Source/HBIOS/cfg_mk4.asm      |   4 +-
 Source/HBIOS/cfg_mon.asm      |   4 +-
 Source/HBIOS/cfg_n8.asm       |   4 +-
 Source/HBIOS/cfg_nabu.asm     |   4 +-
 Source/HBIOS/cfg_rcez80.asm   |   4 +-
 Source/HBIOS/cfg_rcz180.asm   |   4 +-
 Source/HBIOS/cfg_rcz280.asm   |   4 +-
 Source/HBIOS/cfg_rcz80.asm    |   4 +-
 Source/HBIOS/cfg_rph.asm      |   4 +-
 Source/HBIOS/cfg_s100.asm     |   4 +-
 Source/HBIOS/cfg_sbc.asm      |   4 +-
 Source/HBIOS/cfg_scz180.asm   |   4 +-
 Source/HBIOS/cfg_una.asm      |   4 +-
 Source/HBIOS/cfg_z80retro.asm |   4 +-
 Source/HBIOS/cfg_zeta.asm     |   4 +-
 Source/HBIOS/cfg_zeta2.asm    |   4 +-
 25 files changed, 190 insertions(+), 46 deletions(-)
 create mode 100644 .vscode/settings.json

diff --git a/.gitignore b/.gitignore
index d33e8d5a..7ad6b419 100644
--- a/.gitignore
+++ b/.gitignore
@@ -109,4 +109,142 @@ Source/ZPM3/zccp.com
 Source/ZPM3/zpmldr.com
 Source/ZPM3/genbnk.dat
 
-Source/ZSDOS/zsdos.err
\ No newline at end of file
+Source/ZSDOS/zsdos.err
+
+# Lets explicit list all generate untracked binary files
+Binary/Apps/Tunes/bgm.vgm
+Binary/Apps/Tunes/ending.vgm
+Binary/Apps/Tunes/inchina.vgm
+Binary/Apps/Tunes/shirakaw.vgm
+Binary/Apps/Tunes/startdem.vgm
+Binary/Apps/Tunes/wonder01.vgm
+Binary/Apps/fdu.doc
+Binary/Apps/zmconfig.ovr
+Binary/Apps/zminit.ovr
+Binary/Apps/zmp.doc
+Binary/Apps/zmp.hlp
+Binary/Apps/zmterm.ovr
+Binary/Apps/zmxfer.ovr
+Binary/CPM3/bdos3.spr
+Binary/CPM3/bios3.spr
+Binary/CPM3/bnkbdos3.spr
+Binary/CPM3/bnkbios3.spr
+Binary/CPM3/cpm3fix.pat
+Binary/CPM3/genbnk.dat
+Binary/CPM3/gencpm.dat
+Binary/CPM3/genres.dat
+Binary/CPM3/readme.1st
+Binary/CPM3/resbdos3.spr
+Binary/CPNET/cpn12duo.lbr
+Binary/CPNET/cpn12mt.lbr
+Binary/CPNET/cpn12ser.lbr
+Binary/CPNET/cpn3duo.lbr
+Binary/CPNET/cpn3mt.lbr
+Binary/CPNET/cpn3ser.lbr
+Binary/RCEZ80_std.upd
+Binary/RCZ80_std.upd
+Binary/ZPM3/bnkbdos3.spr
+Binary/ZPM3/bnkbios3.spr
+Binary/ZPM3/gencpm.dat
+Binary/ZPM3/resbdos3.spr
+Binary/ZPM3/zinstal.zpm
+Binary/hd1k_prefix.dat
+Source/BPBIOS/def-ww.lib
+Source/CPNET/cpn12duo.lbr
+Source/CPNET/cpn12mt.lbr
+Source/CPNET/cpn12ser.lbr
+Source/CPNET/cpn3duo.lbr
+Source/CPNET/cpn3mt.lbr
+Source/CPNET/cpn3ser.lbr
+Source/Fonts/font8x11c.asm
+Source/Fonts/font8x11c.bin
+Source/Fonts/font8x11u.asm
+Source/Fonts/font8x16c.asm
+Source/Fonts/font8x16c.bin
+Source/Fonts/font8x16u.asm
+Source/Fonts/font8x8c.asm
+Source/Fonts/font8x8c.bin
+Source/Fonts/font8x8u.asm
+Source/Fonts/fontcgac.asm
+Source/Fonts/fontcgac.bin
+Source/Fonts/fontcgau.asm
+Source/Fonts/fontvgarcc.asm
+Source/Fonts/fontvgarcc.bin
+Source/Fonts/fontvgarcu.asm
+Source/HBIOS/RCEZ80_std.upd
+Source/HBIOS/RCZ80_std.upd
+Source/HBIOS/build_env.cmd
+Source/HBIOS/hbios_env.sh
+Source/Images/blank144
+Source/Images/blankhd1k
+Source/Images/blankhd512
+Source/Images/fd144_aztecc.img
+Source/Images/fd144_bascomp.img
+Source/Images/fd144_cowgol.img
+Source/Images/fd144_cpm22.img
+Source/Images/fd144_cpm3.img
+Source/Images/fd144_fortran.img
+Source/Images/fd144_games.img
+Source/Images/fd144_hitechc.img
+Source/Images/fd144_nzcom.img
+Source/Images/fd144_qpm.img
+Source/Images/fd144_tpascal.img
+Source/Images/fd144_ws4.img
+Source/Images/fd144_z80asm.img
+Source/Images/fd144_zpm3.img
+Source/Images/fd144_zsdos.img
+Source/Images/hd1k_aztecc.img
+Source/Images/hd1k_bascomp.img
+Source/Images/hd1k_blank.img
+Source/Images/hd1k_bp.img
+Source/Images/hd1k_combo.img
+Source/Images/hd1k_cowgol.img
+Source/Images/hd1k_cpm22.img
+Source/Images/hd1k_cpm3.img
+Source/Images/hd1k_fortran.img
+Source/Images/hd1k_games.img
+Source/Images/hd1k_hitechc.img
+Source/Images/hd1k_nzcom.img
+Source/Images/hd1k_qpm.img
+Source/Images/hd1k_tpascal.img
+Source/Images/hd1k_ws4.img
+Source/Images/hd1k_z80asm.img
+Source/Images/hd1k_zpm3.img
+Source/Images/hd1k_zsdos.img
+Source/Images/hd512_aztecc.img
+Source/Images/hd512_bascomp.img
+Source/Images/hd512_blank.img
+Source/Images/hd512_combo.img
+Source/Images/hd512_cowgol.img
+Source/Images/hd512_cpm22.img
+Source/Images/hd512_cpm3.img
+Source/Images/hd512_dos65.img
+Source/Images/hd512_fortran.img
+Source/Images/hd512_games.img
+Source/Images/hd512_hitechc.img
+Source/Images/hd512_nzcom.img
+Source/Images/hd512_qpm.img
+Source/Images/hd512_tpascal.img
+Source/Images/hd512_ws4.img
+Source/Images/hd512_z80asm.img
+Source/Images/hd512_zpm3.img
+Source/Images/hd512_zsdos.img
+Source/RomDsk/rom0_una.dat
+Source/RomDsk/rom0_wbw.dat
+Source/RomDsk/rom128_una.dat
+Source/RomDsk/rom128_wbw.dat
+Source/RomDsk/rom256_una.dat
+Source/RomDsk/rom256_wbw.dat
+Source/RomDsk/rom384_una.dat
+Source/RomDsk/rom384_wbw.dat
+Source/RomDsk/rom896_una.dat
+Source/RomDsk/rom896_wbw.dat
+Source/ZCPR-DJ/zcprdemo.com
+Source/ZPM3/autotog.com
+Source/ZPM3/clrhist.com
+Source/ZPM3/cpmldr.com
+Source/ZPM3/setz3.com
+Tools/unix/OpenSpin/build/
+Tools/unix/zxcc/config.h
+Tools/unix/zxcc/zxcc
+Binary/Apps/bbcbasic.txt
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 00000000..7c12e6b0
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,4 @@
+{
+  "files.trimTrailingWhitespace": false,
+  "files.eol": "\r\n"
+}
diff --git a/Dockerfile b/Dockerfile
index 52b07835..770c6ceb 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -4,7 +4,9 @@ FROM ubuntu:jammy-20240111 as basebuilder
 
 # docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it vipoo/romwbw:latest
 
-# cd Source && make ROM_PLATFORM=RCZ80 ROM_CONFIG=std
+# cd Tools && make
+# cd Source && make rom ROM_PLATFORM=RCEZ80 ROM_CONFIG=std
+
 LABEL Maintainer="Dean Netherton" \
       Description="spike to use clang for ez80 target"
 
diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm
index 4843f81b..979f32ae 100644
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index dd3f3c05..b37b2222 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm
index 4002c7d1..8bdd7d04 100644
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm
index 41f6cb6a..2ef14948 100644
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index e10cda1d..52be3841 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -12,8 +12,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm
index bc37a51f..0f12e79e 100644
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 691440e6..b8464158 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm
index 00f7b408..cfc28dcc 100644
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index d810827d..a4979601 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm
index 538bc8e1..754bce99 100644
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 2e7c2c91..aa3a6cbe 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80|]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index d1f2da99..b229fbb0 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index f97f7033..8d9da62b 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 7224ff1d..ba3ae249 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rph.asm b/Source/HBIOS/cfg_rph.asm
index fbf1ebbf..2ecbb855 100644
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm
index 70800cf8..14e2225a 100644
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 76cd046b..6da370f0 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 52849489..018029b9 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_una.asm b/Source/HBIOS/cfg_una.asm
index ca57b1f3..94fb6e51 100644
--- a/Source/HBIOS/cfg_una.asm
+++ b/Source/HBIOS/cfg_una.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
 FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm
index e95c80ae..8fb1c216 100644
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 0b3c409f..0a213bb3 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 7e3c6f10..00900b97 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -15,8 +15,8 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)

From a92aebddd7c439453d27a0bb74674729cb29b907 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 1 Jun 2024 15:03:27 +1000
Subject: [PATCH 03/62] eZ80: hbios i/o operations updated for FPLED_IO and ram
 bank initialisation

---
 Source/HBIOS/cfg_rcez80.asm |  1 +
 Source/HBIOS/hbios.asm      | 55 +++++++++++++++++++++++++++++++++----
 Source/HBIOS/std.asm        |  1 +
 3 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index aa3a6cbe..629de8cb 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -17,6 +17,7 @@
 ;
 PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+EZ80IOBASE	.EQU	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 99920627..b588ae73 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1397,7 +1397,12 @@ BOOTWAIT:
 ;
 	;LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
 	LD	A,RTCDEF		; DEFAULT VALUE
+#IF (CPUFAM == CPU_EZ80)
+	LD	BC,EZ80IOBASE << 8 + RTCIO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+#ELSE
 	OUT	(RTCIO),A		; SET IT
+#ENDIF
 ;
 #IF (PLATFORM == PLT_N8)
 	LD	A,N8_DEFACR		; ENSURE N8 ACR
@@ -1421,9 +1426,16 @@ BOOTWAIT:
 	LD	A,DIAG_01
   #ENDIF
 ;
+#IF (CPUFAM == CPU_EZ80)
+	LD	BC,EZ80IOBASE << 8 + FPLED_IO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+#ELSE
 	OUT	(FPLED_IO),A
 #ENDIF
+
+#ENDIF
 ;
+
 #IF (LEDENABLE)
   #IF ((LEDMODE == LEDMODE_STD) | (LEDMODE == LEDMODE_SC))
 	XOR	A			; LED IS INVERTED, TURN IT ON
@@ -1688,28 +1700,49 @@ ROMRESUME:
 ;
 #IF (MEMMGR == MM_Z2)
 ;
-  #IFDEF ROMBOOT
+  #IF (CPUFAM == CPU_EZ80)
+	XOR	A
+	LD	BC,EZ80IOBASE << 8 + MPGSEL_0
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+	INC	A
+	INC	BC			; BC = MPGSEL_1
+	OUT	(C),A			; OUT (MPGSEL_1), $01
+
+	LD	A,64 - 2
+	INC	BC			; BC = MPGSEL_2
+	OUT	(C),A			; PROG THIRD 16K MMU REGISTER
+	INC	A
+	INC	BC			; BC = MPGSEL_3
+	OUT	(C),A			; PROG FOURTH 16K MMU REGISTER
+	; ENABLE PAGING
+	LD	A,1
+	INC	BC			; BC =  MPGENA
+	OUT	(C),A			; ENABLE MMU NOW
+
+  #ELSE
+    #IFDEF ROMBOOT
 	; IF THIS IS A ROM BOOT, SETUP THE FIRST 2 16K MMU REGISTERS
 	; TO MAP THE LOWEST 32K OF PHYSICAL ROM TO THE LOW 32K OF
 	; CPU ADDRESS SPACE (BANKING AREA).  THE FIRST 16K MAPPING IS
 	; REDUNDANT BECAUSE WE ARE ALREADY RUNNING IN THIS AREA.  THE
 	; MAPPING OF THE SECOND 16K IS CRITICAL BECAUSE ALL ZETA 2
 	; MMU REGISTERS WILL BE 0 AT RESET!
+
 	XOR	A
 	OUT	(MPGSEL_0),A		; PROG FIRST 16K MMU REGISTER
 	INC	A
 	OUT	(MPGSEL_1),A		; PROG SECOND 16K MMU REGISTER
-  #ENDIF
-;
-  #IF (PLATFORM == PLT_DUO)
+    #ENDIF
+; 
+    #IF (PLATFORM == PLT_DUO)
 	; DUO HAS VARIABLE RAM SIZE.  RAM ALWAYS STARTS AT 2048K.
 	; SETUP COMMON RAM FOR HIGHEST 32K OF RAM BASED ON TOTAL RAM.
 	LD	A,128 + (RAMSIZE / 16) - 2
-  #ELSE
+    #ELSE
 	; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM.  SETUP COMMON
 	; FOR TOP 32K OF THIS.
 	LD	A,64 - 2
-  #ENDIF
+    #ENDIF
 ;
 	OUT	(MPGSEL_2),A		; PROG THIRD 16K MMU REGISTER
 	INC	A
@@ -1717,7 +1750,9 @@ ROMRESUME:
 	; ENABLE PAGING
 	LD	A,1
 	OUT	(MPGENA),A		; ENABLE MMU NOW
+  #ENDIF
 #ENDIF
+
 ;
 ;--------------------------------------------------------------------------------------------------
 ; PROXY INSTALLATION
@@ -7117,7 +7152,15 @@ FP_SETLEDS:
   #IF (FPLED_INV)
 	XOR	$FF			; INVERT BITS IF NEEDED
   #ENDIF
+
+  #IF (CPUFAM == CPU_EZ80)
+	PUSH	BC
+	LD	BC,EZ80IOBASE << 8 + FPLED_IO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+	POP	BC
+  #ELSE
 	OUT	(FPLED_IO),A		; WRITE 
+  #ENDIF
 FP_SETLEDS1:
 	POP	HL			; RESTORE HL
 	RET				; DONE
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 9a51e3a3..3a90169d 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -63,6 +63,7 @@ CPU_NONE	.EQU	0		; NO CPU TYPE DEFINED
 CPU_Z80		.EQU	1		; Z80 FAMILY
 CPU_Z180	.EQU	2		; Z180 FAMILY
 CPU_Z280	.EQU	3		; Z280 FAMILY
+CPU_EZ80	.EQU	4		; eZ280 FAMILY
 ;
 ; BIOS MODE
 ;

From 57364bb581795af5728d7c701e930b7a1c3a10e3 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 1 Jun 2024 18:41:32 +1000
Subject: [PATCH 04/62] EZ80: initial skeleton of driver for EZ80 UART

---
 Source/HBIOS/Config/RCEZ80_std.asm | 18 ++++---
 Source/HBIOS/cfg_rcez80.asm        |  5 +-
 Source/HBIOS/ez80uart.asm          | 87 ++++++++++++++++++++++++++++++
 Source/HBIOS/hbios.asm             | 42 +++++++++++++--
 4 files changed, 138 insertions(+), 14 deletions(-)
 create mode 100644 Source/HBIOS/ez80uart.asm

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 923c2b32..f916d410 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -26,19 +26,21 @@
 ;
 #include "cfg_rcez80.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
@@ -54,11 +56,11 @@ AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
-IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 629de8cb..93bcea3c 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -31,7 +31,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
@@ -165,7 +165,8 @@ ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
 ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+EZ80UARTENABLE	.EQU	TRUE		; EZ80UART: ENABLE EZ80 UART SERIAL DRIVER (EZ80UART.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
new file mode 100644
index 00000000..c9239c30
--- /dev/null
+++ b/Source/HBIOS/ez80uart.asm
@@ -0,0 +1,87 @@
+;
+;==================================================================================================
+; eZ80 UART DRIVER (SERIAL PORT)
+;==================================================================================================
+;
+
+UART0_LSR	.EQU	$C5
+UART0_THR       .EQU	$C0
+
+LSR_THRE	.EQU	$20
+
+#DEFINE IN0_A(p)	.DB	$ED,$38,p
+#DEFINE OUT0_A(p)	.DB	$ED,$39,p
+
+; #DEFINE CALLIL(a,b)	.DB	$5B,$CD \	.DW b	\ .DB b
+
+EZUART_PREINIT:
+	LD	E, 'A'
+	CALL	EZUART_OUT
+	LD	E, 'B'
+	CALL	EZUART_OUT
+	LD	E, 'C'
+	CALL	EZUART_OUT
+	LD	E, 'D'
+	CALL	EZUART_OUT
+	LD	E, 13
+	CALL	EZUART_OUT
+	LD	E, 10
+	CALL	EZUART_OUT
+	RET
+
+EZUART_INIT:
+	LD	E, '1'
+	CALL	EZUART_OUT
+	LD	E, '2'
+	CALL	EZUART_OUT
+	LD	E, '3'
+	CALL	EZUART_OUT
+	LD	E, '4'
+	CALL	EZUART_OUT
+	LD	E, 13
+	CALL	EZUART_OUT
+	LD	E, 10
+	CALL	EZUART_OUT
+
+	;call.il, $001000
+	.db	$5B,$CD
+	.dw	$1000
+	.db	$00
+
+	RET
+
+EZUART_IN:
+
+;
+; OUT CHAR IN E
+EZUART_OUT:
+	; WAIT FOR UART TO BE READY FOR TX
+WAIT_FOR_TX_READY:
+	; IN0	A,(UART0_LSR)		; /*ED38C5*/
+	IN0_A	(UART0_LSR)
+	AND	LSR_THRE
+	JR	Z,WAIT_FOR_TX_READY
+     
+	; SEND THE CHAR
+	LD	A, E
+	; OUT0	(UART0_LSR),A		; ED39C0
+	OUT0_A	(UART0_THR)
+	RET
+
+EZUART_IST:
+EZUART_OST:
+EZUART_INITDEV:
+EZUART_QUERY:
+EZUART_DEVICE:
+	RET
+	
+EZUART_FNTBL:
+	.DW	EZUART_IN
+	.DW	EZUART_OUT
+	.DW	EZUART_IST
+	.DW	EZUART_OST
+	.DW	EZUART_INITDEV
+	.DW	EZUART_QUERY
+	.DW	EZUART_DEVICE
+#IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID EZUART FUNCTION TABLE ***\n"
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index b588ae73..160bbb00 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -623,11 +623,20 @@ HBX_ROM:
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
+ #IF (CPU_FAM == CPU_EZ80)
+	PUSH	BC
+	LD	BC,EZ80IOBASE<<8+MPGSEL_0
+	OUT	(C),A			; BANK_0: 0K - 16K
+	INC	A
+	INC	BC			; BC = MPGSEL_0
+	OUT	(C),A			; BANK_1: 16K - 32K
+ #ELSE
 	OUT	(MPGSEL_0),A		; BANK_0: 0K - 16K
 	INC	A			;
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
-  #IF (CPUFAM == CPU_Z280)
+    #IF (CPUFAM == CPU_Z280)
 	PCACHE
+    #ENDIF
   #ENDIF
 	RET				; DONE
 #ENDIF
@@ -1809,7 +1818,7 @@ ROMRESUME:
 ; THEN IT MEANS THE S100 MONITOR IS ATTEMPTING TO REBOOT INTO ROMWBW
 ; HBIOS AND WE ABORT THE TRANSITION TO THE S100 MONITOR.
 ;
-#IF ((PLATFORM == PLT_S100) & TRUE)
+#IF (PLATFORM == PLT_S100)
 	; CHECK S100 BOARD DIP SWITCH, BIT 1
 	IN	A,($75)			; READ SWITCHES
 	BIT	1,A			; CHECK BIT 1
@@ -1843,9 +1852,19 @@ S100MON_SKIP:
 ; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
 ; CREATED.
 ;
+#IF (CPUFAM == CPU_EZ80)
+#DEFINE OUTA(p)	PUSH BC 
+#DEFCONT \ 		LD	BC,EZ80IOBASE << 8 + p
+#DEFCONT \ 		OUT	(C),A 
+#DEFCONT \ 		POP BC
+#ELSE
+#DEFINE OUTA(P) OUT	(RTCIO),A
+#ENDIF
+
+
 	LD	A,(RTCDEFVAL)
 	LD	(HB_RTCVAL),A
-	OUT	(RTCIO),A		; SET IT
+	OUTA(RTCIO)			; SET IT
 	DIAG(1)				; REAPPLY CURRENT DIAG LED SETUP
 ;
 ;--------------------------------------------------------------------------------------------------
@@ -1991,7 +2010,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 ;
 	; NOTIFY THAT WE MADE THE TRANSITION!
 	FPLEDS(DIAG_03)
-	DIAG(2)
+	DIAG(2)	
 ;
 	; RECOVER DATA PASSED PRIOR TO RAM TRANSITION
 	; (HBX_LOC - 1) = BATCOND
@@ -3614,6 +3633,9 @@ HB_PCINITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_PREINIT
 #ENDIF
+#IF (EZ80UARTENABLE)
+	.DW	EZUART_PREINIT
+#ENDIF
 #IF (ACIAENABLE)
 	.DW	ACIA_PREINIT
 #ENDIF
@@ -3692,6 +3714,9 @@ HB_INITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_INIT
 #ENDIF
+#IF (EZ80UARTENABLE)
+	.DW	EZUART_INIT
+#ENDIF
 #IF (ACIAENABLE)
 	.DW	ACIA_INIT
 #ENDIF
@@ -8050,6 +8075,15 @@ SIZ_SIO		.EQU	$ - ORG_SIO
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (EZ80UARTENABLE)
+ORG_EZU	.EQU	$
+  #INCLUDE "ez80uart.asm"
+SIZ_EZU		.EQU	$ - ORG_EZU
+		MEMECHO	"EZ80 UART occupies "
+		MEMECHO	SIZ_EZU
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ACIAENABLE)
 ORG_ACIA	.EQU	$
   #INCLUDE "acia.asm"

From 2bc807edc83f125477be18472d702dff2ccd9598 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 2 Jun 2024 09:34:31 +1000
Subject: [PATCH 05/62] eZ80: uart driver init and pre-init functions defer to
 routines within the eZ80 Flash rom

---
 Source/HBIOS/ez80uart.asm | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index c9239c30..ac4ade80 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -14,6 +14,9 @@ LSR_THRE	.EQU	$20
 
 ; #DEFINE CALLIL(a,b)	.DB	$5B,$CD \	.DW b	\ .DB b
 
+; call.IL $01FFxx WHERE xx IS r*4
+#DEFINE FIRMWARE_FN(r)	.DB	$5B,$CD \	.DW	($FF00+(r*4))	\ .DB $01
+
 EZUART_PREINIT:
 	LD	E, 'A'
 	CALL	EZUART_OUT
@@ -27,6 +30,9 @@ EZUART_PREINIT:
 	CALL	EZUART_OUT
 	LD	E, 10
 	CALL	EZUART_OUT
+
+	FIRMWARE_FN(0)
+
 	RET
 
 EZUART_INIT:
@@ -43,10 +49,11 @@ EZUART_INIT:
 	LD	E, 10
 	CALL	EZUART_OUT
 
-	;call.il, $001000
-	.db	$5B,$CD
-	.dw	$1000
-	.db	$00
+	FIRMWARE_FN(1)
+	; ;call.il, $001000
+	; .db	$5B,$CD
+	; .dw	$FF00
+	; .db	$01
 
 	RET
 

From d358c8bc1ca4796a0c3789eb160e8cdf74e0be3d Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 2 Jun 2024 19:41:35 +1000
Subject: [PATCH 06/62] eZ80: uart and hbios banking code updated to support
 the eZ80 for RC2014 configuration

---
 Source/Doc/SystemGuide.md   |  35 ++++++------
 Source/HBIOS/cfg_rcez80.asm |  21 ++++----
 Source/HBIOS/ez80uart.asm   | 103 +++++++++++++++++++++---------------
 Source/HBIOS/hbios.asm      |  10 +++-
 Source/HBIOS/hbios.inc      |   3 +-
 5 files changed, 100 insertions(+), 72 deletions(-)

diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md
index c9cdb2ea..08766843 100644
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -393,23 +393,24 @@ All character units are assigned a Device Type ID which indicates
 the specific hardware device driver that handles the unit.  The table
 below enumerates these values.
 
-| **Device Type** | **ID** | **Description**                          | **Driver** |
-|-----------------|-------:|------------------------------------------|------------|
-| CIODEV_UART     | 0x00   | 16C550 Family Serial Interface           | uart.asm   |
-| CIODEV_ASCI     | 0x01   | Z180 Built-in Serial Ports               | asci.asm   |
-| CIODEV_TERM     | 0x02   | Terminal                                 | ansi.asm   |
-| CIODEV_PRPCON   | 0x03   | PropIO Serial Console Interface          | prp.asm    |
-| CIODEV_PPPCON   | 0x04   | ParPortProp Serial Console Interface     | ppp.asm    |
-| CIODEV_SIO      | 0x05   | Zilog Serial Port Interface              | sio.asm    |
-| CIODEV_ACIA     | 0x06   | MC68B50 Asynchronous Interface           | acia.asm   |
-| CIODEV_PIO      | 0x07   | Zilog Parallel Interface Controller      | pio.asm    |
-| CIODEV_UF       | 0x08   | FT232H-based ECB USB FIFO                | uf.asm     |
-| CIODEV_DUART    | 0x09   | SCC2681 Family Dual UART                 | duart.asm  |
-| CIODEV_Z2U      | 0x0A   | Zilog Z280 Built-in Serial Ports         | z2u.asm    |
-| CIODEV_LPT      | 0x0B   | Parallel I/O Controller                  | lpt.asm    |
-| CIODEV_ESPCON   | 0x0B   | ESP32 VGA Console                        | esp.asm    |
-| CIODEV_ESPSER   | 0x0B   | ESP32 Serial Port                        | esp.asm    |
-| CIODEV_SCON     | 0x0B   | S100 Console                             | scon.asm   |
+| **Device Type** | **ID** | **Description**                          | **Driver**   |
+|-----------------|-------:|------------------------------------------|--------------|
+| CIODEV_UART     | 0x00   | 16C550 Family Serial Interface           | uart.asm     |
+| CIODEV_ASCI     | 0x01   | Z180 Built-in Serial Ports               | asci.asm     |
+| CIODEV_TERM     | 0x02   | Terminal                                 | ansi.asm     |
+| CIODEV_PRPCON   | 0x03   | PropIO Serial Console Interface          | prp.asm      |
+| CIODEV_PPPCON   | 0x04   | ParPortProp Serial Console Interface     | ppp.asm      |
+| CIODEV_SIO      | 0x05   | Zilog Serial Port Interface              | sio.asm      |
+| CIODEV_ACIA     | 0x06   | MC68B50 Asynchronous Interface           | acia.asm     |
+| CIODEV_PIO      | 0x07   | Zilog Parallel Interface Controller      | pio.asm      |
+| CIODEV_UF       | 0x08   | FT232H-based ECB USB FIFO                | uf.asm       |
+| CIODEV_DUART    | 0x09   | SCC2681 Family Dual UART                 | duart.asm    |
+| CIODEV_Z2U      | 0x0A   | Zilog Z280 Built-in Serial Ports         | z2u.asm      |
+| CIODEV_LPT      | 0x0B   | Parallel I/O Controller                  | lpt.asm      |
+| CIODEV_ESPCON   | 0x0B   | ESP32 VGA Console                        | esp.asm      |
+| CIODEV_ESPSER   | 0x0B   | ESP32 Serial Port                        | esp.asm      |
+| CIODEV_SCON     | 0x0B   | S100 Console                             | scon.asm     |
+| CIODEV_EZ80UART | 0x10   | eZ80 Built-in UART0 Interface            | ez80uart.asm | 
 
 Character devices can usually be configured with line characteristics
 such as speed, framing, etc. A word value (16 bit) is used to describe
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 93bcea3c..26ea9cb7 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -30,7 +30,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
@@ -49,7 +49,7 @@ RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
@@ -107,7 +107,7 @@ PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
@@ -136,7 +136,7 @@ DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
 DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
@@ -146,14 +146,14 @@ UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
 UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
 UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
 UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
 UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
 Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
 ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
 ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
@@ -166,6 +166,7 @@ ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 EZ80UARTENABLE	.EQU	TRUE		; EZ80UART: ENABLE EZ80 UART SERIAL DRIVER (EZ80UART.ASM)
+;
 SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
@@ -203,7 +204,7 @@ EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDTRACE		.EQU	2		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -259,7 +260,7 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -272,9 +273,9 @@ CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
 PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index ac4ade80..bcc72965 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -5,82 +5,101 @@
 ;
 
 UART0_LSR	.EQU	$C5
-UART0_THR       .EQU	$C0
+UART0_THR	.EQU	$C0
+UART0_RBR	.EQU	$C0
 
 LSR_THRE	.EQU	$20
+LSR_DR		.EQU	$01
 
 #DEFINE IN0_A(p)	.DB	$ED,$38,p
-#DEFINE OUT0_A(p)	.DB	$ED,$39,p
+#DEFINE IN0_B(p)	.DB	$ED,$00,p
+#DEFINE IN0_C(p)	.DB	$ED,$08,p
+#DEFINE IN0_D(p)	.DB	$ED,$10,p
+#DEFINE IN0_E(p)	.DB	$ED,$18,p
+#DEFINE IN0_H(p)	.DB	$ED,$20,p
+#DEFINE IN0_L(p)	.DB	$ED,$28,p
 
-; #DEFINE CALLIL(a,b)	.DB	$5B,$CD \	.DW b	\ .DB b
+#DEFINE OUT0_A(p)	.DB	$ED,$39,p
+#DEFINE OUT0_B(p)	.DB	$ED,$01,p
+#DEFINE OUT0_C(p)	.DB	$ED,$09,p
+#DEFINE OUT0_D(p)	.DB	$ED,$11,p
+#DEFINE OUT0_E(p)	.DB	$ED,$19,p
+#DEFINE OUT0_H(p)	.DB	$ED,$21,p
+#DEFINE OUT0_L(p)	.DB	$ED,$29,p
 
 ; call.IL $01FFxx WHERE xx IS r*4
 #DEFINE FIRMWARE_FN(r)	.DB	$5B,$CD \	.DW	($FF00+(r*4))	\ .DB $01
 
 EZUART_PREINIT:
-	LD	E, 'A'
-	CALL	EZUART_OUT
-	LD	E, 'B'
-	CALL	EZUART_OUT
-	LD	E, 'C'
-	CALL	EZUART_OUT
-	LD	E, 'D'
-	CALL	EZUART_OUT
-	LD	E, 13
-	CALL	EZUART_OUT
-	LD	E, 10
-	CALL	EZUART_OUT
+	FIRMWARE_FN(0)
+	LD	BC, EZUART_FNTBL
+	LD	DE, EZUART_CFG		
+	CALL	CIO_ADDENT
+	LD	(EZUART_ID), A
 
 	FIRMWARE_FN(0)
 
+	XOR	A
 	RET
 
 EZUART_INIT:
-	LD	E, '1'
-	CALL	EZUART_OUT
-	LD	E, '2'
-	CALL	EZUART_OUT
-	LD	E, '3'
-	CALL	EZUART_OUT
-	LD	E, '4'
-	CALL	EZUART_OUT
-	LD	E, 13
-	CALL	EZUART_OUT
-	LD	E, 10
-	CALL	EZUART_OUT
-
 	FIRMWARE_FN(1)
-	; ;call.il, $001000
-	; .db	$5B,$CD
-	; .dw	$FF00
-	; .db	$01
 
+	XOR	A
 	RET
 
+
+; RETRIEVE THE NEXT CHARACTER FROM THE UART AND RETURN IN E
 EZUART_IN:
+	IN0_A	(UART0_LSR)		; CHECK FOR RX READY
+	AND	LSR_DR
+	JR	Z, EZUART_IN
+	
+	IN0_E	(UART0_RBR)		; GET THE CHAR
 
-;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+	
 ; OUT CHAR IN E
 EZUART_OUT:
-	; WAIT FOR UART TO BE READY FOR TX
-WAIT_FOR_TX_READY:
-	; IN0	A,(UART0_LSR)		; /*ED38C5*/
-	IN0_A	(UART0_LSR)
+	IN0_A	(UART0_LSR)		; WAIT FOR TX READY
 	AND	LSR_THRE
-	JR	Z,WAIT_FOR_TX_READY
+	JR	Z, EZUART_OUT
      
-	; SEND THE CHAR
-	LD	A, E
-	; OUT0	(UART0_LSR),A		; ED39C0
-	OUT0_A	(UART0_THR)
+	OUT0_E	(UART0_THR)		; SEND THE CHAR
+
+	XOR	A			; SIGNAL SUCCESS
 	RET
 
 EZUART_IST:
+	IN0_A	(UART0_LSR)		; CHECK FOR RX READY
+	AND	LSR_DR
+	RET
+
 EZUART_OST:
+	IN0_A	(UART0_LSR)		; WAIT FOR TX READY
+	AND	LSR_THRE
+	RET	Z
+	LD	A, 1
+	RET
+
 EZUART_INITDEV:
 EZUART_QUERY:
+	LD	A, 0			; NOT IMPLEMENTED ERROR
+	RET
+
 EZUART_DEVICE:
+	LD	D, CIODEV_EZ80UART	; D := DEVICE TYPE
+	LD	E, (IY)			; E := PHYSICAL UNIT
+	LD	C, 0			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	HL, 0			; H := MODE, L := BASE I/O ADDRESS
+	
+	XOR	A			; SIGNAL SUCCESS
 	RET
+
+EZUART_CFG:
+EZUART_ID:	.DB	0
+
 	
 EZUART_FNTBL:
 	.DW	EZUART_IN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 160bbb00..2d570e42 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -623,13 +623,14 @@ HBX_ROM:
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
- #IF (CPU_FAM == CPU_EZ80)
-	PUSH	BC
+ #IF (CPUFAM == CPU_EZ80)
+	EXX
 	LD	BC,EZ80IOBASE<<8+MPGSEL_0
 	OUT	(C),A			; BANK_0: 0K - 16K
 	INC	A
 	INC	BC			; BC = MPGSEL_0
 	OUT	(C),A			; BANK_1: 16K - 32K
+	EXX
  #ELSE
 	OUT	(MPGSEL_0),A		; BANK_0: 0K - 16K
 	INC	A			;
@@ -2191,6 +2192,10 @@ HB_CLRIVT_Z:
 	LD	L,4		; WE ARE Z280
 ;
 #ENDIF
+
+#IF (CPUFAM == CPU_EZ80)
+	LD	L,5
+#ENDIF
 ;
 HB_CPU1:
 	LD	A,L
@@ -7800,6 +7805,7 @@ HB_CPU_STR:	.TEXT	" Z80$"
 		.TEXT	" Z8S180-K$"
 		.TEXT	" Z8S180-N$"
 		.TEXT	" Z80280$"
+		.TEXT   " eZ80$"
 ;
 PS_STRNUL	.TEXT	"--$"		; DISPLAY STRING FOR NUL VALUE
 ;
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index ce3f1924..05219ae1 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -187,7 +187,7 @@ DIAG_7SEG	.EQU	4		; 7-SEGMENT
 DIAG_FLASH	.EQU	5		; FLASH
 DIAG_TRIG	.EQU	6		; TRIGGER
 ;
-DIAG_DISP	.EQU	DIAG_PROG	; DEFAULT
+DIAG_DISP	.EQU	DIAG_BINARY	; DEFAULT
 ;
 #IF (DIAG_DISP == DIAG_PROG)
 DIAG_00 .EQU 00000000B	
@@ -323,6 +323,7 @@ CIODEV_ESPCON	.EQU	$0C
 CIODEV_ESPSER	.EQU	$0D
 CIODEV_SCON	.EQU	$0E
 CIODEV_EF	.EQU	$0F
+CIODEV_EZ80UART	.EQU	$10
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;

From 7e2b054fc1ad030f1ceaee466e6955b2c6cd2504 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 3 Jun 2024 20:46:16 +1000
Subject: [PATCH 07/62] eZ80: added platform config PLT_RCEZ80

---
 Source/Doc/SystemGuide.md   | 1 +
 Source/HBIOS/cfg_rcez80.asm | 2 +-
 Source/HBIOS/hbios.inc      | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md
index 08766843..a2b6089e 100644
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -1963,6 +1963,7 @@ The hardware Platform (L) is identified as follows:
 | PLT_MK4       |5       | MARK IV                                 |
 | PLT_UNA       |6       | UNA BIOS                                |
 | PLT_RCZ80     |7       | RCBUS W/ Z80                            |
+| PLT_RCEZ80    |7       | RCBUS W/ eZ80                           |
 | PLT_RCZ180    |8       | RCBUS W/ Z180                           |
 | PLT_EZZ80     |9       | EASY/TINY Z80                           |
 | PLT_SCZ180    |10      | RCBUS SC126, SC130, SC131, SC140        |
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 26ea9cb7..1304166b 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+PLATFORM	.EQU	PLT_RCEZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 EZ80IOBASE	.EQU	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index 05219ae1..2cabc656 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -158,6 +158,7 @@ PLT_EPITX	.EQU	19		; Z180 MINI-ITX
 PLT_MON		.EQU	20		; MONSPUTER
 PLT_STDZ180	.EQU	21		; GENESIS Z180 SYSTEM
 PLT_NABU	.EQU	22		; NABU PERSONAL COMPUTER
+PLT_RCEZ80	.EQU	23		; RCBUS W/ eZ80
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;

From 46cc57e5fc550e96d5d728d40425e29944d06b8e Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 3 Jun 2024 20:53:18 +1000
Subject: [PATCH 08/62] eZ80: hbios io out operations now managed through a
 expected feature in the eZ80 on-chip rom

---
 Source/HBIOS/hbios.asm | 90 ++++++++++++------------------------------
 1 file changed, 26 insertions(+), 64 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 2d570e42..83fe6cd3 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -351,6 +351,14 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 	DEVECHO	"\n"
 #ENDIF
 ;
+; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
+;
+#IF (CPUFAM == CPU_EZ80)
+  #DEFINE EZ80_IO	.DB $49 $CF
+#ELSE
+  #DEFINE EZ80_IO
+#ENDIF
+;
 ;==================================================================================================
 ; Z80 PAGE ZERO, VECTORS, ETC.
 ;==================================================================================================
@@ -623,21 +631,13 @@ HBX_ROM:
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
- #IF (CPUFAM == CPU_EZ80)
-	EXX
-	LD	BC,EZ80IOBASE<<8+MPGSEL_0
-	OUT	(C),A			; BANK_0: 0K - 16K
-	INC	A
-	INC	BC			; BC = MPGSEL_0
-	OUT	(C),A			; BANK_1: 16K - 32K
-	EXX
- #ELSE
+ 	EZ80_IO()
 	OUT	(MPGSEL_0),A		; BANK_0: 0K - 16K
 	INC	A			;
+	EZ80_IO()
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
-    #IF (CPUFAM == CPU_Z280)
+  #IF (CPUFAM == CPU_Z280)
 	PCACHE
-    #ENDIF
   #ENDIF
 	RET				; DONE
 #ENDIF
@@ -1407,12 +1407,8 @@ BOOTWAIT:
 ;
 	;LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
 	LD	A,RTCDEF		; DEFAULT VALUE
-#IF (CPUFAM == CPU_EZ80)
-	LD	BC,EZ80IOBASE << 8 + RTCIO
-	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
-#ELSE
+	EZ80_IO()
 	OUT	(RTCIO),A		; SET IT
-#ENDIF
 ;
 #IF (PLATFORM == PLT_N8)
 	LD	A,N8_DEFACR		; ENSURE N8 ACR
@@ -1436,12 +1432,8 @@ BOOTWAIT:
 	LD	A,DIAG_01
   #ENDIF
 ;
-#IF (CPUFAM == CPU_EZ80)
-	LD	BC,EZ80IOBASE << 8 + FPLED_IO
-	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
-#ELSE
+	EZ80_IO
 	OUT	(FPLED_IO),A
-#ENDIF
 
 #ENDIF
 ;
@@ -1710,27 +1702,7 @@ ROMRESUME:
 ;
 #IF (MEMMGR == MM_Z2)
 ;
-  #IF (CPUFAM == CPU_EZ80)
-	XOR	A
-	LD	BC,EZ80IOBASE << 8 + MPGSEL_0
-	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
-	INC	A
-	INC	BC			; BC = MPGSEL_1
-	OUT	(C),A			; OUT (MPGSEL_1), $01
-
-	LD	A,64 - 2
-	INC	BC			; BC = MPGSEL_2
-	OUT	(C),A			; PROG THIRD 16K MMU REGISTER
-	INC	A
-	INC	BC			; BC = MPGSEL_3
-	OUT	(C),A			; PROG FOURTH 16K MMU REGISTER
-	; ENABLE PAGING
-	LD	A,1
-	INC	BC			; BC =  MPGENA
-	OUT	(C),A			; ENABLE MMU NOW
-
-  #ELSE
-    #IFDEF ROMBOOT
+  #IFDEF ROMBOOT
 	; IF THIS IS A ROM BOOT, SETUP THE FIRST 2 16K MMU REGISTERS
 	; TO MAP THE LOWEST 32K OF PHYSICAL ROM TO THE LOW 32K OF
 	; CPU ADDRESS SPACE (BANKING AREA).  THE FIRST 16K MAPPING IS
@@ -1739,28 +1711,32 @@ ROMRESUME:
 	; MMU REGISTERS WILL BE 0 AT RESET!
 
 	XOR	A
+	EZ80_IO()
 	OUT	(MPGSEL_0),A		; PROG FIRST 16K MMU REGISTER
 	INC	A
+	EZ80_IO()
 	OUT	(MPGSEL_1),A		; PROG SECOND 16K MMU REGISTER
-    #ENDIF
+  #ENDIF
 ; 
-    #IF (PLATFORM == PLT_DUO)
+  #IF (PLATFORM == PLT_DUO)
 	; DUO HAS VARIABLE RAM SIZE.  RAM ALWAYS STARTS AT 2048K.
 	; SETUP COMMON RAM FOR HIGHEST 32K OF RAM BASED ON TOTAL RAM.
 	LD	A,128 + (RAMSIZE / 16) - 2
-    #ELSE
+  #ELSE
 	; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM.  SETUP COMMON
 	; FOR TOP 32K OF THIS.
 	LD	A,64 - 2
-    #ENDIF
+  #ENDIF
 ;
+	EZ80_IO()
 	OUT	(MPGSEL_2),A		; PROG THIRD 16K MMU REGISTER
 	INC	A
+	EZ80_IO()
 	OUT	(MPGSEL_3),A		; PROG FOURTH 16K MMU REGISTER
 	; ENABLE PAGING
 	LD	A,1
+	EZ80_IO()
 	OUT	(MPGENA),A		; ENABLE MMU NOW
-  #ENDIF
 #ENDIF
 
 ;
@@ -1853,19 +1829,11 @@ S100MON_SKIP:
 ; SEE COMMENTS ABOVE REGARDING THE FUNKY WAY THAT THE RTCDEFVAL IS
 ; CREATED.
 ;
-#IF (CPUFAM == CPU_EZ80)
-#DEFINE OUTA(p)	PUSH BC 
-#DEFCONT \ 		LD	BC,EZ80IOBASE << 8 + p
-#DEFCONT \ 		OUT	(C),A 
-#DEFCONT \ 		POP BC
-#ELSE
-#DEFINE OUTA(P) OUT	(RTCIO),A
-#ENDIF
-
 
 	LD	A,(RTCDEFVAL)
 	LD	(HB_RTCVAL),A
-	OUTA(RTCIO)			; SET IT
+	EZ80_IO()
+	OUT	(RTCIO),A		; SET IT
 	DIAG(1)				; REAPPLY CURRENT DIAG LED SETUP
 ;
 ;--------------------------------------------------------------------------------------------------
@@ -7183,14 +7151,8 @@ FP_SETLEDS:
 	XOR	$FF			; INVERT BITS IF NEEDED
   #ENDIF
 
-  #IF (CPUFAM == CPU_EZ80)
-	PUSH	BC
-	LD	BC,EZ80IOBASE << 8 + FPLED_IO
-	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
-	POP	BC
-  #ELSE
+	EZ80_IO
 	OUT	(FPLED_IO),A		; WRITE 
-  #ENDIF
 FP_SETLEDS1:
 	POP	HL			; RESTORE HL
 	RET				; DONE

From d9e009864bebe03b0076ae5844555c27edbc48c3 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Wed, 5 Jun 2024 17:44:48 +1000
Subject: [PATCH 09/62] eZ80: hbios HBX_BNKSEL_INT is fully implemented in eZ80
 firmware to optimal performance

---
 Source/HBIOS/ez80uart.asm |  8 -------
 Source/HBIOS/hbios.asm    | 46 +++++++++++++++++++++++++++++++++++++--
 2 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index bcc72965..28af82f7 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -27,24 +27,16 @@ LSR_DR		.EQU	$01
 #DEFINE OUT0_H(p)	.DB	$ED,$21,p
 #DEFINE OUT0_L(p)	.DB	$ED,$29,p
 
-; call.IL $01FFxx WHERE xx IS r*4
-#DEFINE FIRMWARE_FN(r)	.DB	$5B,$CD \	.DW	($FF00+(r*4))	\ .DB $01
-
 EZUART_PREINIT:
-	FIRMWARE_FN(0)
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
 	CALL	CIO_ADDENT
 	LD	(EZUART_ID), A
 
-	FIRMWARE_FN(0)
-
 	XOR	A
 	RET
 
 EZUART_INIT:
-	FIRMWARE_FN(1)
-
 	XOR	A
 	RET
 
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 83fe6cd3..9983e7d1 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -354,7 +354,9 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
 ;
 #IF (CPUFAM == CPU_EZ80)
-  #DEFINE EZ80_IO	.DB $49 $CF
+  #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
+  #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
+  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 #ELSE
   #DEFINE EZ80_IO
 #ENDIF
@@ -620,6 +622,12 @@ HBX_ROM:
 #ENDIF
 ;
 #IF (MEMMGR == MM_Z2)
+
+#IF (CPUFAM == CPU_EZ80)
+	EZ80_BNKSEL
+	RET
+#ELSE
+
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
@@ -641,6 +649,7 @@ HBX_ROM:
   #ENDIF
 	RET				; DONE
 #ENDIF
+#ENDIF
 ;
 #IF (MEMMGR == MM_N8)
 	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
@@ -1368,7 +1377,9 @@ HB_START:
 HB_RESTART:
 ;
 	DI				; NO INTERRUPTS
+#IF (CPUFAM != CPU_EZ80)
 	IM	1			; INTERRUPT MODE 1
+#ENDIF
 ;
 #IFDEF APPBOOT
 ;
@@ -1419,6 +1430,33 @@ BOOTWAIT:
 	LD	A,RPH_DEFACR		; ENSURE RPH ACR
 	OUT0	(RPH_ACR),A		; ... REGISTER IS INITIALIZED
 #ENDIF
+
+
+#IF (CPUFAM == CPU_EZ80)
+
+; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
+
+	XOR	A			; FUNCTION CODE TO INIT FIRMWARE
+	LD	HL, PLT_DESCR
+
+	EZ80_FN				; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+	JR	PLT_DESCR_END
+
+PLT_DESCR:
+	.DB	PLT_RCZ80
+	.DB	MEMMGR
+	.DW	RAMSIZE
+	.DW	ROMSIZE
+	.DB	MPGSEL_0
+	.DB	MPGSEL_1
+	.DB	MPGSEL_2
+	.DB	MPGSEL_3
+	.DB	MPGENA
+
+PLT_DESCR_END:
+
+#ENDIF
+
 ;
 ; INITIALIZE DIAGNOSTIC AND/OR FRONT PANEL LED(S) TO INDICATE THE
 ; SYSTEM IS ALIVE. WE HAVE NO RAM AT THIS TIME, SO WE CANNOT USE
@@ -1432,7 +1470,7 @@ BOOTWAIT:
 	LD	A,DIAG_01
   #ENDIF
 ;
-	EZ80_IO
+	EZ80_IO()
 	OUT	(FPLED_IO),A
 
 #ENDIF
@@ -2420,6 +2458,7 @@ HB_CPU3:
 ; OPERATING INTERRUPT MODE.  NOTE THAT INTERRUPTS REMAIN
 ; DISABLED AT THIS POINT.
 ;
+#IF (CPUFAM != CPU_EZ80)
 #IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180)))
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
@@ -2435,6 +2474,7 @@ HB_CPU3:
 	IM	2			; SWITCH TO INT MODE 2
   #ENDIF
 #ENDIF
+#ENDIF
 ;
 #IF (MEMMGR == MM_Z280)
 	; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE
@@ -2445,6 +2485,7 @@ HB_CPU3:
 	LDCTL	(C),HL
 #ENDIF
 ;
+#IF (CPUFAM != CPU_EZ80)
 #IF (INTMODE == 3)
 ;
 	; SETUP Z280 INT A FOR VECTORED INTERRUPTS
@@ -2456,6 +2497,7 @@ HB_CPU3:
 	IM	3
 ;
 #ENDIF
+#ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
 ; SYSTEM TIMER INITIALIZATION

From 572309d03c9158adbc97a43cef35dea3dd4e7925 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 6 Jun 2024 22:49:51 +1000
Subject: [PATCH 10/62] eZ80: reverted MDTRACE back to 1

---
 Source/HBIOS/cfg_rcez80.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 1304166b..5a9b7a67 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -204,7 +204,7 @@ EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
 MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	2		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

From baf0cd778889c7270555003d234400b5e8758c06 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 8 Jun 2024 16:38:46 +1000
Subject: [PATCH 11/62] eZ80: updated ide.asm to suppport eZ80 16 bit i/o
 operations

---
 Source/HBIOS/Config/RCEZ80_std.asm | 4 ++--
 Source/HBIOS/cfg_rcez80.asm        | 2 +-
 Source/HBIOS/ide.asm               | 4 ++++
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index f916d410..42aa6252 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -31,7 +31,7 @@ CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
@@ -59,7 +59,7 @@ SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
-IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 5a9b7a67..a27932d7 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -218,7 +218,7 @@ FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
 IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDETRACE	.EQU	3		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
 IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
 IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm
index 388c3181..6398522d 100644
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -1553,6 +1553,7 @@ IDE_WAIT001:
 	LD	C,(IY+IDE_IOBASE)
 	LD	B,8			; NUMBER OF REGISTERS TO CHECK
 IDE_WAIT002:
+	EZ80_IO
 	IN	A,(C)			; GET REGISTER VALUE
 	;CALL	PC_SPACE
 	;CALL	PRTHEXBYTE
@@ -1978,6 +1979,7 @@ IDE_IN:
 	LD	C,(IY+IDE_IOBASE)							; 19TS
 	ADD	A,C									; 4TS
 	LD	C,A									; 4TS
+	EZ80_IO
 	IN	A,(C)									; 12TS
 	POP	BC									; 10TS
 	EX	(SP),HL			; RESTORE STACK					; 19TS
@@ -1995,6 +1997,7 @@ IDE_OUT:
 	ADD	A,C
 	LD	C,A
 	POP	AF
+	EZ80_IO 
 	OUT	(C),A
 	POP	BC
 	EX	(SP),HL			; RESTORE STACK
@@ -2138,6 +2141,7 @@ IDE_REGDUMP:
 	LD	C,A
 	LD	B,7
 IDE_REGDUMP1:
+	EZ80_IO
 	IN	A,(C)
 	CALL	PRTHEXBYTE
 	DEC	C

From d834742337108d7a39d1c388363204e8835e099b Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 14 Jun 2024 15:56:33 +1000
Subject: [PATCH 12/62] eZ80: updated rp5rtc.asm to support eZ80 16 bit i/o
 operations

---
 Source/HBIOS/Config/RCEZ80_std.asm |  4 ++--
 Source/HBIOS/cfg_rcez80.asm        |  2 +-
 Source/HBIOS/rp5rtc.asm            | 23 +++++++++++++++++++++++
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 42aa6252..7aa6a916 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -34,7 +34,7 @@ FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	TRUE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
@@ -59,7 +59,7 @@ SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
-IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index a27932d7..0c172d11 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -218,7 +218,7 @@ FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
 IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	3		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDETRACE	.EQU	4		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
 IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
 IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/rp5rtc.asm b/Source/HBIOS/rp5rtc.asm
index 66753fcc..aa03aaf3 100644
--- a/Source/HBIOS/rp5rtc.asm
+++ b/Source/HBIOS/rp5rtc.asm
@@ -83,9 +83,11 @@ RP5RTC_INIT:
 RP5RTC_INIT1:
 ;	ENSURE DEVICE IS RESET AND NOT IN TEST MODE
 	LD	A, REG_TEST		; SELECT TEST REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 	CALL	DLY16
 	XOR	A
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A		; TURN OFF ALL TEST MODE BITS
 
 	LD	B, MODE_ALRMST
@@ -94,8 +96,10 @@ RP5RTC_INIT1:
 	CALL	RP5RTC_ENTIME
 
 	LD	A, REG_12_24		; SET TO 24 HOUR CLOCK
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 	LD	A, 1
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A
 
 	CALL	RP5RTC_RDTIM
@@ -179,7 +183,9 @@ RP5RTC_GETBYT:
 	LD	B, MODE_RAM0
 	CALL	RP5RTC_SETMD
 	LD	A, C			; SELECT NVRAM INDEX
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
+	EZ80_IO
 	IN	A, (RP5RTC_DAT)
 	AND	$0F			; RETRIEVE UNIT NIBBLE
 	LD	E, A
@@ -187,7 +193,9 @@ RP5RTC_GETBYT:
 	LD	B, MODE_RAM1
 	CALL	RP5RTC_SETMD
 	LD	A, C			; SELECT NVRAM INDEX
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
+	EZ80_IO
 	IN	A, (RP5RTC_DAT)
 	AND	$0F			; RETRIEVE UNIT NIBBLE
 	RLCA
@@ -218,14 +226,17 @@ RP5RTC_SETBYT:
 	LD	B, MODE_RAM0
 	CALL	RP5RTC_SETMD
 	LD	A, C			; SELECT NVRAM INDEX
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 	LD	A, E
 	AND	$0F
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A
 
 	LD	B, MODE_RAM1
 	CALL	RP5RTC_SETMD
 	LD	A, C			; SELECT NVRAM INDEX
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 	LD	A, E
 	AND	$F0
@@ -233,6 +244,7 @@ RP5RTC_SETBYT:
 	RRCA
 	RRCA
 	RRCA
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A
 
 	XOR	A			; SIGNAL SUCCESS
@@ -374,11 +386,14 @@ RP5RTC_RDTIM:
 ; MODE IN B (MODE_TIMEST, MODE_ALRMST, MODE_RAM0, MODE_RAM1)
 RP5RTC_SETMD:
 	LD	A, REG_MODE			; SELECT MODE REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 
+	EZ80_IO
 	IN	A, (RP5RTC_DAT)
 	AND	MD_TIME | MD_ALRM
 	OR	B
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A			; ASSIGN MODE
 	RET
 
@@ -391,14 +406,18 @@ RP5RTC_ENTIME:
 ; REGISTER IN B
 RP5RTC_RDVL:
 	LD	A, B				; SELECT UNIT REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
+	EZ80_IO
 	IN	A, (RP5RTC_DAT)
 	AND	$0F				; RETRIEVE UNIT NIBBLE
 	LD	L, A
 
 	INC	B
 	LD	A, B				; SELECT TENS REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
+	EZ80_IO
 	IN	A, (RP5RTC_DAT)
 	AND	$0F
 	RLCA
@@ -416,13 +435,16 @@ RP5RTC_RDVL:
 RP5RTC_WRVL:
 	LD	C, A
 	LD	A, B				; SELECT UNIT REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 
 	LD	A, C				; WRITE C (ONLY LOW NIBBLE WILL BE USED)
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A
 
 	INC	B
 	LD	A, B				; SELECT TENS REGISTER
+	EZ80_IO
 	OUT	(RP5RTC_REG), A
 
 	LD	A, C				; SHIFT TOP NIBBLE TO LOW NIBBLE
@@ -430,6 +452,7 @@ RP5RTC_WRVL:
 	RRCA
 	RRCA
 	RRCA
+	EZ80_IO
 	OUT	(RP5RTC_DAT), A			; WRITE IT
 
 	RET

From 4ac7c1213a7c7085e5bcf3707467c326b099036a Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 14 Jun 2024 22:00:11 +1000
Subject: [PATCH 13/62] eZ80: updated tms.asm to support eZ80 16 bit i/o
 operations

---
 Source/HBIOS/Config/RCEZ80_std.asm |  6 ++--
 Source/HBIOS/tms.asm               | 50 ++++++++++++++++++++++++------
 2 files changed, 44 insertions(+), 12 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 7aa6a916..a2d33aed 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -26,7 +26,7 @@
 ;
 #include "cfg_rcez80.asm"
 ;
-CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
@@ -44,9 +44,9 @@ EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index e8fbbf40..8c776315 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -182,9 +182,9 @@ TMS_PREINIT:
 	; DISABLE INTERRUPT GENERATION UNTIL AFTER INTERRUPT HANDLER
 	; HAS BEEN INSTALLED.
 	LD	A, (TMS_INITVDU_REG_1)
-        RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
+	RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
 	LD	(TMS_INITVDU_REG_1), A
-        LD	C, TMSCTRL1
+	LD	C, TMSCTRL1
 	JP	TMS_SET
 ;
 TMS_INIT:
@@ -194,6 +194,7 @@ TMS_INIT:
 ;
 #IF ((TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
 	LD	A,$FF
+	EZ80_IO
 	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
 #ENDIF
 ;
@@ -202,6 +203,7 @@ TMS_INIT:
 
 #IF ((TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO))
 	LD	A,$FE
+	EZ80_IO
 	OUT	(TMS_ACR),A		; CLEAR VDP RESET
 #ENDIF
 ;
@@ -288,10 +290,12 @@ TMS_INIT1:
   #IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
 	; ENABLE VDP INTERRUPTS ON NABU INTERRUPT CONTROLLER
 	LD	A,14			; PSG R14 (PORT A DATA)
+	EZ80_IO
 	OUT	(NABU_RSEL),A		; SELECT IT
 	LD	A,(NABU_CTLVAL)		; GET NABU CTL PORT SHADOW REG
 	SET	4,A			; ENABLE VDP INTERRUPTS
 	LD	(NABU_CTLVAL),A		; UPDATE SHADOW REG
+	EZ80_IO
 	OUT	(NABU_RDAT),A		; WRITE TO HARDWARE
   #ENDIF
 ;
@@ -551,10 +555,12 @@ TMS_READ:
 ;
 TMS_SET:
 	HB_DI
+	EZ80_IO
 	OUT	(TMS_CMDREG),A		; WRITE IT
 	TMS_IODELAY
 	LD	A,C			; GET THE DESIRED REGISTER
 	OR	$80			; SET BIT 7
+	EZ80_IO
 	OUT	(TMS_CMDREG),A		; SELECT THE DESIRED REGISTER
 	TMS_IODELAY
 	HB_EI
@@ -568,13 +574,15 @@ TMS_SET:
 ;
 TMS_WR:
 #IF ((TMSMODE == TMSMODE_MSX9958)  | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80))
-        ; CLEAR R#14 FOR V9958
+	; CLEAR R#14 FOR V9958
 	HB_DI
-        XOR     A
-        OUT     (TMS_CMDREG), A
+	XOR	A
+	EZ80_IO
+	OUT	(TMS_CMDREG), A
 	TMS_IODELAY
-        LD      A, $80 | 14
-        OUT     (TMS_CMDREG), A
+	LD	A, $80 | 14
+	EZ80_IO
+	OUT	(TMS_CMDREG), A
 	TMS_IODELAY
 	HB_EI
 #ENDIF
@@ -588,9 +596,11 @@ TMS_WR:
 TMS_RD:
 	HB_DI
 	LD	A,L
+	EZ80_IO
 	OUT	(TMS_CMDREG),A
 	TMS_IODELAY
 	LD	A,H
+	EZ80_IO
 	OUT	(TMS_CMDREG),A
 	TMS_IODELAY
 	HB_EI
@@ -608,10 +618,12 @@ TMS_PROBE:
 	CALL	TMS_WR
 	; WRITE TEST PATTERN TO FIRST TWO BYTES
 	LD	A,$A5			; FIRST BYTE
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; OUTPUT
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
 	CPL				; COMPLEMENT ACCUM
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; SECOND BYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
@@ -621,11 +633,13 @@ TMS_PROBE:
 	CALL	TMS_RD
 	; READ TEST PATTERN
 	LD	C,$A5			; VALUE TO EXPECT
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; READ FIRST BYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
 	CP	C			; COMPARE
 	RET	NZ			; RETURN ON MISCOMPARE
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; READ SECOND BYTE
 	;TMS_IODELAY			; DELAY
 	CALL	DLY64			; DELAY
@@ -646,6 +660,7 @@ TMS_CRTINIT:
 	LD	DE,$4000		; 16KB
 TMS_CRTINIT1:
 	XOR	A
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY			; DELAY
 	DEC	DE
@@ -672,7 +687,7 @@ TMS_CRTINIT2:
 	LD	A,%00000100		; ONLY WTE BIT SET
 	CALL	TMS_SET			; DO IT
 #ENDIF
-    	RET
+	RET
 ;
 ;----------------------------------------------------------------------
 ; CLEAR SCREEN AND HOME CURSOR
@@ -730,6 +745,7 @@ TMS_LOADFONT:
 	LD	DE,TMS_FNTSIZE
 TMS_LOADFONT1:
 	LD	A,(HL)
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY			; DELAY
 	INC	HL
@@ -766,11 +782,13 @@ TMS_SETCUR:
 	PUSH	DE			; PRESERVE DE
 	LD	HL,(TMS_POS)		; GET CURSOR POSITION
 	CALL	TMS_RD			; SETUP TO READ VDU BUF
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; GET REAL CHAR UNDER CURSOR
 	TMS_IODELAY			; DELAY
 	PUSH	AF			; SAVE THE CHARACTER
 	CALL	TMS_WR			; SETUP TO WRITE TO THE SAME PLACE
 	LD	A,$FF			; REPLACE REAL CHAR WITH 255
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; DO IT
 	TMS_IODELAY			; DELAY
 	POP	AF			; RECOVER THE REAL CHARACTER
@@ -794,6 +812,7 @@ TMS_SETCUR0:				; MULT BY 8 FOR FONT INDEX
 	LD	B,8			; 8 BYTES
 	LD	HL,TMS_BUF		; INTO BUFFER
 TMS_SETCUR1:				; READ GLYPH LOOP
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; GET NEXT BYTE
 	TMS_IODELAY			; IO DELAY
 	LD	(HL),A			; SAVE VALUE IN BUF
@@ -809,6 +828,7 @@ TMS_SETCUR2:				; WRITE INVERTED GLYPH LOOP
 	LD	A,(HL)			; GET THE BYTE
 	INC	HL			; BUMP THE BUF POINTER
 	XOR	$FF			; INVERT THE VALUE
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; WRITE IT TO VDU
 	TMS_IODELAY			; IO DELAY
 	DJNZ	TMS_SETCUR2		; LOOP FOR ALL 8 BYTES OF GLYPH
@@ -825,6 +845,7 @@ TMS_CLRCUR:	; REMOVE VIRTUAL CURSOR FROM SCREEN
 	LD	HL,(TMS_POS)		; POINT TO CURRENT CURSOR POS
 	CALL	TMS_WR			; SET UP TO WRITE TO VDU
 	LD	A,(TMS_CURSAV)		; GET THE REAL CHARACTER
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; WRITE IT
 	TMS_IODELAY			; IO DELAY
 	POP	HL			; RECOVER HL
@@ -864,6 +885,7 @@ TMS_PUTCHAR:
 	LD	HL,(TMS_POS)		; LOAD CURRENT POSITION INTO HL
 	CALL	TMS_WR			; SET THE WRITE ADDRESS
 	POP	AF			; RECOVER CHARACTER TO WRITE
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; WRITE THE CHARACTER
 	TMS_IODELAY
 	LD	HL,(TMS_POS)		; LOAD CURRENT POSITION INTO HL
@@ -885,6 +907,7 @@ TMS_FILL:
 ;
 TMS_FILL1:
 	LD	A,C			; RECOVER CHARACTER TO WRITE
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY
 	DEC	DE
@@ -910,6 +933,7 @@ TMS_SCROLL0:				; READ LINE THAT IS ONE PAST CURRENT DESTINATION
 	LD	DE,TMS_BUF
 	LD	B,TMS_COLS
 TMS_SCROLL1:
+	EZ80_IO
 	IN	A,(TMS_DATREG)
 	TMS_IODELAY
 	LD	(DE),A
@@ -923,6 +947,7 @@ TMS_SCROLL1:
 	LD	B,TMS_COLS
 TMS_SCROLL2:
 	LD	A,(DE)
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY
 	INC	DE
@@ -939,6 +964,7 @@ TMS_SCROLL2:
 	LD	A,' '
 	LD	B,TMS_COLS
 TMS_SCROLL3:
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY
 	DJNZ	TMS_SCROLL3
@@ -963,6 +989,7 @@ TMS_RSCROLL0:	; READ THE LINE THAT IS ONE PRIOR TO CURRENT DESTINATION
 	LD	DE,TMS_BUF		; POINT TO BUFFER
 	LD	B,TMS_COLS		; LOOP FOR EACH COLUMN
 TMS_RSCROLL1:
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; GET THE CHAR
 	TMS_IODELAY			; RECOVER
 	LD	(DE),A			; SAVE IN BUFFER
@@ -976,6 +1003,7 @@ TMS_RSCROLL1:
 	LD	B,TMS_COLS		; INIT LOOP COUNTER
 TMS_RSCROLL2:
 	LD	A,(DE)			; LOAD THE CHAR
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; WRITE TO SCREEN
 	TMS_IODELAY			; DELAY
 	INC	DE			; BUMP BUF POINTER
@@ -992,6 +1020,7 @@ TMS_RSCROLL2:
 	LD	A,' '
 	LD	B,TMS_COLS
 TMS_RSCROLL3:
+	EZ80_IO
 	OUT	(TMS_DATREG),A
 	TMS_IODELAY
 	DJNZ	TMS_RSCROLL3
@@ -1013,6 +1042,7 @@ TMS_BLKCPY1:
 	LD	DE,TMS_BUF		; POINT TO BUFFER
 	LD	B,C
 TMS_BLKCPY2:
+	EZ80_IO
 	IN	A,(TMS_DATREG)		; GET THE NEXT BYTE
 	TMS_IODELAY			; DELAY
 	LD	(DE),A			; SAVE IN BUFFER
@@ -1027,6 +1057,7 @@ TMS_BLKCPY2:
 	LD	B,C
 TMS_BLKCPY3:
 	LD	A,(DE)			; GET THE CHAR FROM BUFFER
+	EZ80_IO
 	OUT	(TMS_DATREG),A		; WRITE TO VDU
 	TMS_IODELAY			; DELAY
 	INC	DE			; BUMP BUF PTR
@@ -1069,7 +1100,8 @@ TMS_Z180IOX:
 
 #IF (TMSTIMENABLE & (INTMODE > 0))
 TMS_TSTINT:
- 	IN      A,(TMS_CMDREG)		; TEST FOR INT FLAG
+	EZ80_IO
+	IN	A,(TMS_CMDREG)		; TEST FOR INT FLAG
 	AND	$80
 	JR	NZ,TMS_INTHNDL
 	AND	$00			; RETURN Z - NOT HANDLED

From 20bdb78084f17e196131b247c27ee9b87b4a45ec Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 15 Jun 2024 14:23:19 +1000
Subject: [PATCH 14/62] eZ80: tms.asm interrupt handling activated - with
 appropriate delegation from the eZ80 firmware

---
 Source/HBIOS/Config/RCEZ80_std.asm |  2 +-
 Source/HBIOS/cfg_rcez80.asm        |  2 +-
 Source/HBIOS/hbios.asm             | 18 ++++++++++++++----
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index a2d33aed..f5a95c4c 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -45,7 +45,7 @@ EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSTIMENABLE	.SET	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 0c172d11..817eb23d 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -31,7 +31,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 9983e7d1..30bb4887 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -357,6 +357,9 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
   #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
   #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
+
+  #DEFINE RET.L		.DB	$49 \ RET
+
 #ELSE
   #DEFINE EZ80_IO
 #ENDIF
@@ -1178,7 +1181,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 HBX_RETI:
 	RETI
 ;
-  #ELSE
+  #ELSE ; (MEMMGR == MM_Z280)
 ;
 ; COMMON INTERRUPT DISPATCHING CODE
 ; SETUP AND CALL HANDLER IN BIOS BANK
@@ -1216,16 +1219,23 @@ HBX_INT_SP	.EQU	$ - 2
 ;
 	POP	HL			; RESTORE HL
 ;
+
+#IF (CPUFAM == CPU_EZ80)
+	RET.L				; INTERRUPTS WILL BE ENABLED BY BY EZ80 FIRMWARE
+					; CAN THEY BE ENABLED HERE - DOES THAT RISK RE-ENTRANT OF THE HANDLER?
+#ELSE
 	HB_EI				; ENABLE INTERRUPTS
 	RETI				; AND RETURN
+#ENDIF
+
 ;
-  #ENDIF
+  #ENDIF ; END ELSE IF (MEMMGR == MM_Z280)
 ;
-#ELSE
+#ELSE ; #IF (INTMODE > 0)
 ;
 	RET
 ;
-#ENDIF
+#ENDIF ; #END ELSE IF (INTMODE > 0)
 ;
 ; SMALL TEMPORARY STACK FOR USE BY HBX_BNKCPY
 ;

From 6b00f5c992c5d4f65bcbd1f4dd6977a72bb50678 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 15 Jun 2024 20:15:18 +1000
Subject: [PATCH 15/62] eZ80: tms.asm increased speed of interrupt handler's IO
 process

---
 Source/HBIOS/hbios.asm | 1 +
 Source/HBIOS/tms.asm   | 6 +++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 30bb4887..0cbbf3c4 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -359,6 +359,7 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 
   #DEFINE RET.L		.DB	$49 \ RET
+IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
 
 #ELSE
   #DEFINE EZ80_IO
diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index 8c776315..fd955b16 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -1100,8 +1100,12 @@ TMS_Z180IOX:
 
 #IF (TMSTIMENABLE & (INTMODE > 0))
 TMS_TSTINT:
-	EZ80_IO
+#IF (CPUFAM == CPU_EZ80)
+	LD	BC, IO_SEGMENT<<8 | TMS_CMDREG
+	IN	A,(C)			; TEST FOR INT FLAG
+#ELSE
 	IN	A,(TMS_CMDREG)		; TEST FOR INT FLAG
+#ENDIF
 	AND	$80
 	JR	NZ,TMS_INTHNDL
 	AND	$00			; RETURN Z - NOT HANDLED

From a31119bd5d5f0a9ae4d606b9ac711a07eff2640a Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 4 Jul 2024 12:05:49 +1000
Subject: [PATCH 16/62] ez80: updated notes for the docker build script

---
 Dockerfile | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/Dockerfile b/Dockerfile
index 770c6ceb..d2e716e1 100644
--- a/Dockerfile
+++ b/Dockerfile
@@ -1,12 +1,25 @@
 FROM ubuntu:jammy-20240111 as basebuilder
 
-# docker build --progress plain -t vipoo/romwbw .
+# This docker file can be used to build a tool chain docker image for building RomWBW images.
 
-# docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it vipoo/romwbw:latest
+# Tested on a ubuntu host and on Windows un WSL (with docker desktop)
+
+# First build the docker image (will b)
+# docker build --progress plain -t romwbw-chain .
+
+# After you have built the above image (called romwbw-chain), you can use it to compile and build the RomWBW images
+# as per the standard make scripts within RomWBW.
+# Start a new terminal, cd to where you have clone RomWBW, and then run this command: 
+# docker run -v ${PWD}:/src/ --privileged=true -u $(id -u ${USER}):$(id -g ${USER}) -it romwbw-chain:latest
+
+# you can now compile and build the required images:
 
 # cd Tools && make
+# cd Source && make # at least once to build many common units
 # cd Source && make rom ROM_PLATFORM=RCEZ80 ROM_CONFIG=std
 
+# when finish, type 'exit' to return to back to your standard terminal session
+
 LABEL Maintainer="Dean Netherton" \
       Description="spike to use clang for ez80 target"
 
@@ -33,4 +46,3 @@ WORKDIR /src/
 RUN apt install -y --no-install-recommends build-essential libncurses-dev srecord bsdmainutils
 
 RUN adduser --disabled-password --gecos "" builder
-

From 44d890be599eca9e4730c88e37d253effa4a20d3 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 7 Jul 2024 09:58:42 +1000
Subject: [PATCH 17/62] ez80: Added new driver ez80rtc

---
 Source/Doc/SystemGuide.md          |  17 +--
 Source/HBIOS/Config/RCEZ80_std.asm |   7 +-
 Source/HBIOS/cfg_rcez80.asm        |   2 +
 Source/HBIOS/ez80rtc.asm           | 172 +++++++++++++++++++++++++++++
 Source/HBIOS/hbios.asm             |  11 ++
 Source/HBIOS/hbios.inc             |   1 +
 Source/HBIOS/rp5rtc.asm            |   2 +-
 Source/RomDsk/Makefile             |   2 +-
 Source/RomDsk/ROM_384KB/WDATE.COM  | Bin 0 -> 2816 bytes
 9 files changed, 200 insertions(+), 14 deletions(-)
 create mode 100644 Source/HBIOS/ez80rtc.asm
 create mode 100644 Source/RomDsk/ROM_384KB/WDATE.COM

diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md
index a2b6089e..07e32b77 100644
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -889,14 +889,15 @@ more than one at a time.  The RTC unit is assigned a Device Type ID
 which indicates the specific hardware device driver that handles the 
 unit.  The table below enumerates these values.
 
-| **Device Type** | **ID** | **Description**                          | **Driver** |
-|-----------------|-------:|------------------------------------------|------------|
-| RTCDEV_DS       | 0x00   | Maxim DS1302 Real-Time Clock w/ NVRAM    | dsrtc.asm  |
-| RTCDEV_BQ       | 0x01   | BQ4845P Real Time Clock                  | bqrtc.asm  |
-| RTCDEV_SIMH     | 0x02   | SIMH Simulator Real-Time Clock           | simrtc.asm |
-| RTCDEV_INT      | 0x03   | Interrupt-based Real Time Clock          | intrtc.asm |
-| RTCDEV_DS7      | 0x04   | Maxim DS1307 PCF I2C RTC w/ NVRAM        | ds7rtc.asm |
-| RTCDEV_RP5      | 0x05   | Ricoh RPC01A Real-Time Clock w/ NVRAM    | rp5rtc.asm |
+| **Device Type** | **ID** | **Description**                          | **Driver**  |
+|-----------------|-------:|------------------------------------------|-------------|
+| RTCDEV_DS       | 0x00   | Maxim DS1302 Real-Time Clock w/ NVRAM    | dsrtc.asm   |
+| RTCDEV_BQ       | 0x01   | BQ4845P Real Time Clock                  | bqrtc.asm   |
+| RTCDEV_SIMH     | 0x02   | SIMH Simulator Real-Time Clock           | simrtc.asm  |
+| RTCDEV_INT      | 0x03   | Interrupt-based Real Time Clock          | intrtc.asm  |
+| RTCDEV_DS7      | 0x04   | Maxim DS1307 PCF I2C RTC w/ NVRAM        | ds7rtc.asm  |
+| RTCDEV_RP5      | 0x05   | Ricoh RPC01A Real-Time Clock w/ NVRAM    | rp5rtc.asm  |
+| RTCDEV_EZ80     | 0x06   | eZ80 on-chip RTC                         | ez80rtc.asm |
 
 The time functions to get and set the time (RTCGTM and RTCSTM) require a
 6 byte date/time buffer in the following format. Each byte is BCD 
diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index f5a95c4c..b72ac5ec 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -33,8 +33,7 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-RP5RTCENABLE	.SET	TRUE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
@@ -44,8 +43,8 @@ EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSTIMENABLE	.SET	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 817eb23d..a04ac19f 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -117,6 +117,8 @@ DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
 BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
 BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
+EZ80RTCENABLE	.EQU	TRUE		; EZ80 ON CHIP RTC
+;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
 RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
new file mode 100644
index 00000000..ff6e105c
--- /dev/null
+++ b/Source/HBIOS/ez80rtc.asm
@@ -0,0 +1,172 @@
+;
+;==================================================================================================
+; EZ80 ON-CHIP CLOCK DRIVER
+;==================================================================================================
+;
+EZ80RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+; RTC DEVICE INITIALIZATION ENTRY
+
+		DEVECHO	"EZ80 RTC:\n"
+
+EZ80RTC_INIT:
+	; display driver install message
+	; delegate init function to firmware
+	; install dispatcher
+	; dispatch local routine that delgates to firmware routines
+
+	LD	A, (RTC_DISPACT)	; RTC DISPATCHER ALREADY SET?
+	OR	A			; SET FLAGS
+	RET	NZ			; IF ALREADY ACTIVE, ABORT
+
+	CALL	NEWLINE			; FORMATTING
+	PRTS("EZ80 RTC: ON-CHIP$")
+
+	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
+	LD	B, 0			; RTC INIT FUNCTION
+	EZ80_FN	
+	; TODO VERIFY SUCCESS -> A IS ZERO
+
+	; DISPLAY CURRENT TIME
+	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
+	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
+	LD	B, 1			; READ DATE-TIME INTO (HL)
+	EZ80_FN
+
+	LD	HL, EZ80RTC_BCDBUF	; POINT TO BCD BUF
+	CALL	PRTDT			; DISPLAY THIS TIME
+;
+	LD	BC, EZ80RTC_DISPATCH
+	CALL	RTC_SETDISP
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+
+;
+; RTC DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+EZ80RTC_DISPATCH:
+	LD	A,B			; GET REQUESTED FUNCTION
+	AND	$0F			; ISOLATE SUB-FUNCTION
+	JP	Z,EZ80RTC_GETTIM		; GET TIME
+	DEC	A
+	JP	Z,EZ80RTC_SETTIM		; SET TIME
+	DEC	A
+	JP	Z,EZ80RTC_GETBYT		; GET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,EZ80RTC_SETBYT		; SET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,EZ80RTC_GETBLK		; GET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,EZ80RTC_SETBLK		; SET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,EZ80RTC_GETALM		; GET ALARM
+	DEC	A
+	JP	Z,EZ80RTC_SETALM		; SET ALARM
+	DEC	A
+	JP	Z,EZ80RTC_DEVICE		; REPORT RTC DEVICE INFO
+	SYSCHKERR(ERR_NOFUNC)
+	RET
+;
+; RTC GET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (OUT)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+EZ80RTC_GETTIM:
+	PUSH	HL
+	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
+	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
+	LD	B, 1			; READ DATE-TIME INTO (HL)
+	EZ80_FN
+
+	LD	A, BID_BIOS		; COPY FROM BIOS BANK
+	LD	(HB_SRCBNK), A		; SET IT
+	LD	A, (HB_INVBNK)		; COPY TO CURRENT USER BANK
+	LD	(HB_DSTBNK), A		; SET IT
+	LD	HL, EZ80RTC_BCDBUF	; SOURCE ADR
+	POP	DE			; DEST ADR
+	LD	BC, EZ80RTC_BUFSIZ	; LENGTH
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;
+; RTC SET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (IN)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSSWW
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+EZ80RTC_SETTIM:
+	; COPY TO BCD BUF
+	LD	A,(HB_INVBNK)		; COPY FROM CURRENT USER BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,BID_BIOS		; COPY TO BIOS BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	DE,EZ80RTC_BCDBUF	; DEST ADR
+	LD	BC,EZ80RTC_BUFSIZ	; LENGTH
+	CALL	HB_BNKCPY		; COPY THE RPC DATA
+
+	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
+	LD	(HL), $20		; CENTURY NOT SUPPORT BY HBIOS
+	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
+	LD	B, 2			; WRITE DATE-TIME FROM (HL)
+	EZ80_FN
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; RTC GET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE (OUTPUT)
+;   A:0 IF OK, ERR_RANGE IF OUT OF RANGE
+;
+EZ80RTC_GETBYT:
+	SYSCHKERR(ERR_NOTIMPL)
+	; XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+
+
+; RTC SET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE
+;   A:0 IF OK, ERR_RANGE IF OUT OF RANGE
+;
+EZ80RTC_SETBYT:
+	SYSCHKERR(ERR_NOTIMPL)
+	; XOR	A			; SIGNAL SUCCESS
+	RET
+
+EZ80RTC_GETBLK:
+EZ80RTC_SETBLK:
+EZ80RTC_GETALM:
+EZ80RTC_SETALM:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; REPORT RTC DEVICE INFO
+;
+EZ80RTC_DEVICE:
+	LD	D, RTCDEV_EZ80		; D := DEVICE TYPE
+	LD	E, 0			; E := PHYSICAL DEVICE NUMBER
+	LD	HL, 00			; H := 0, DRIVER HAS NO MODES,  L := 0, NO I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+
+
+; REGISTER EXTRACTED VALUES
+;
+EZ80RTC_BCDBUF_EXT:
+EZ80RTC_CN	.DB	20	; CENTURY
+EZ80RTC_BCDBUF:
+EZ80RTC_YR	.DB	24
+EZ80RTC_MO	.DB	01
+EZ80RTC_DT	.DB	01
+EZ80RTC_HH	.DB	00
+EZ80RTC_MM	.DB	00
+EZ80RTC_SS	.DB	00
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 0cbbf3c4..6d476148 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -3779,6 +3779,9 @@ HB_INITTBL:
 #IF (RP5RTCENABLE)
 	.DW	RP5RTC_INIT
 #ENDIF
+#IF (EZ80RTCENABLE)
+	.DW	EZ80RTC_INIT
+#ENDIF
 #IF (VDUENABLE)
 	.DW	VDU_INIT
 #ENDIF
@@ -8051,6 +8054,14 @@ SIZ_RP5RTC	.EQU	$ - ORG_RP5RTC
 		MEMECHO	SIZ_RP5RTC
 		MEMECHO	" bytes.\n"
 #ENDIF
+#IF (EZ80RTCENABLE)
+ORG_EZ80RTC	.EQU	$
+  #INCLUDE "ez80rtc.asm"
+SIZ_EZ80RTC	.EQU	$ - ORG_EZ80RTC
+		MEMECHO	"EZ80RTC occupies "
+		MEMECHO	SIZ_EZ80RTC
+		MEMECHO	" bytes.\n"
+#ENDIF
 #IF (ASCIENABLE)
 ORG_ASCI	.EQU	$
   #INCLUDE "asci.asm"
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index 2cabc656..8949f3fc 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -359,6 +359,7 @@ RTCDEV_SIMH	.EQU	$02		; SIMH
 RTCDEV_INT	.EQU	$03		; PERIODIC INT TIMER
 RTCDEV_DS7	.EQU	$04		; DS1307 (I2C)
 RTCDEV_RP5	.EQU	$05		; RP5C01
+RTCDEV_EZ80	.EQU	$06		; EZ80 ON-CHIP RTC
 ;
 ; DSKY DEVICE IDS
 ;
diff --git a/Source/HBIOS/rp5rtc.asm b/Source/HBIOS/rp5rtc.asm
index aa03aaf3..2a7b99a6 100644
--- a/Source/HBIOS/rp5rtc.asm
+++ b/Source/HBIOS/rp5rtc.asm
@@ -297,7 +297,7 @@ RP5RTC_SETTIM:
 	LD	(HB_DSTBNK),A		; SET IT
 	LD	DE,RP5RTC_BCDBUF	; DEST ADR
 	LD	BC,RP5RTC_BUFSIZ	; LENGTH
-	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+	CALL	HB_BNKCPY		; COPY THE RPC DATA
 ;
 	LD	B, MODE_TIMEST
 	CALL	RP5RTC_SETMD
diff --git a/Source/RomDsk/Makefile b/Source/RomDsk/Makefile
index 1f067db1..c4ab2ec3 100644
--- a/Source/RomDsk/Makefile
+++ b/Source/RomDsk/Makefile
@@ -6,7 +6,7 @@ include $(TOOLS)/Makefile.inc
 
 .SHELLFLAGS = -ce
 
-ROMAPPS1 := assign mode rtc syscopy xm
+ROMAPPS1 := assign mode rtc syscopy xm ../../Source/Images/Common/All/WDATE
 ROMAPPS2 := fdu format survey sysgen talk timer cpuspd
 
 rom128_%.dat: DISKDEF=wbw_rom128
diff --git a/Source/RomDsk/ROM_384KB/WDATE.COM b/Source/RomDsk/ROM_384KB/WDATE.COM
new file mode 100644
index 0000000000000000000000000000000000000000..c7ab78e304f4e190a716a56aebc7e2cfb0da4fa9
GIT binary patch
literal 2816
zcmd^ATWl0n7(P2YGka?b+d?~~P|mnShg-W8gu3c9U_%MeR$&nXsb$*^-2&Zd_R{XQ
zuwr5~KA4dBV4{gWXd;S<0^(v~V%BESNplEmToX++PRQ^8LMXc6gPHoDnU;$r>Vt_7
z?q<&So$tS#vuFPEFGBzO&twH_h?iMX=ETqFsB4B8<SYUM`Hmys&>4`)H^K81N1A;m
z`a))OO?;Ijjf|y@&S?cY<@xkjfJ>VQ-_r9CDI<-vGuo^zOJtr@@wUSa%Rw`}L04H0
zl1tolNz~a|)JtyiuxwE?$cG+lH-?F%3bQikCRc2sEVogA*vDM~atJiYF22r9HZo^}
zPI8W^__UP*q&mQaKIR5Pr#aOKo#NC7k^h3LKHQ^|uifNr2ExEhUbe_-j(jjnLT9LG
zWe$CEhvw#7Z)fuBELqOO57xCpiLT~9!NG9^0)a(5s;VPDF=K%mN*|?^1R1@U*Z$t|
z&oTETr|J6VGCQg&?$D)k^!}yq${47b-3J+V@rayvNl)dZI&%x=3C~Qv!J1D4TS(dD
zJ1m<vU9G(M95?w8LmFJBLt0>n`>kq$!@FH36Gllq!PTN?meh|Gb>aPV%SkSDl7o8S
z$Tdb-W->tbIE4n&3FHN*P;K%+a!$cxm!e&Els7VBVz&Nnn}mxPW7HhQiKse;qspNX
zoK(`uN^kS1EsZMi#E=@R^rAH_Yu7!zenTtTm52-~Av`t^Nh)}6b9A%^@14jfk@yij
zF|5XtQNV#n=132oh^i?|9g3xr$`QObq4cY<fgTL$?C@aIn#d~Lua0EmLxa&Imim{s
z1Y6ePZOZ6S3~y4^n6e6YJh>f@u5AiJ)TYP)j-`hClz0eR6LlmB+iOB$RmH=RSO!Pp
zgQ;O9mP|CEE*0+xKY_YaNv!V2@kne?xxYtkhQOeRD74tH)`s;WszQWAWw{dWf$XIh
zL^BHIQWet+a&bDZYh|d->`f&3Kr=wp1HyGE#A&T8W6Qs6dRtxRHdy?ebtj=n%i$hz
z7jNH6cs<j4Q7f0Hn(gnUd8C$~wny#unU@OX_D*@eh|pB)RDIA<e`WcV$MG-I`JzTG
zpr?6v-PHqEcYtmF&AR4}%$9qFjos7Xo_#}k&F~|X%}H#aM)(anR4H3+Pi__ItWX|5
zjh*B@emsX=6Q%<*LakB1GCviXYAAVovrMA6(%Aq$H(+h+Znk&!9rSw<$?y~Bf{ar}
z%;7T<BmAtxI;6nEwKNL$l1mK{{GR2ZOMDxIHnqSg^d00;w<p|_hm-q3cEFK>tBi!3
z1*6oPJ}GetUqFDJ<u#bNveiD=by*vReTqkszuWCNipV~f*zL{+9@y?~>2k}c<$@dL
zp)PkvZ!N0Nni#ueG`5n%ztRn_*iKEkuc*Ed*yD3CV4x|4A7RkWlXqQ~Tj+v2CoKWn
zY#vB1T$~NFmdw$NS+iN<&DHR$>tzSH1PYsJuDSG%TpA96W~f|`s6m$<IcVgw_8hJN
zZ9M`}2Q?s+?yu7SLV-gzj+oA%qhZswQs2Q^)X2h1_Oy5E;hqxA24H4DMP1!w<ckIH
z@E>!4RLoPC)rL{%<dN9z^<?w<z9IT9ihE#yKo_kQ`ZA1?VaMp>r=>-Pe}GmI<u!(%
zo#Twa72&`%7~sEeohK)G#-Z!6@)F^ZacG-C(<!YoS!tQc!NW_7O&2_FNiaRqeA5e$
zPjZ_Tl3QLZxaCHHm6r-gg9gfqC%qa}I4hn7gpA_nfKI?K0a?HzAP4w8AP=Z}HSscV
z8nYLW#`FWym_vXxCJsnr(ttGPFrW+Yc|bSdi+~=$R{*_$uL1f1-vX=vJZ`UnoD7GY
zoP*^Vc55V-io`Q$v(gv0NM|J8A4MBS;zNf}XC#BRreX>VhcakmYA}^ZqMgb}QlVWE
zb@wM#ie2icEwn5BHrbhqL6=6I(2xPbDJ4O1w=xj3SvZ=CThiwE5Vh=#BvWxp+S=NX
zvBI3mn!B+#kTs8EHjvdd>-Aip(F)y{u1~dfOtnq59qq_mns+p>6?kveOvSO_?;yMc
zpO5mIJVUN|bJAl_Wd1Y0ELrTU4%GYu5YPB{k#Ig*KJv_5nstzd$F^*gv&7>Y3;gvs
MZH3#{>R(y^4-_PiqyPW_

literal 0
HcmV?d00001


From ce9778e189cf48989b925a461f773bbaec9d7403 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 8 Jul 2024 16:35:38 +1000
Subject: [PATCH 18/62] ez80: implemented timer get/set function - delegates to
 firmware

---
 Source/HBIOS/cfg_rcez80.asm       |   2 +-
 Source/HBIOS/hbios.asm            |  31 ++++++++++++++++++++++++++++++
 Source/RomDsk/Makefile            |   4 ++--
 Source/RomDsk/ROM_384KB/timer.com | Bin 0 -> 900 bytes
 4 files changed, 34 insertions(+), 3 deletions(-)
 create mode 100644 Source/RomDsk/ROM_384KB/timer.com

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index a04ac19f..3cd7910b 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -31,7 +31,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (EZ80 operates with IM 2 - simulating IM 1)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 6d476148..9d22a730 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -5058,6 +5058,13 @@ SYS_GETFN:
 ;     DE:HL: TIMER VALUE (32 BIT)
 ;
 SYS_GETTIMER:
+#IF (CPUFAM == CPU_EZ80)
+	LD	A, 2
+	LD	B, 0	; GET TIMER TICK
+	EZ80_FN
+	RET
+
+#ELSE
 	LD	HL,HB_TICKS
 	HB_DI
 	CALL	LD32
@@ -5065,6 +5072,8 @@ SYS_GETTIMER:
 	LD	C, TICKFREQ
 	XOR	A
 	RET
+#ENDIF
+
 ;
 ; GET SECONDS
 ;   RETURNS:
@@ -5072,6 +5081,13 @@ SYS_GETTIMER:
 ;     C: NUM TICKS WITHIN CURRENT SECOND
 ;
 SYS_GETSECS:
+#IF (CPUFAM == CPU_EZ80)
+	LD	A, 2
+	LD	B, 1	; GET SECOND TICK
+	EZ80_FN
+	RET
+
+#ELSE
 	LD	HL,HB_SECS
 	HB_DI
 	CALL	LD32
@@ -5082,6 +5098,7 @@ SYS_GETSECS:
 	LD	C,A
 	XOR	A
 	RET
+#ENDIF
 ;
 ; GET BOOT INFORMATION
 ;   RETURNS:
@@ -5289,24 +5306,38 @@ SYS_SETBOOTINFO:
 ;     DE:HL: TIMER VALUE (32 BIT)
 ;
 SYS_SETTIMER:
+#IF (CPUFAM == CPU_EZ80)
+	LD	A, 2
+	LD	B, 2	; SET TICKS
+	EZ80_FN
+	RET
+#ELSE
 	LD	BC,HB_TICKS
 	HB_DI
 	CALL	ST32
 	HB_EI
 	XOR	A
 	RET
+#ENDIF
 ;
 ; SET SECS
 ;   ON ENTRY:
 ;     DE:HL: SECONDS VALUE (32 BIT)
 ;
 SYS_SETSECS:
+#IF (CPUFAM == CPU_EZ80)
+	LD	A, 2
+	LD	B, 3	; SET SECS
+	EZ80_FN
+	RET
+#ELSE
 	LD	BC,HB_SECS
 	HB_DI
 	CALL	ST32
 	HB_EI
 	XOR	A
 	RET
+#ENDIF
 ;
 ; SET SYSTEM CPU SPEED ATTRIBUTES
 ;   ON ENTRY:
diff --git a/Source/RomDsk/Makefile b/Source/RomDsk/Makefile
index c4ab2ec3..57e5ff7c 100644
--- a/Source/RomDsk/Makefile
+++ b/Source/RomDsk/Makefile
@@ -6,8 +6,8 @@ include $(TOOLS)/Makefile.inc
 
 .SHELLFLAGS = -ce
 
-ROMAPPS1 := assign mode rtc syscopy xm ../../Source/Images/Common/All/WDATE
-ROMAPPS2 := fdu format survey sysgen talk timer cpuspd
+ROMAPPS1 := assign mode rtc syscopy xm
+ROMAPPS2 := fdu format survey sysgen talk cpuspd
 
 rom128_%.dat: DISKDEF=wbw_rom128
 rom256_%.dat: DISKDEF=wbw_rom256
diff --git a/Source/RomDsk/ROM_384KB/timer.com b/Source/RomDsk/ROM_384KB/timer.com
new file mode 100644
index 0000000000000000000000000000000000000000..be41c75462b188160ebcd9eb823ca398e549e809
GIT binary patch
literal 900
zcmbtRUr19?96t9rXAQO(72FcWFD5x-Zf+vfkgGV#q%uim4<d5iZhC3%+T9<VBcX?S
z?kNg-jvj<P1PzKr9fij@%{{2|(O^M=)E-<BdT-}Ck*LRhaKCeY-#NeU`#5(ezJ+~_
zb@U7e_0-P+qEGQoW(yOx+8N(~=_^j-mRGRQ@tR?loV$<cbG&+m)4a>`9DTwq^55uV
zZ2oCmD+Ee7Cm??bgE_E)-@2Ob`8P1tIqJoB)x^Zutzv<7f`@+P()1LzXAC;9iE}QC
z&Fs)=J<7RWW{Gnyx1zy{*0nm%X~ESjm(Sz;0<P-*P0W7^?CV+{PG8XUIc*=T&N;0N
z4csqNLBNEOLTCYOPT|D@95YvJs3348OWv)Q$84DCZx@%y?m>VGTdgceg{+^=xy)>L
zlCKuY?mF$nv#iUougEUVu%JfR3KLnPO}K2p5(&|3cx<+T72AZ!=M(QAHGk}GCgt-;
zp`&=4>@rU(V`f+(jyCRli9W;}zh~exouRGDz=3SK;O#tqac`&R&58ptPvh}x$pi~)
zE9BrY7M=VLO)P1dwGUbHKv`=dU+m*`yv5#V;_L0*CLXchz#g-z6NGg1-!;^C<MJ&?
z`8+;1_}W_gl~k+0&3DOa2`bZRRi2nkfGgMn2Iq#5n2t#d)x@L}b3<?cF!T;whg3Tn
zj*Amg0BUL@-ry*Vc)Lce7656+b4bHcxgv6WIx40ioK#gQmVksjC8>}Sqe-d77&5A+
z<?X6<07pY9NsY@&48&Ljl7{c!Bf)=0{?Lc85=+Rjq>_wB(=BK~RK+PN!Q3TPRa9^t
z+1_SdO&;~d!phXNn2^V#67=-l90YcD7{d)$513TDrvp^!Zc<jI2!bIwd?)S(1cMSY
HjKtAzv0y}K

literal 0
HcmV?d00001


From 9bc4f26f6e3a24cbd52486f6366529f1721e1bbb Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 8 Jul 2024 16:36:06 +1000
Subject: [PATCH 19/62] timer.com: added new switch (/R) to reset current timer
 ticks

---
 Source/Apps/timer.asm | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/Source/Apps/timer.asm b/Source/Apps/timer.asm
index b220db1a..7c68a075 100644
--- a/Source/Apps/timer.asm
+++ b/Source/Apps/timer.asm
@@ -186,6 +186,8 @@ option:
 	jp	z,usage		; yes, display usage
 	cp	'C'		; is it a 'C', continuous?
 	jp	z,setcont	; yes, set continuous display
+	cp	'R'
+	jp	z,reset		; reset timer
 	jp	errprm		; anything else is an error
 ;
 usage:
@@ -197,6 +199,30 @@ setcont:
 	or	$FF		; set A to true
 	ld	(cont),a	; and set continuous flag
 	jr	option		; check for more option letters
+
+reset:
+	; Test of API function to set seconds value
+	push	bc
+	push	hl
+	push	de
+	push	af
+	ld	b,bf_sysset	; HBIOS SYSGET function
+	ld	c,bf_syssettimer; SECONDS subfunction
+	ld	de,0		; set seconds value
+	ld	hl,0		; ... to 1000
+	rst	08		; call HBIOS, DE:HL := seconds value
+
+	ld	b,bf_sysset	; HBIOS SYSGET function
+	ld	c,bf_syssetsecs	; SECONDS subfunction
+	ld	de,0		; set seconds value
+	ld	hl,0		; ... to 1000
+	rst	08		; call HBIOS, DE:HL := seconds value
+
+	pop	af
+	pop	de
+	pop	hl
+	pop	bc
+	jr	option
 ;
 ; Identify active BIOS.  RomWBW HBIOS=1, UNA UBIOS=2, else 0
 ;
@@ -491,12 +517,13 @@ stack	.equ	$		; stack top
 ;
 ; Messages
 ;
-msgban	.db	"TIMER v1.1, 10-Nov-2019",13,10
+msgban	.db	"TIMER v1.2, 10-Nov-2019",13,10
 	.db	"Copyright (C) 2019, Wayne Warthen, GNU GPL v3",0
 msguse	.db	"Usage: TIMER [/C] [/?]",13,10
 	.db	"  ex. TIMER           (display current timer value)",13,10
 	.db	"      TIMER /?        (display version and usage)",13,10
-	.db	"      TIMER /C        (display timer value continuously)",0
+	.db	"      TIMER /C        (display timer value continuously)",13,10
+	.db	"      TIMER /R        (reset timer values to 0)",0
 msgprm	.db	"Parameter error (TIMER /? for usage)",0
 msgbio	.db	"Incompatible BIOS or version, "
 	.db	"HBIOS v", '0' + rmj, ".", '0' + rmn, " required",0

From cb7ba38f76610642179aa369f8d48724d16d8b95 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 12 Jul 2024 10:08:11 +1000
Subject: [PATCH 20/62] ez80uart: defer basic i/o operations to ez80 firmware

---
 Source/HBIOS/ez80uart.asm | 32 ++++++++++++--------------------
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index 28af82f7..8f88003c 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -43,36 +43,28 @@ EZUART_INIT:
 
 ; RETRIEVE THE NEXT CHARACTER FROM THE UART AND RETURN IN E
 EZUART_IN:
-	IN0_A	(UART0_LSR)		; CHECK FOR RX READY
-	AND	LSR_DR
-	JR	Z, EZUART_IN
-	
-	IN0_E	(UART0_RBR)		; GET THE CHAR
-
-	XOR	A			; SIGNAL SUCCESS
+	LD	A, 3			; UART
+	LD	B, 0			; UART-IN
+	EZ80_FN				; CHAR RETURNED IN E
 	RET
 	
 ; OUT CHAR IN E
 EZUART_OUT:
-	IN0_A	(UART0_LSR)		; WAIT FOR TX READY
-	AND	LSR_THRE
-	JR	Z, EZUART_OUT
-     
-	OUT0_E	(UART0_THR)		; SEND THE CHAR
-
-	XOR	A			; SIGNAL SUCCESS
+	LD	A, 3			; UART
+	LD	B, 1			; UART-OUT
+	EZ80_FN
 	RET
 
 EZUART_IST:
-	IN0_A	(UART0_LSR)		; CHECK FOR RX READY
-	AND	LSR_DR
+	LD	A, 3			; UART
+	LD	B, 2			; UART-IST
+	EZ80_FN
 	RET
 
 EZUART_OST:
-	IN0_A	(UART0_LSR)		; WAIT FOR TX READY
-	AND	LSR_THRE
-	RET	Z
-	LD	A, 1
+	LD	A, 3			; UART
+	LD	B, 3			; UART-OST
+	EZ80_FN
 	RET
 
 EZUART_INITDEV:

From 229bf119d4184deff2f67a23a0824d18955f0471 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 12 Jul 2024 14:42:25 +1000
Subject: [PATCH 21/62] ez80: uart query implemented

---
 Source/HBIOS/ez80instr.inc        |  50 +++++++++++++
 Source/HBIOS/ez80uart.asm         | 119 +++++++++++++++++++++++++-----
 Source/HBIOS/hbios.asm            |  13 +---
 Source/RomDsk/ROM_384KB/timer.com | Bin 900 -> 937 bytes
 4 files changed, 153 insertions(+), 29 deletions(-)
 create mode 100644 Source/HBIOS/ez80instr.inc

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
new file mode 100644
index 00000000..dbb4ed8f
--- /dev/null
+++ b/Source/HBIOS/ez80instr.inc
@@ -0,0 +1,50 @@
+;
+;==================================================================================================
+;   HELPER MACROS FOR TARGETING EZ80 CPU INSTRUCTIONS
+;==================================================================================================
+
+;
+; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
+;
+#IF (CPUFAM == CPU_EZ80)
+  #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
+  #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
+  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
+
+  #DEFINE RET.L		.DB	$49 \ RET
+
+  #DEFINE IN0_A(p)	.DB	$ED,$38,p
+  #DEFINE IN0_B(p)	.DB	$ED,$00,p
+  #DEFINE IN0_C(p)	.DB	$ED,$08,p
+  #DEFINE IN0_D(p)	.DB	$ED,$10,p
+  #DEFINE IN0_E(p)	.DB	$ED,$18,p
+  #DEFINE IN0_H(p)	.DB	$ED,$20,p
+  #DEFINE IN0_L(p)	.DB	$ED,$28,p
+
+  #DEFINE OUT0_A(p)	.DB	$ED,$39,p
+  #DEFINE OUT0_B(p)	.DB	$ED,$01,p
+  #DEFINE OUT0_C(p)	.DB	$ED,$09,p
+  #DEFINE OUT0_D(p)	.DB	$ED,$11,p
+  #DEFINE OUT0_E(p)	.DB	$ED,$19,p
+  #DEFINE OUT0_H(p)	.DB	$ED,$21,p
+  #DEFINE OUT0_L(p)	.DB	$ED,$29,p
+
+  #DEFINE LDHLMM.LIL(Mmn)	\
+  #defcont \	.DB	$5B
+  #defcont \	LD	HL, Mmn
+  #defcont \	.DB	(Mmn >> 16) & $FF
+
+  #DEFINE LDBCMM.LIL(Mmn)	\
+  #defcont \	.DB	$5B
+  #defcont \	LD	BC, Mmn
+  #defcont \	.DB	(Mmn >> 16) & $FF
+
+  #DEFINE SBCHLBC.LIL \
+  #defcont \	.DB	$49
+  #defcont \	SBC	HL, BC
+
+IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
+
+#ELSE
+  #DEFINE EZ80_IO
+#ENDIF
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index 8f88003c..cbe0e74e 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -11,22 +11,6 @@ UART0_RBR	.EQU	$C0
 LSR_THRE	.EQU	$20
 LSR_DR		.EQU	$01
 
-#DEFINE IN0_A(p)	.DB	$ED,$38,p
-#DEFINE IN0_B(p)	.DB	$ED,$00,p
-#DEFINE IN0_C(p)	.DB	$ED,$08,p
-#DEFINE IN0_D(p)	.DB	$ED,$10,p
-#DEFINE IN0_E(p)	.DB	$ED,$18,p
-#DEFINE IN0_H(p)	.DB	$ED,$20,p
-#DEFINE IN0_L(p)	.DB	$ED,$28,p
-
-#DEFINE OUT0_A(p)	.DB	$ED,$39,p
-#DEFINE OUT0_B(p)	.DB	$ED,$01,p
-#DEFINE OUT0_C(p)	.DB	$ED,$09,p
-#DEFINE OUT0_D(p)	.DB	$ED,$11,p
-#DEFINE OUT0_E(p)	.DB	$ED,$19,p
-#DEFINE OUT0_H(p)	.DB	$ED,$21,p
-#DEFINE OUT0_L(p)	.DB	$ED,$29,p
-
 EZUART_PREINIT:
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
@@ -67,9 +51,110 @@ EZUART_OST:
 	EZ80_FN
 	RET
 
+BAUD_RATE	.EQU	115200
+
 EZUART_INITDEV:
+	LD	A, 3			; UART
+	LD	B, 4			; UART-CONFIG
+	LDHLMM.LIL(BAUD_RATE)
+
+	LD	E, 3 << 3
+	EZ80_FN
+	RET
+
+
+#DEFINE	TRANSLATE(nnn,rrr) \
+#defcont \		LDBCMM.LIL(nnn)
+#defcont \		SBCHLBC.LIL
+#defcont \		JR	NC, $+7
+#defcont \		LD	D, rrr
+#defcont \		JP	uart_query_end
+
 EZUART_QUERY:
-	LD	A, 0			; NOT IMPLEMENTED ERROR
+	LD	A, 3			; UART
+	LD	B, 5			; UART-QUERY
+	EZ80_FN
+
+	OR	A
+	; HL24 bit has the baud rate, we need to convert to the 5 bit representation?
+	TRANSLATE(112, 			00000b)	; BAUDRATE=75 (BETWEEN 0 AND 112)
+	TRANSLATE(187-112, 		00001b)	; BAUDRATE=150 (BETWEEN 113 AND 187)
+	TRANSLATE(262-187, 		10000b)	; BAUDRATE=225 (BETWEEN 188 AND 262)
+	TRANSLATE(375-262, 		00010b)	; BAUDRATE=300 (BETWEEN 263 AND 375)
+	TRANSLATE(525-375, 		10001b)	; BAUDRATE=450 (BETWEEN 376 AND 525)
+	TRANSLATE(750-525, 		00011b)	; BAUDRATE=600 (BETWEEN 526 AND 750)
+	TRANSLATE(1050-750, 		10010b)	; BAUDRATE=900 (BETWEEN 751 AND 1050)
+	TRANSLATE(1500-1050, 		00100b)	; BAUDRATE=1200 (BETWEEN 1051 AND 1500)
+	TRANSLATE(2100-1500, 		10011b)	; BAUDRATE=1800 (BETWEEN 1501 AND 2100)
+	TRANSLATE(3000-2100, 		00101b)	; BAUDRATE=2400 (BETWEEN 2101 AND 3000)
+	TRANSLATE(4200-3000, 		10100b)	; BAUDRATE=3600 (BETWEEN 3001 AND 4200)
+	TRANSLATE(6000-4200, 		00110b)	; BAUDRATE=4800 (BETWEEN 4201 AND 6000)
+	TRANSLATE(8400-6000, 		10101b)	; BAUDRATE=7200 (BETWEEN 6001 AND 8400)
+	TRANSLATE(12000-8400, 		00111b)	; BAUDRATE=9600 (BETWEEN 8401 AND 12000)
+	TRANSLATE(16800-12000, 		10110b)	; BAUDRATE=14400 (BETWEEN 12001 AND 16800)
+	TRANSLATE(24000-16800, 		01000b)	; BAUDRATE=19200 (BETWEEN 16801 AND 24000)
+	TRANSLATE(33600-24000, 		10111b)	; BAUDRATE=28800 (BETWEEN 24001 AND 33600)
+	TRANSLATE(48000-33600, 		01001b)	; BAUDRATE=38400 (BETWEEN 33601 AND 48000)
+	TRANSLATE(67200-48000, 		11000b)	; BAUDRATE=57600 (BETWEEN 48001 AND 67200)
+	TRANSLATE(96000-67200, 		01010b)	; BAUDRATE=76800 (BETWEEN 67201 AND 96000)
+	TRANSLATE(134400-96000, 	11001b)	; BAUDRATE=115200 (BETWEEN 96001 AND 134400)
+	TRANSLATE(192000-134400, 	01011b)	; BAUDRATE=153600 (BETWEEN 134401 AND 192000)
+	TRANSLATE(268800-192000, 	11010b)	; BAUDRATE=230400 (BETWEEN 192001 AND 268800)
+	TRANSLATE(384000-268800, 	01100b)	; BAUDRATE=307200 (BETWEEN 268801 AND 384000)
+	TRANSLATE(537600-384000, 	11011b)	; BAUDRATE=460800 (BETWEEN 384001 AND 537600)
+	TRANSLATE(768000-537600, 	01101b)	; BAUDRATE=614400 (BETWEEN 537601 AND 768000)
+	TRANSLATE(1075200-768000,	11100b)	; BAUDRATE=921600 (BETWEEN 768001 AND 1075200)
+	TRANSLATE(1536000-1075200,	01110b)	; BAUDRATE=1228800 (BETWEEN 1075201 AND 1536000)
+	TRANSLATE(2150400-1536000,	11101b)	; BAUDRATE=1843200 (BETWEEN 1536001 AND 2150400)
+	TRANSLATE(3072000-2150400,	01111b)	; BAUDRATE=2457600 (BETWEEN 2150401 AND 3072000)
+	TRANSLATE(5529600-3072000,	11110b)	; BAUDRATE=3686400 (BETWEEN 3072001 AND 5529600)
+
+	LD	D, 11111b				; BAUDRATE=7372800 (>=5529601)
+uart_query_end:
+
+; Convert from line control settings from:
+;
+;     E{0:1} = Parity    (00 -> NONE, 01 -> NONE, 10 -> ODD, 11 -> EVEN)
+;     E{2}   = Stop Bits (0 -> 1, 1 -> 2)
+;     E{3:4} = Data Bits (00 -> 5, 01 -> 6, 10 -> 7, 11 -> 8)
+;     E{5:5} = Hardware Flow Control CTS (0 -> OFF, 1 -> ON)
+;
+; to
+;
+;     E{7}   = TODO: DTR
+;     E{6}   = NOT IMPLEMENTED: XON/XOFF Flow Control
+;     E{5}   = NOT SUPPORTED: Stick Parity (set for true)
+;     E{4}   = Even Parity (set for true)
+;     E{3}   = Parity Enable (set for true)
+;     E{2}   = Stop Bits (set for true)
+;     E{1:0} = Data Bits (5-8 encoded as 0-3)
+
+	XOR	A
+	OR	3 << 3		; ISOLATE DATA BITS
+	AND	E		; MASK IN DATA BITS
+
+	RRCA			; SHIFT TO BITS 1:0
+	RRCA
+	RRCA
+	LD	H, A		; H{1:0} DATA BITS
+
+	BIT	2, E		; STOP BITS
+	JR	Z, SKIP1
+	SET	2, H		; APPLY TO H
+
+SKIP1:
+	BIT	0, E		; PARITY ENABLE
+	JR	Z, SKIP2
+	SET	3, H		; APPLY TO H
+
+SKIP2:
+	BIT	1, E		; EVEN PARITY
+	JR	Z, SKIP3
+	SET	4, H		; APPLY TO H
+
+SKIP3:
+	LD	E, H
+	XOR	A
 	RET
 
 EZUART_DEVICE:
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 9d22a730..bacf8616 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -350,20 +350,9 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
   #ENDIF
 	DEVECHO	"\n"
 #ENDIF
-;
-; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
-;
-#IF (CPUFAM == CPU_EZ80)
-  #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
-  #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
-  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 
-  #DEFINE RET.L		.DB	$49 \ RET
-IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
+#include "ez80instr.inc"
 
-#ELSE
-  #DEFINE EZ80_IO
-#ENDIF
 ;
 ;==================================================================================================
 ; Z80 PAGE ZERO, VECTORS, ETC.
diff --git a/Source/RomDsk/ROM_384KB/timer.com b/Source/RomDsk/ROM_384KB/timer.com
index be41c75462b188160ebcd9eb823ca398e549e809..8c39f2ffdba8a94794391aee9906a377cf8497fb 100644
GIT binary patch
delta 465
zcmXX?K}Z`x6rK4d8x3^B;$><fM3g3nQZ-P}P}X2+p;r;S2;#v*PYPbFp%ul_TTwjN
zg9oq0LlBD#28&TrGLdhxhXtYZ5F|wpLHCeoG0ygH+ktuiz0YI*pSKeF5?ZX!DHuq%
z;X@t^Vv@%geuH{Ofuw3s{|Vp^uJ}<M%xC+AS=qhB@B~V)xavFF;rN*!iYv^4cB@y)
zse7<Ymb{0Umb!z3MEqUy4zL$+42+EcJw`6OOv-$U5qOJ36JTul{ZtFAL|E6N9tN3}
z*v-nG_f}EGifXvD!_|w@SFT1&IevTr$LG-Wk}VKF3pJ;q{njf6W8I9EiQ50EYghB)
zU~TW^Vgy{-Fdxt~S2|r*LL=5Gnzn2>I0Xx&GIVV+&Et^25%~&E9$!PvhrAreS(sc1
z(IGM}e?`8p#!u66S$oW8a2cwyQE+Pb395G9mC=5FeTLh>Ma#!cZ<31MB#1KIGy9%*
z47Tbcxnh*jP(R{-tC?YvuKfGs!ya*?rp{ERa*~xFW-7h%()idW!bUnEg2r?}FbbOz
VYkHC~Z@tP>>({(}_Yu6|e*kv~&=>#!

delta 402
zcmX9)O-lk{5PoO;A|Yd`!<HaMk<uYch(c_QqAvXaPZ4wrf}k#?lmyYa2%?~K5Ck5C
z7K$Ph!&jKhgJyIputOl_LFpj7jWjUN%riX9*M(!xk*ICF;+We)z2LP`5WIp;u@-+t
z$x-3D1L+D3c*vnPe$AMa{kwwBF+UGR;NcSJ1n$*uI!61i>$woBpstBv1-<rA8E^f*
z?O++n1PY+CZslgIDi)Y&BlHDZ)H8ufyj>5ypze3N>>iVBLieYVa$rZ#8Qz=`$zOso
zn@>U}gPA*Qn!y)TKMvpK5?@f44Xu+K)n%zq_uDz^R+~lHC{Y+=%;M}t7Hv`w@-VE+
zY$;8HSZzaEMri?;Vh%P=qVlur@xb>q?UU6Zu||vdE*sfWl~(Y*n669DDEw4tA3<%k
z@ys0N;A%2>gv-<d;f~2xZRRHD5j?d0z5mrTC(|Pd?!IM<>QvlT)uv2aRly(Qvzw+A
N!aM?uq^58c{s7<>uaf`(


From aeb579d6ad46a829006fbb9509334a94973b84be Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 13 Jul 2024 12:29:45 +1000
Subject: [PATCH 22/62] ez80: uart init implemented

---
 Source/HBIOS/ez80uart.asm | 204 +++++++++++++++++++++++++++++++++-----
 1 file changed, 180 insertions(+), 24 deletions(-)

diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index cbe0e74e..9f9e8465 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -3,6 +3,29 @@
 ; eZ80 UART DRIVER (SERIAL PORT)
 ;==================================================================================================
 ;
+;
+; Supported Line Characteristics are encoded as follows in the DE register pair:
+;
+; | **Bits** | **Characteristic**                     |
+; |---------:|----------------------------------------|
+; | 15-14    | Reserved (set to 0)                    |
+; | 13       | RTS (Not implemented)                  |
+; | 12-8     | Baud Rate* (see below)                 |
+; | 7        | DTR (Not implemented)                  |
+; | 6        | XON/XOFF Flow Control (not implemented)|
+; | 5        | Stick Parity (not implemented)         |
+; | 4        | Even Parity (set for true)             |
+; | 3        | Parity Enable (set for true)           |
+; | 2        | Stop Bits (0-> 1 BIT, 1-> 2 BITS)      |
+; | 1-0      | Data Bits (5-8 encoded as 0-3)         |
+;
+; * The 5-bit Baud Rate value (V) is encoded as V = 75 * 2^X * 3^Y. The
+; bits are defined as YXXXX.
+;
+; STICK & EVEN & PARITY -> MARK PARITY -> NOT SUPPORTED
+; STICK & !EVEN & PARITY -> SPACE PARITY -> NOT SUPPORTED
+; THEREFORE, MARK PARITY WILL BE INTERPRETED AS EVEN PARITY
+; AND SPACE PARITY WILL BE INTERPRETED AS ODD PARITY
 
 UART0_LSR	.EQU	$C5
 UART0_THR	.EQU	$C0
@@ -11,6 +34,7 @@ UART0_RBR	.EQU	$C0
 LSR_THRE	.EQU	$20
 LSR_DR		.EQU	$01
 
+
 EZUART_PREINIT:
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
@@ -23,28 +47,69 @@ EZUART_PREINIT:
 EZUART_INIT:
 	XOR	A
 	RET
-
-
-; RETRIEVE THE NEXT CHARACTER FROM THE UART AND RETURN IN E
+;
+; ### Function 0x00 -- Character Input (CIOIN)
+;
+; Read and return a Character (E).  If no character(s) are available in the
+; input buffer, this function will wait indefinitely.  The returned Status
+; (A) is a standard HBIOS result code.
+;
+; Outputs:
+;  E: Character
+;  A: Status (0-OK, else error)
+;
 EZUART_IN:
 	LD	A, 3			; UART
 	LD	B, 0			; UART-IN
 	EZ80_FN				; CHAR RETURNED IN E
 	RET
-	
-; OUT CHAR IN E
+;
+; ### Function 0x01 -- Character Output (CIOOUT)
+;
+; Send the Character (E).  If there is no space available in the unit's output
+; buffer, the function will wait indefinitely.  The returned Status (A) is a
+; standard HBIOS result code.
+;
+; Inputs:
+;  E: Character
+;
+; Outputs:
+;  A: Status (0-OK, else error)
+;
 EZUART_OUT:
 	LD	A, 3			; UART
 	LD	B, 1			; UART-OUT
 	EZ80_FN
 	RET
-
+;
+; ### Function 0x02 -- Character Input Status (CIOIST)
+;
+; Return the count of Characters Pending (A) in the input buffer.
+;
+; The value returned in register A is used as both a Status (A) code and
+; the return value. Negative values (bit 7 set) indicate a standard HBIOS
+; result (error) code.  Otherwise, the return value represents the number
+; of characters in the input buffer.
+;
+; Outputs:
+;  A: Status / Characters Pending
+;
 EZUART_IST:
 	LD	A, 3			; UART
 	LD	B, 2			; UART-IST
 	EZ80_FN
 	RET
-
+;
+; ### Function 0x03 -- Character Output Status (CIOOST)
+;
+; Return the status of the output FIFO.  0 means the output FIFO is full and
+; no more characters can be sent. 1 means the output FIFO is not full and at
+; least one character can be sent.  Negative values (bit 7 set) indicate a
+; standard HBIOS result (error) code.
+;
+; Outputs
+;   A: Status (0 -> Full, 1 -> OK to send, < 0 -> HBIOS error code)
+;
 EZUART_OST:
 	LD	A, 3			; UART
 	LD	B, 3			; UART-OST
@@ -52,16 +117,76 @@ EZUART_OST:
 	RET
 
 BAUD_RATE	.EQU	115200
-
+;
+; ### Function 0x04 -- Character I/O Initialization (CIOINIT)
+;
+; Apply the requested line Characteristics in (DE). The definition of the
+; line characteristics value is described above.  If DE contains -1 (0xFFFF),
+; then the input and output buffers will be flushed and reset.
+; The Status (A) is a standard HBIOS result code.
+;
+; Inputs:
+;   DE: Line Characteristics
+;
+; Outputs:
+;   A: Status (0-OK, else error)
+;
 EZUART_INITDEV:
-	LD	A, 3			; UART
-	LD	B, 4			; UART-CONFIG
-	LDHLMM.LIL(BAUD_RATE)
+	LD	A, D
+	CP	E
+	JR	NZ, NOT_RESET
+	CP	$FF
+	JR	NZ, NOT_RESET
 
-	LD	E, 3 << 3
+	; reset requested
+	LD	A, 3			; UART
+	LD	B, 6			; UART-RESET
 	EZ80_FN
 	RET
 
+NOT_RESET:
+	PUSH	DE			; SAVE LINE CHARACTERISTICS
+	LD	A, D
+	AND	$1F			; ISOLATE ENCODED BAUD RATE
+	LD	L, A			; PUT IN L
+	LD	H, 0			; H IS ALWAYS ZERO
+	LD	DE, 75			; BAUD RATE DECODE CONSTANT
+	CALL	DECODE			; DE:HL := BAUD RATE
+
+	;; convert E:HL{15:0} to HL{23:0}
+	LD	A, 0
+	LD	B, 1			; UTIL - LD HL, E:HL
+	EZ80_FN				;
+
+	POP	DE			; RESTORE REQUESTED LINE CHARACTERISTICS
+	LD	A, E
+	AND	3			; MASK FOR DATA BITS
+	RLCA
+	RLCA
+	RLCA				; SHIFT TO BITS 4:3
+	LD	D, A			; SAVE INTO D
+
+	BIT	2, E			; STOP BITS (1 OR 2)
+	JR	Z, ISKIP1
+	SET	2, D			; APPLY TO D
+ISKIP1:
+
+	BIT	3, E			; PARITY ENABLE
+	JR	Z, ISKIP2
+	SET	1, D			; APPLY TO D
+ISKIP2:
+
+	BIT	4, E			; EVEN PARITY
+	JR	Z, ISKIP3
+	SET	0, D			; APPLY TO D
+ISKIP3:
+
+	; D NOW CONTAINS THE LINE CONTROL BITS AS PER EZ80 FUNCTION
+
+	LD	A, 3			; UART
+	LD	B, 4			; UART-CONFIG
+	EZ80_FN
+	RET
 
 #DEFINE	TRANSLATE(nnn,rrr) \
 #defcont \		LDBCMM.LIL(nnn)
@@ -69,11 +194,27 @@ EZUART_INITDEV:
 #defcont \		JR	NC, $+7
 #defcont \		LD	D, rrr
 #defcont \		JP	uart_query_end
-
+;
+; ### Function 0x05 -- Character I/O Query (CIOQUERY)
+;
+; Returns the current Line Characteristics (DE). The definition of the line
+; characteristics value is described above. The returned status (A) is a
+; standard HBIOS result code.
+;
+; As the eZ80 UART driver supports more than the defined HBIOS baud rates, the
+; returned baud rate may be an approximation of the actual baud rate.
+;
+; Outputs:
+;  DE: Line Characteristics
+;  A: Status (0-OK, else error)
+;
 EZUART_QUERY:
 	LD	A, 3			; UART
 	LD	B, 5			; UART-QUERY
-	EZ80_FN
+	EZ80_FN		
+					; HL{23:0} := BAUD RATE
+					; D = LINE CONTROL BITS
+	PUSH	DE			; SAVE D
 
 	OR	A
 	; HL24 bit has the baud rate, we need to convert to the 5 bit representation?
@@ -109,15 +250,17 @@ EZUART_QUERY:
 	TRANSLATE(3072000-2150400,	01111b)	; BAUDRATE=2457600 (BETWEEN 2150401 AND 3072000)
 	TRANSLATE(5529600-3072000,	11110b)	; BAUDRATE=3686400 (BETWEEN 3072001 AND 5529600)
 
-	LD	D, 11111b				; BAUDRATE=7372800 (>=5529601)
+	LD	D, 11111b			; BAUDRATE=7372800 (>=5529601)
 uart_query_end:
 
+	POP	BC				; B = LINE CONTROL BITS
+
 ; Convert from line control settings from:
 ;
-;     E{0:1} = Parity    (00 -> NONE, 01 -> NONE, 10 -> ODD, 11 -> EVEN)
-;     E{2}   = Stop Bits (0 -> 1, 1 -> 2)
-;     E{3:4} = Data Bits (00 -> 5, 01 -> 6, 10 -> 7, 11 -> 8)
-;     E{5:5} = Hardware Flow Control CTS (0 -> OFF, 1 -> ON)
+;     B{0:1} = Parity    (00 -> NONE, 01 -> NONE, 10 -> ODD, 11 -> EVEN)
+;     B{2}   = Stop Bits (0 -> 1, 1 -> 2)
+;     B{3:4} = Data Bits (00 -> 5, 01 -> 6, 10 -> 7, 11 -> 8)
+;     B{5:5} = Hardware Flow Control CTS (0 -> OFF, 1 -> ON)
 ;
 ; to
 ;
@@ -131,24 +274,24 @@ uart_query_end:
 
 	XOR	A
 	OR	3 << 3		; ISOLATE DATA BITS
-	AND	E		; MASK IN DATA BITS
+	AND	B		; MASK IN DATA BITS
 
 	RRCA			; SHIFT TO BITS 1:0
 	RRCA
 	RRCA
 	LD	H, A		; H{1:0} DATA BITS
 
-	BIT	2, E		; STOP BITS
+	BIT	2, B		; STOP BITS
 	JR	Z, SKIP1
 	SET	2, H		; APPLY TO H
 
 SKIP1:
-	BIT	0, E		; PARITY ENABLE
+	BIT	1, B		; PARITY ENABLE
 	JR	Z, SKIP2
 	SET	3, H		; APPLY TO H
 
 SKIP2:
-	BIT	1, E		; EVEN PARITY
+	BIT	0, B		; EVEN PARITY
 	JR	Z, SKIP3
 	SET	4, H		; APPLY TO H
 
@@ -156,7 +299,20 @@ SKIP3:
 	LD	E, H
 	XOR	A
 	RET
-
+;
+; ### Function 0x06 -- Character I/O Device (CIODEVICE)
+;
+; Returns device information.  The status (A) is a standard HBIOS result
+; code.
+;
+; Outputs
+;  A: Status (0 - OK)
+;  C: Device Attribute (0 - RS/232)
+;  D: Device Type (CIODEV_EZ80UART)
+;  E: Physical Device Number
+;  H: Device Mode (0)
+;  L: Device I/O Base Address - Not Supported (0)
+;
 EZUART_DEVICE:
 	LD	D, CIODEV_EZ80UART	; D := DEVICE TYPE
 	LD	E, (IY)			; E := PHYSICAL UNIT

From 37b3b96e491faf8b3e06f6136d4aafa490133e56 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 14 Jul 2024 15:18:58 +1000
Subject: [PATCH 23/62] ez80: rtc fix missing space in boot report

---
 Source/HBIOS/ez80rtc.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index ff6e105c..7909b4a8 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -20,7 +20,7 @@ EZ80RTC_INIT:
 	RET	NZ			; IF ALREADY ACTIVE, ABORT
 
 	CALL	NEWLINE			; FORMATTING
-	PRTS("EZ80 RTC: ON-CHIP$")
+	PRTS("EZ80 RTC: ON-CHIP $")
 
 	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
 	LD	B, 0			; RTC INIT FUNCTION

From bc68674ce26fb83e92a509e83e661e51982c5610 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 14 Jul 2024 15:21:18 +1000
Subject: [PATCH 24/62] ez80: updated ch.asm driver to support ez80

SD Card not supported yet
---
 Source/HBIOS/cfg_rcez80.asm | 14 +++++++-------
 Source/HBIOS/ch.asm         |  4 ++++
 Source/HBIOS/chsd.asm       |  2 ++
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 3cd7910b..900bde81 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -262,16 +262,16 @@ SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	2		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	2		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	2		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$88		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
diff --git a/Source/HBIOS/ch.asm b/Source/HBIOS/ch.asm
index 0bfb877d..b7f52caa 100644
--- a/Source/HBIOS/ch.asm
+++ b/Source/HBIOS/ch.asm
@@ -236,6 +236,7 @@ CH_INIT4:
 CH_CMD:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
 	INC	C			; BUMP TO CMD PORT
+	EZ80_IO
 	OUT	(C),A			; SEND COMMAND
 	CALL	CH_NAP			; *DEBUG*
 	RET
@@ -245,6 +246,7 @@ CH_CMD:
 CH_STAT:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
 	INC	C			; BUMP TO CMD PORT
+	EZ80_IO
 	IN	A,(C)			; READ STATUS
 	RET
 ;
@@ -252,6 +254,7 @@ CH_STAT:
 ;
 CH_RD:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	IN	A,(C)			; READ BYTE
 	RET
 ;
@@ -259,6 +262,7 @@ CH_RD:
 ;
 CH_WR:
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	OUT	(C),A			; READ BYTE
 	RET
 ;
diff --git a/Source/HBIOS/chsd.asm b/Source/HBIOS/chsd.asm
index c4b38194..e1a7e81d 100644
--- a/Source/HBIOS/chsd.asm
+++ b/Source/HBIOS/chsd.asm
@@ -196,6 +196,7 @@ CHSD_READ1:
 #IF (CHSD_FASTIO)
 	LD	B,A			; BYTE COUNT TO READ
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO ;!! NOT SUPPORT INIR YET
 	INIR				; DO IT FAST
 #ELSE
 	LD	B,A			; SAVE IT
@@ -263,6 +264,7 @@ CHSD_WRITE1:
 #IF (CHSD_FASTIO)
 	LD	B,A			; BYTE COUNT TO WRITE
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO ;!! NOT SUPPORT OTIR YET
 	OTIR				; DO IT FAST
 #ELSE
 	LD	B,A			; SAVE IT

From ba8cd05cb7a19af28c3d77a35f9277ddde9cd18a Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Tue, 16 Jul 2024 16:52:45 +1000
Subject: [PATCH 25/62] ez80: 60hz timer updated to support native 24 bit tick
 counters implemented in firmware

---
 Source/HBIOS/ez80uart.asm |  2 +-
 Source/HBIOS/hbios.asm    | 21 +++++++++++++++------
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index 9f9e8465..c91873aa 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -156,7 +156,7 @@ NOT_RESET:
 	;; convert E:HL{15:0} to HL{23:0}
 	LD	A, 0
 	LD	B, 1			; UTIL - LD HL, E:HL
-	EZ80_FN				;
+	EZ80_FN
 
 	POP	DE			; RESTORE REQUESTED LINE CHARACTERISTICS
 	LD	A, E
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index bacf8616..3d19bfa1 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -5049,7 +5049,7 @@ SYS_GETFN:
 SYS_GETTIMER:
 #IF (CPUFAM == CPU_EZ80)
 	LD	A, 2
-	LD	B, 0	; GET TIMER TICK
+	LD	B, 0			; GET TIMER TICK
 	EZ80_FN
 	RET
 
@@ -5072,7 +5072,7 @@ SYS_GETTIMER:
 SYS_GETSECS:
 #IF (CPUFAM == CPU_EZ80)
 	LD	A, 2
-	LD	B, 1	; GET SECOND TICK
+	LD	B, 1			; GET SECOND TICK
 	EZ80_FN
 	RET
 
@@ -5082,7 +5082,7 @@ SYS_GETSECS:
 	CALL	LD32
 	LD	A,(HB_SECTCK)
 	HB_EI
-	NEG			; CONVERT DOWNCOUNTER TO UPCOUNTER
+	NEG				; CONVERT DOWNCOUNTER TO UPCOUNTER
 	ADD	A,TICKFREQ
 	LD	C,A
 	XOR	A
@@ -5296,8 +5296,13 @@ SYS_SETBOOTINFO:
 ;
 SYS_SETTIMER:
 #IF (CPUFAM == CPU_EZ80)
-	LD	A, 2
-	LD	B, 2	; SET TICKS
+	;; convert E:HL{15:0} to HL{23:0}
+	LD	A, 0
+	LD	B, 1			; UTIL - LD HL, E:HL
+	EZ80_FN
+
+	LD	A, 2		
+	LD	B, 2			; SET TICKS
 	EZ80_FN
 	RET
 #ELSE
@@ -5315,8 +5320,12 @@ SYS_SETTIMER:
 ;
 SYS_SETSECS:
 #IF (CPUFAM == CPU_EZ80)
+	LD	A, 0
+	LD	B, 1			; UTIL - LD HL, E:HL
+	EZ80_FN
+
 	LD	A, 2
-	LD	B, 3	; SET SECS
+	LD	B, 3			; SET SECS
 	EZ80_FN
 	RET
 #ELSE

From 37a7574f1f3613d8746005e8e90abb8db9eab437 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Tue, 16 Jul 2024 17:02:53 +1000
Subject: [PATCH 26/62] ez80: report if RTC is not powered

---
 Source/HBIOS/ez80rtc.asm | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index 7909b4a8..1adaac44 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -25,8 +25,14 @@ EZ80RTC_INIT:
 	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
 	LD	B, 0			; RTC INIT FUNCTION
 	EZ80_FN	
-	; TODO VERIFY SUCCESS -> A IS ZERO
+	JR	Z, RTC_POWERED
 
+	PUSH	AF
+	PRTS("NOT POWERED$")
+	POP	AF
+	RET
+
+RTC_POWERED:
 	; DISPLAY CURRENT TIME
 	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
 	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP

From 44ceaa3e7173143ea76c4466651f8b40802e820f Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Tue, 16 Jul 2024 18:22:28 +1000
Subject: [PATCH 27/62] ez80: update to new version of 60hz get sec firmware
 interface

---
 Source/HBIOS/hbios.asm | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 3d19bfa1..03c5edb0 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -5074,6 +5074,12 @@ SYS_GETSECS:
 	LD	A, 2
 	LD	B, 1			; GET SECOND TICK
 	EZ80_FN
+
+	LD	A, 0
+	LD	B, 2			; LD E:HL{15:0}, HL
+	EZ80_FN
+	LD	D, 0
+
 	RET
 
 #ELSE

From e757591fb319f42632290ed6277446cf075252a5 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Tue, 16 Jul 2024 08:34:46 +0000
Subject: [PATCH 28/62] ez80: added missing #ENDIF in ez80uart.asm

---
 Source/HBIOS/ez80rtc.asm  | 2 --
 Source/HBIOS/ez80uart.asm | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index 1adaac44..e58bad36 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -7,8 +7,6 @@ EZ80RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 
-		DEVECHO	"EZ80 RTC:\n"
-
 EZ80RTC_INIT:
 	; display driver install message
 	; delegate init function to firmware
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index c91873aa..e79fa9a3 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -34,7 +34,6 @@ UART0_RBR	.EQU	$C0
 LSR_THRE	.EQU	$20
 LSR_DR		.EQU	$01
 
-
 EZUART_PREINIT:
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
@@ -336,3 +335,4 @@ EZUART_FNTBL:
 	.DW	EZUART_DEVICE
 #IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2))
 	.ECHO	"*** INVALID EZUART FUNCTION TABLE ***\n"
+#ENDIF

From 20aa3a7d6585242f5e18bcaba68d4dc8338d4e56 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Tue, 16 Jul 2024 08:45:10 +0000
Subject: [PATCH 29/62] makefile: turn off forced tracing - use option (--trace
 and or --debug) to trace makefile execution

---
 Source/HBIOS/Makefile | 14 +++++++-------
 Source/Makefile       |  4 ++--
 Tools/Makefile        |  2 +-
 Tools/Makefile.inc    | 30 +++++++++++++++---------------
 Tools/unix/Makefile   |  4 ++--
 5 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index d684aa1f..97910740 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -18,7 +18,7 @@ endif
 
 ifeq ($(OBJECTS),)
 start:
-	chmod +x Build.sh
+	@chmod +x Build.sh
 	bash Build.sh $(DIFFBUILD)
 endif
 
@@ -59,7 +59,7 @@ ROMNAME=${ROM_PLATFORM}_${ROM_CONFIG}
 # $(info TASM=$(TASM))
 
 $(OBJECTS) : $(ROMDEPS)
-	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin
+	@cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin ../CPM22/cpm_$(BIOS).bin >osimg.bin
 	cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >osimg_small.bin
 	if [ $(ROM_PLATFORM) != UNA ] ; then \
 		cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin usrrom.bin >osimg1.bin ; \
@@ -104,19 +104,19 @@ tastybasic.bin:
 	cp ../TastyBasic/src/$@ .
 	
 hbios_rom.bin:	hbios.asm build.inc  $(DEPS)
-	$(TASM) -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst
+	@$(TASM) -dROMBOOT hbios.asm hbios_rom.bin hbios_rom.lst
 
 hbios_app.bin:	hbios.asm build.inc  $(DEPS)
-	$(TASM) -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst
+	@$(TASM) -dAPPBOOT hbios.asm hbios_app.bin hbios_app.lst
 
 hbios_img.bin:	hbios.asm build.inc  $(DEPS)
-	$(TASM) -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst
+	@$(TASM) -dIMGBOOT hbios.asm hbios_img.bin hbios_img.lst
 
 hbios_env.com:	hbios_env.asm build.inc
-	$(TASM) -dBASH hbios_env.asm hbios_env.com hbios_env.lst
+	@$(TASM) -dBASH hbios_env.asm hbios_env.com hbios_env.lst
 	
 hbios_env.sh: hbios_env.com
-	$(ZXCC) hbios_env.com >hbios_env.sh
+	@$(ZXCC) hbios_env.com >hbios_env.sh
 
 romldr.bin:	build.inc
 dbgmon.bin:	build.inc
diff --git a/Source/Makefile b/Source/Makefile
index ea0bd77f..add7330d 100644
--- a/Source/Makefile
+++ b/Source/Makefile
@@ -5,7 +5,7 @@
 .PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512
 
 .ONESHELL:
-.SHELLFLAGS = -cex
+.SHELLFLAGS = -ce
 
 all: prop shared bp images rom zrc z1rcc zzrcc zrc512
 
@@ -40,7 +40,7 @@ images:
 	$(MAKE) --directory Images $(ACTION)
 
 rom:
-	$(MAKE) --directory HBIOS $(ACTION)
+	@$(MAKE) --directory HBIOS $(ACTION)
 
 zrc:
 	$(MAKE) --directory ZRC $(ACTION)
diff --git a/Tools/Makefile b/Tools/Makefile
index 74baac9a..a4bbdb71 100644
--- a/Tools/Makefile
+++ b/Tools/Makefile
@@ -3,7 +3,7 @@
 #
 
 .ONESHELL:
-.SHELLFLAGS = -cex
+.SHELLFLAGS = -ce
 
 UNAME := $(shell uname)
 
diff --git a/Tools/Makefile.inc b/Tools/Makefile.inc
index 10be67c5..a541305c 100644
--- a/Tools/Makefile.inc
+++ b/Tools/Makefile.inc
@@ -56,7 +56,7 @@ CPM=$(TOOLS)/cpm/bin80/
 #    exit if any command returns a non-zero result ("x").
 #
 .ONESHELL:
-.SHELLFLAGS = -cex
+.SHELLFLAGS = -ce
 
 %.com: %.asm
 	@if [ "$(USETASM)" = 1 ] ; then \
@@ -70,52 +70,52 @@ CPM=$(TOOLS)/cpm/bin80/
 	fi
 
 %.rom: %.asm
-	$(TASM) $(TASMFLAGS) $< $@ $*.lst
+	@$(TASM) $(TASMFLAGS) $< $@ $*.lst
 
 %.hex: %.asm
-	$(ZXCC) $(CPM)/MAC -$< -$$PO
+	@$(ZXCC) $(CPM)/MAC -$< -$$PO
 
 %.bin: %.ASM
-	$(ZXCC) $(CPM)/MAC -$< -$$PO
+	@$(ZXCC) $(CPM)/MAC -$< -$$PO
 	$(ZXCC) $(CPM)/MLOAD25 -tmp.bin=$*.hex
 	mv tmp.bin $@
 	rm -f /tmp/casefn.cache
 	rm -f $$($(CASEFN) $*.hex)
 
 %.com: %.z80
-	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/F
+	@$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/F
 	rm -f /tmp/casefn.cache
 	mv $$($(CASEFN) $@) tmp.com ; mv tmp.com $@
 
 %.bin: %.asm
-	$(TASM) $(TASMFLAGS) $< $@ $(basename $<).lst
+	@$(TASM) $(TASMFLAGS) $< $@ $(basename $<).lst
 
 %.rel: %.asm
-	$(ZXCC) $(CPM)/RMAC -$<
+	@$(ZXCC) $(CPM)/RMAC -$<
 
 %.rel: %.z80
-	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF
+	@$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/MF
 
 #%.hex: %.z80
-#	$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
+#	@$(ZXCC) $(CPM)/Z80ASM -$(basename $<)/HF
 
 %.hex: %.z80
-	$(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF
+	@$(ZXCC) $(CPM)/SLR180 -$(basename $<)/HF
 
 %.rel: %.azm
-	$(ZXCC) $(CPM)/ZSM =$< -/L
+	@$(ZXCC) $(CPM)/ZSM =$< -/L
 
 %.bin: %.rel
-	$(ZXCC) $(CPM)/LINK -$@=$<
+	@$(ZXCC) $(CPM)/LINK -$@=$<
 
 %.rel: %.mac
-	$(ZXCC) $(CPM)/M80 -=$(basename $<)
+	@$(ZXCC) $(CPM)/M80 -=$(basename $<)
 
 %.com: %.rel
-	$(ZXCC) $(CPM)/L80 -$(basename $<),$(basename $<).com/n/e
+	@$(ZXCC) $(CPM)/L80 -$(basename $<),$(basename $<).com/n/e
 
 %.eeprom: %.spin
-	$(OPENSPIN) -e $<
+	@$(OPENSPIN) -e $<
 
 #
 # first target is default
diff --git a/Tools/unix/Makefile b/Tools/unix/Makefile
index ebdecfb5..7cefdb27 100644
--- a/Tools/unix/Makefile
+++ b/Tools/unix/Makefile
@@ -3,7 +3,7 @@
 #
 
 .ONESHELL:
-.SHELLFLAGS = -cex
+.SHELLFLAGS = -ce
 
 UNAME := $(shell uname)
 ifeq ($(UNAME), Linux)
@@ -20,4 +20,4 @@ all:
 	@$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) all;)
 
 clean:
-	@$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) clean;)
\ No newline at end of file
+	@$(foreach subdir,$(SUBDIRS),$(MAKE) --directory $(subdir) clean;)

From 3318b12667c1f6949111c2923c7cd6758efcb896 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 19 Jul 2024 19:19:05 +1000
Subject: [PATCH 30/62] ez80: fixed issue with CH37x-USB driver not working at
 frequency > 7Mhz

---
 Source/HBIOS/cfg_rcez80.asm | 6 +++---
 Source/HBIOS/cfg_rcz80.asm  | 6 +++---
 Source/HBIOS/chsd.asm       | 2 +-
 Source/HBIOS/chusb.asm      | 2 ++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 900bde81..5beab79f 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -263,9 +263,9 @@ SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	2		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	2		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	2		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
 CH0BASE		.EQU	$88		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index ba3ae249..a3069384 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -261,12 +261,12 @@ CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
 CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$88		; CH 0: BASE I/O ADDRESS
 CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
 CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
 CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
 CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
diff --git a/Source/HBIOS/chsd.asm b/Source/HBIOS/chsd.asm
index e1a7e81d..2b217b80 100644
--- a/Source/HBIOS/chsd.asm
+++ b/Source/HBIOS/chsd.asm
@@ -19,7 +19,7 @@
 ;
 #DEFINE	CHSD_IMGFILE "DISK.IMG"
 ;
-CHSD_FASTIO	.EQU	TRUE		; USE INIR/OTIR?
+CHSD_FASTIO	.EQU	FALSE		; USE INIR/OTIR?
 ;
 ; CHUSB DEVICE STATUS
 ;
diff --git a/Source/HBIOS/chusb.asm b/Source/HBIOS/chusb.asm
index 175a00b2..d77f3f64 100644
--- a/Source/HBIOS/chusb.asm
+++ b/Source/HBIOS/chusb.asm
@@ -196,6 +196,7 @@ CHUSB_READ1:
 	PUSH	BC			; SAVE LOOP CONTROL
 	LD	B,64			; READ 64 BYTES
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	INIR				; DO IT FAST
 	POP	BC			; RESTORE LOOP CONTROL
 #ELSE
@@ -260,6 +261,7 @@ CHUSB_WRITE1:
 	PUSH	BC			; SAVE LOOP CONTROL
 	LD	B,64			; WRITE 64 BYTES
 	LD	C,(IY+CH_IOBASE)	; BASE PORT
+	EZ80_IO
 	OTIR				; DO IT FAST
 	POP	BC			; RESTORE LOOP CONTROL
 #ELSE

From 53198e066cf9a5a4783fbea113e8b686c360988a Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 19 Jul 2024 21:18:28 +1000
Subject: [PATCH 31/62] ez80: added macros for accessing all firmware functions

---
 Source/HBIOS/ez80instr.inc | 21 +++++++++++++++++++++
 Source/HBIOS/ez80rtc.asm   | 16 ++++------------
 Source/HBIOS/ez80uart.asm  | 34 ++++++++--------------------------
 Source/HBIOS/hbios.asm     | 33 ++++++++-------------------------
 4 files changed, 41 insertions(+), 63 deletions(-)

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index dbb4ed8f..4e854af9 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,6 +11,27 @@
   #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 
+  #DEFINE EZ80_UTIL_INIT	LD A, 0 \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_EHL_TO_HL	LD A, 0 \ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_UTIL_HL_TO_EHL	LD A, 0 \ LD B, 2 \ EZ80_FN
+
+  #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_RTC_SET_TIME 	LD A, 1	\ LD B, 2 \ EZ80_FN
+
+  #DEFINE EZ80_TMR_GET_TICKS	LD A, 2 \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_SECONDS	LD A, 2 \ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_TICKS	LD A, 2 \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B, 3 \ EZ80_FN
+
+  #DEFINE EZ80_UART_IN		LD A, 3 \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UART_OUT		LD A, 3 \ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_UART_IN_STAT	LD A, 3 \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_UART_OUT_STAT	LD A, 3 \ LD B, 3 \ EZ80_FN
+  #DEFINE EZ80_UART_CONFIG	LD A, 3 \ LD B, 4 \ EZ80_FN
+  #DEFINE EZ80_UART_QUERY	LD A, 3 \ LD B, 5 \ EZ80_FN
+  #DEFINE EZ80_UART_RESET	LD A, 3 \ LD B, 6 \ EZ80_FN
+
   #DEFINE RET.L		.DB	$49 \ RET
 
   #DEFINE IN0_A(p)	.DB	$ED,$38,p
diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index e58bad36..78fae96f 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -20,9 +20,7 @@ EZ80RTC_INIT:
 	CALL	NEWLINE			; FORMATTING
 	PRTS("EZ80 RTC: ON-CHIP $")
 
-	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
-	LD	B, 0			; RTC INIT FUNCTION
-	EZ80_FN	
+	EZ80_RTC_INIT()
 	JR	Z, RTC_POWERED
 
 	PUSH	AF
@@ -33,9 +31,7 @@ EZ80RTC_INIT:
 RTC_POWERED:
 	; DISPLAY CURRENT TIME
 	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
-	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
-	LD	B, 1			; READ DATE-TIME INTO (HL)
-	EZ80_FN
+	EZ80_RTC_GET_TIME()
 
 	LD	HL, EZ80RTC_BCDBUF	; POINT TO BCD BUF
 	CALL	PRTDT			; DISPLAY THIS TIME
@@ -83,9 +79,7 @@ EZ80RTC_DISPATCH:
 EZ80RTC_GETTIM:
 	PUSH	HL
 	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
-	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
-	LD	B, 1			; READ DATE-TIME INTO (HL)
-	EZ80_FN
+	EZ80_RTC_GET_TIME()		; (HL) <- TIME
 
 	LD	A, BID_BIOS		; COPY FROM BIOS BANK
 	LD	(HB_SRCBNK), A		; SET IT
@@ -118,9 +112,7 @@ EZ80RTC_SETTIM:
 
 	LD	HL, EZ80RTC_BCDBUF_EXT	; POINT TO BCD BUF EXTENDED
 	LD	(HL), $20		; CENTURY NOT SUPPORT BY HBIOS
-	LD	A, 1			; RTC FIRMWARE FUNCTION GROUP
-	LD	B, 2			; WRITE DATE-TIME FROM (HL)
-	EZ80_FN
+	EZ80_RTC_SET_TIME()		; (HL) -> SYSTEM TIME
 
 	XOR	A			; SIGNAL SUCCESS
 	RET
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index e79fa9a3..abc7e104 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -58,9 +58,7 @@ EZUART_INIT:
 ;  A: Status (0-OK, else error)
 ;
 EZUART_IN:
-	LD	A, 3			; UART
-	LD	B, 0			; UART-IN
-	EZ80_FN				; CHAR RETURNED IN E
+	EZ80_UART_IN()			; CHAR RETURNED IN E
 	RET
 ;
 ; ### Function 0x01 -- Character Output (CIOOUT)
@@ -76,9 +74,7 @@ EZUART_IN:
 ;  A: Status (0-OK, else error)
 ;
 EZUART_OUT:
-	LD	A, 3			; UART
-	LD	B, 1			; UART-OUT
-	EZ80_FN
+	EZ80_UART_OUT()
 	RET
 ;
 ; ### Function 0x02 -- Character Input Status (CIOIST)
@@ -94,9 +90,7 @@ EZUART_OUT:
 ;  A: Status / Characters Pending
 ;
 EZUART_IST:
-	LD	A, 3			; UART
-	LD	B, 2			; UART-IST
-	EZ80_FN
+	EZ80_UART_IN_STAT()
 	RET
 ;
 ; ### Function 0x03 -- Character Output Status (CIOOST)
@@ -110,9 +104,7 @@ EZUART_IST:
 ;   A: Status (0 -> Full, 1 -> OK to send, < 0 -> HBIOS error code)
 ;
 EZUART_OST:
-	LD	A, 3			; UART
-	LD	B, 3			; UART-OST
-	EZ80_FN
+	EZ80_UART_OUT_STAT()
 	RET
 
 BAUD_RATE	.EQU	115200
@@ -137,10 +129,7 @@ EZUART_INITDEV:
 	CP	$FF
 	JR	NZ, NOT_RESET
 
-	; reset requested
-	LD	A, 3			; UART
-	LD	B, 6			; UART-RESET
-	EZ80_FN
+	EZ80_UART_RESET()
 	RET
 
 NOT_RESET:
@@ -152,10 +141,7 @@ NOT_RESET:
 	LD	DE, 75			; BAUD RATE DECODE CONSTANT
 	CALL	DECODE			; DE:HL := BAUD RATE
 
-	;; convert E:HL{15:0} to HL{23:0}
-	LD	A, 0
-	LD	B, 1			; UTIL - LD HL, E:HL
-	EZ80_FN
+	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
 
 	POP	DE			; RESTORE REQUESTED LINE CHARACTERISTICS
 	LD	A, E
@@ -182,9 +168,7 @@ ISKIP3:
 
 	; D NOW CONTAINS THE LINE CONTROL BITS AS PER EZ80 FUNCTION
 
-	LD	A, 3			; UART
-	LD	B, 4			; UART-CONFIG
-	EZ80_FN
+	EZ80_UART_CONFIG()
 	RET
 
 #DEFINE	TRANSLATE(nnn,rrr) \
@@ -208,9 +192,7 @@ ISKIP3:
 ;  A: Status (0-OK, else error)
 ;
 EZUART_QUERY:
-	LD	A, 3			; UART
-	LD	B, 5			; UART-QUERY
-	EZ80_FN		
+	EZ80_UART_QUERY()
 					; HL{23:0} := BAUD RATE
 					; D = LINE CONTROL BITS
 	PUSH	DE			; SAVE D
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 03c5edb0..359a3e83 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1439,7 +1439,7 @@ BOOTWAIT:
 	XOR	A			; FUNCTION CODE TO INIT FIRMWARE
 	LD	HL, PLT_DESCR
 
-	EZ80_FN				; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+	EZ80_UTIL_INIT()			; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
 	JR	PLT_DESCR_END
 
 PLT_DESCR:
@@ -5048,9 +5048,7 @@ SYS_GETFN:
 ;
 SYS_GETTIMER:
 #IF (CPUFAM == CPU_EZ80)
-	LD	A, 2
-	LD	B, 0			; GET TIMER TICK
-	EZ80_FN
+	EZ80_TMR_GET_TICKS()
 	RET
 
 #ELSE
@@ -5071,15 +5069,10 @@ SYS_GETTIMER:
 ;
 SYS_GETSECS:
 #IF (CPUFAM == CPU_EZ80)
-	LD	A, 2
-	LD	B, 1			; GET SECOND TICK
-	EZ80_FN
+	EZ80_TMR_GET_SECONDS()
 
-	LD	A, 0
-	LD	B, 2			; LD E:HL{15:0}, HL
-	EZ80_FN
+	EZ80_UTIL_HL_TO_EHL()		; E:HL{15:0} <- HL{23:0}
 	LD	D, 0
-
 	RET
 
 #ELSE
@@ -5302,14 +5295,8 @@ SYS_SETBOOTINFO:
 ;
 SYS_SETTIMER:
 #IF (CPUFAM == CPU_EZ80)
-	;; convert E:HL{15:0} to HL{23:0}
-	LD	A, 0
-	LD	B, 1			; UTIL - LD HL, E:HL
-	EZ80_FN
-
-	LD	A, 2		
-	LD	B, 2			; SET TICKS
-	EZ80_FN
+	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+	EZ80_TMR_SET_TICKS()
 	RET
 #ELSE
 	LD	BC,HB_TICKS
@@ -5326,13 +5313,9 @@ SYS_SETTIMER:
 ;
 SYS_SETSECS:
 #IF (CPUFAM == CPU_EZ80)
-	LD	A, 0
-	LD	B, 1			; UTIL - LD HL, E:HL
-	EZ80_FN
+	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
 
-	LD	A, 2
-	LD	B, 3			; SET SECS
-	EZ80_FN
+	EZ80_TMR_SET_SECONDS()
 	RET
 #ELSE
 	LD	BC,HB_SECS

From 026fa3d0d7d47ece6df98541252f21577c483bf4 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 20 Jul 2024 12:58:59 +1000
Subject: [PATCH 32/62] ez80: request CPU speed from ez80 firmware

---
 Source/HBIOS/ez80instr.inc |  6 +--
 Source/HBIOS/hbios.asm     | 78 +++++++++++++++++++++++---------------
 2 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 4e854af9..f8af7d1a 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,9 +11,9 @@
   #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 
-  #DEFINE EZ80_UTIL_INIT	LD A, 0 \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_UTIL_EHL_TO_HL	LD A, 0 \ LD B, 1 \ EZ80_FN
-  #DEFINE EZ80_UTIL_HL_TO_EHL	LD A, 0 \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_UTIL_INIT	XOR A \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_UTIL_HL_TO_EHL	XOR A \ LD B, 2 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 359a3e83..5cceb051 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1431,32 +1431,6 @@ BOOTWAIT:
 	OUT0	(RPH_ACR),A		; ... REGISTER IS INITIALIZED
 #ENDIF
 
-
-#IF (CPUFAM == CPU_EZ80)
-
-; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
-
-	XOR	A			; FUNCTION CODE TO INIT FIRMWARE
-	LD	HL, PLT_DESCR
-
-	EZ80_UTIL_INIT()			; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
-	JR	PLT_DESCR_END
-
-PLT_DESCR:
-	.DB	PLT_RCZ80
-	.DB	MEMMGR
-	.DW	RAMSIZE
-	.DW	ROMSIZE
-	.DB	MPGSEL_0
-	.DB	MPGSEL_1
-	.DB	MPGSEL_2
-	.DB	MPGSEL_3
-	.DB	MPGENA
-
-PLT_DESCR_END:
-
-#ENDIF
-
 ;
 ; INITIALIZE DIAGNOSTIC AND/OR FRONT PANEL LED(S) TO INDICATE THE
 ; SYSTEM IS ALIVE. WE HAVE NO RAM AT THIS TIME, SO WE CANNOT USE
@@ -2157,9 +2131,52 @@ HB_CLRIVT_Z:
 ;	2: Z8S180 - ORIGINAL S-CLASS, REV. K, AKA SL1960, NO ASCI BRG
 ;	3: Z8S180 - REVISED S-CLASS, REV. N, W/ ASCI BRG
 ;	4: Z8280
+;       5: eZ80
 ;
 	LD	HL,0		; L = 0 MEANS Z80
 ;
+
+#IF (CPUFAM == CPU_EZ80)
+
+; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
+	LD	HL, PLT_DESCR
+	EZ80_UTIL_INIT()	; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+
+	LD	A, (EZ80_PLT_CPUMHZ)
+	LD	(CB_CPUMHZ), A
+	LD	HL, (EZ80_PLT_CPUKHZ)
+	LD	(CB_CPUKHZ), HL
+	LD	(HB_CPUOSC), HL
+
+	JR	PLT_DESCR_END
+
+PLT_DESCR:
+EZ80_PLT_EZ80VER:
+	.DB	RMJ
+	.DB	RMN
+	.DB	RUP
+	.DB	RTP
+EZ80_PLT_CPUOSC:
+	.DW	CPUOSC & $FFFF
+	.DW	CPUOSC >> 16
+EZ80_PLT_CPUMHZ:
+	.DB	PLATFORM
+EZ80_PLT_CPUKHZ:
+	.DB	MEMMGR
+	.DB	RAMSIZE & $FF
+EZ80_PLT_CHIP_ID:
+	.DB	RAMSIZE >> 8
+EZ80_PLT_RESVRD:
+	.DB	ROMSIZE & $FF
+	.DB	ROMSIZE >> 8
+	.DB	0 		; RESERVED
+	.DB	0 		; RESERVED
+PLT_DESCR_END:
+
+	LD	HL,5
+
+#ENDIF
+;
 #IF (CPUFAM == CPU_Z180)
 ;
 	; TEST FOR ORIGINAL Z180 USING MLT
@@ -2198,10 +2215,6 @@ HB_CLRIVT_Z:
 	LD	L,4		; WE ARE Z280
 ;
 #ENDIF
-
-#IF (CPUFAM == CPU_EZ80)
-	LD	L,5
-#ENDIF
 ;
 HB_CPU1:
 	LD	A,L
@@ -2261,6 +2274,7 @@ HB_CPU1:
 ;
 ; INIT OSCILLATOR SPEED FROM CONFIG
 ;
+#IF (CPUFAM != CPU_EZ80)
 	LD	HL,CPUOSC / 1000	; OSC SPD IN KHZ
 	LD	(HB_CPUOSC),HL		; INIT HB_CPUOSC DEFAULT
 ;
@@ -2285,6 +2299,7 @@ HB_CPU1:
 	LD	(HB_CPUOSC),HL		; RECORD MEASURED SPEED
 ;
 HB_CPU2:
+#ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
 ; FINALIZE OPERATING CPU SPEED
@@ -7254,6 +7269,8 @@ FP_GETSWITCHES:
 FP_ACTIVE:
 FPSW_ACTIVE	.DB	TRUE
 FPLED_ACTIVE	.DB	TRUE
+
+#IF (CPUFAM != CPU_EZ80) ; eZ80 WILL RETURNED ITS MEASURED CPUOSC - SO NO NEED FOR DETECTION HERE
 ;
 ;==================================================================================================
 ; CPU SPEED DETECTION USING DS-1302 RTC
@@ -7372,6 +7389,7 @@ HB_CPUSPD2:
 	; HANDLE NO RTC OR NOT TICKING
 	OR	$FF			; SIGNAL ERROR
 	RET				; AND DONE
+#ENDIF ; CPUFAM != CPU_EZ80
 ;
 HB_UTIL_END	.EQU	$
 ;

From 4b80f36fd06c7c9806b732ce6c402af231355138 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 20 Jul 2024 13:22:12 +1000
Subject: [PATCH 33/62] ez80: configure and display memory and i/o timings

---
 Source/HBIOS/Config/RCEZ80_std.asm |  3 +++
 Source/HBIOS/cfg_rcez80.asm        | 10 ++++++++
 Source/HBIOS/ez80instr.inc         |  2 ++
 Source/HBIOS/hbios.asm             | 39 ++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index b72ac5ec..3b492d2f 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -66,3 +66,6 @@ SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+
+EZ80_IO_FREQ	.SET	8000
+EZ80_MEM_FREQ	.SET	8000
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 5beab79f..cb030938 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -44,6 +44,16 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
+EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
+EZ80_MEM_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_MEM_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
+;
+; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
+EZ80_IO_CYCLES	.EQU	3		; EZ80 CYCLES FOR IO (1-15)
+EZ80_IO_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_IO_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
+;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index f8af7d1a..1aa5492c 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -14,6 +14,8 @@
   #DEFINE EZ80_UTIL_INIT	XOR A \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_HL_TO_EHL	XOR A \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSTM 	XOR A \ LD B, 3 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSFQ 	XOR A \ LD B, 4 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 5cceb051..27c22d74 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2148,6 +2148,15 @@ HB_CLRIVT_Z:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
+	LD	HL, EZ80_MEM_FREQ
+	LD	DE, EZ80_IO_FREQ
+	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
+
+	LD	A, H
+	LD	(EZ80_PLT_C3CYL), A
+	LD	A, L
+	LD	(EZ80_PLT_C2CYL), A
+
 	JR	PLT_DESCR_END
 
 PLT_DESCR:
@@ -2171,6 +2180,12 @@ EZ80_PLT_RESVRD:
 	.DB	ROMSIZE >> 8
 	.DB	0 		; RESERVED
 	.DB	0 		; RESERVED
+
+EZ80_PLT_C3CYL:
+	.DB	EZ80_MEM_CYCLES
+EZ80_PLT_C2CYL:
+	.DB	EZ80_IO_CYCLES
+
 PLT_DESCR_END:
 
 	LD	HL,5
@@ -2962,7 +2977,16 @@ HB_Z280BUS1:
 ;--------------------------------------------------------------------------------------------------
 ;
 	CALL	NEWLINE
+;
+; DISPLAY MEMORY TIMINGS
+;
+#IF (CPUFAM == CPU_EZ80)
+	LD	A,(EZ80_PLT_C3CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM B/C, $"
 
+#ELSE
 #IF (CPUFAM == CPU_Z280)
 	LD	A,Z280_MEMLOWAIT
 	CALL	PRTDECB
@@ -2981,6 +3005,17 @@ HB_Z280BUS1:
 	CALL	PRTSTRD
 	.TEXT	" MEM W/S, $"
 #ENDIF
+#ENDIF ; CPUFAM = CPU_EZ80
+;
+; DISPLAY I/O TIMINGS
+;
+#IF (CPUFAM == CPU_EZ80)
+	LD	A,(EZ80_PLT_C2CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" I/O B/C$"
+
+#ELSE
 	LD	A,1
 #IF (CPUFAM == CPU_Z180)
 	LD	A,Z180_IOWAIT + 1
@@ -2999,6 +3034,10 @@ HB_Z280BUS1:
 	CALL	PRTSTRD
 	.TEXT	" INT W/S$"
 #ENDIF
+#ENDIF //CPUFAM = CPU_EZ80
+;
+; DISPLAY INTERRUPT MODE
+;
 #IF (INTMODE > 0)
 	CALL	PRTSTRD
 	.TEXT	", INT MODE $"

From 22b10c8ac8fadff62ddecb3f3dea8af09622bd95 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 20 Jul 2024 22:09:13 +1000
Subject: [PATCH 34/62] ez80: updated IDE driver for eZ80 platform.

---
 Source/HBIOS/Config/RCEZ80_std.asm | 2 +-
 Source/HBIOS/cfg_rcez80.asm        | 2 +-
 Source/HBIOS/ide.asm               | 8 ++++++++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 3b492d2f..9426400f 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -58,7 +58,7 @@ SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
-IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index cb030938..df4b903c 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -230,7 +230,7 @@ FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
 IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	4		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
 IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
 IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm
index 6398522d..57ec4749 100644
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -1238,8 +1238,10 @@ IDE_GET8:
 	;LD	C,IDE_REG_DATA
 	LD	C,(IY+IDE_IOBASE)
 	LD	B,A
+	EZ80_IO
 	INIR
 	LD	B,A
+	EZ80_IO
 	INIR
 	RET
 ;
@@ -1253,8 +1255,10 @@ IDE_GET16:
 ;
 IDE_GET16A:
 	LD	C,D			; PORT FOR LSB
+	EZ80_IO
 	INI				; GET IT, SAVE IT, AND DEC B
 	LD	C,E			; PORT FOR MSB
+	EZ80_IO
 	INI				; GET IT, SAVE IT, AND DEC B
 	DEC	A
 	JR	NZ,IDE_GET16A		; LOOP TILL COUNTER EXHAUSTED
@@ -1303,8 +1307,10 @@ IDE_PUT8:
 	;LD	C,IDE_REG_DATA
 	LD	C,(IY+IDE_IOBASE)
 	LD	B,A
+	EZ80_IO
 	OTIR
 	LD	B,A
+	EZ80_IO
 	OTIR
 	RET
 ;
@@ -1318,8 +1324,10 @@ IDE_PUT16:
 ;
 IDE_PUT16A:
 	LD	C,D			; PORT FOR LSB
+	EZ80_IO
 	OUTI				; PUT IT AND DEC B
 	LD	C,E			; PORT FOR MSB
+	EZ80_IO
 	OUTI				; PUT IT AND DEC B
 	DEC	A
 	JR	NZ,IDE_PUT16A		; LOOP TILL COUNTER EXHAUSTED

From 945d5fc2d263a7e5fc1590f68633619082c9c174 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 22 Jul 2024 13:23:03 +1000
Subject: [PATCH 35/62] ez80: set timer tick rate as per platform config
 TICKFREQ

---
 Source/HBIOS/ez80instr.inc | 2 ++
 Source/HBIOS/hbios.asm     | 9 ++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 1aa5492c..2b3b24ed 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -25,6 +25,8 @@
   #DEFINE EZ80_TMR_GET_SECONDS	LD A, 2 \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_TMR_SET_TICKS	LD A, 2 \ LD B, 2 \ EZ80_FN
   #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B, 3 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_FREQTICK	LD A, 2 \ LD B, 4 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_FREQTICK	LD A, 2 \ LD B, 5 \ EZ80_FN
 
   #DEFINE EZ80_UART_IN		LD A, 3 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UART_OUT		LD A, 3 \ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 27c22d74..21359664 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2140,7 +2140,7 @@ HB_CLRIVT_Z:
 
 ; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
 	LD	HL, PLT_DESCR
-	EZ80_UTIL_INIT()	; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+	EZ80_UTIL_INIT()		; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
 
 	LD	A, (EZ80_PLT_CPUMHZ)
 	LD	(CB_CPUMHZ), A
@@ -2157,6 +2157,11 @@ HB_CLRIVT_Z:
 	LD	A, L
 	LD	(EZ80_PLT_C2CYL), A
 
+	LD	C, TICKFREQ
+	EZ80_TMR_SET_FREQTICK
+
+	LD	HL, 5			; HB_CPUTYPE = 5 FOR eZ80
+
 	JR	PLT_DESCR_END
 
 PLT_DESCR:
@@ -2188,8 +2193,6 @@ EZ80_PLT_C2CYL:
 
 PLT_DESCR_END:
 
-	LD	HL,5
-
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)

From 209f4571207cb80d17d5827a6ea1b9ea429d2b8f Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Mon, 22 Jul 2024 13:23:03 +1000
Subject: [PATCH 36/62] ez80: updated to use new functions EZ80_UTIL_VER_EXCH,
 EZ80_UTIL_GET_CPU_FQ and EZ80_UTIL_BNK_HLP

---
 Source/HBIOS/ez80instr.inc |  4 +++-
 Source/HBIOS/hbios.asm     | 23 ++++++++++++++++++-----
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 2b3b24ed..f64043d4 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,11 +11,13 @@
   #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 
-  #DEFINE EZ80_UTIL_INIT	XOR A \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_VER_EXCH	XOR A \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_HL_TO_EHL	XOR A \ LD B, 2 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 	XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 	XOR A \ LD B, 4 \ EZ80_FN
+  #DEFINE EZ80_UTIL_GET_CPU_FQ 	XOR A \ LD B, 5 \ EZ80_FN
+  #DEFINE EZ80_UTIL_BNK_HLP 	XOR A \ LD B, 6 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 21359664..f5d27a33 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2139,19 +2139,32 @@ HB_CLRIVT_Z:
 #IF (CPUFAM == CPU_EZ80)
 
 ; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
-	LD	HL, PLT_DESCR
-	EZ80_UTIL_INIT()		; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+	LD	C, 1			; RomWBW'S ASSIGNED CODE
+	LD	D, RMJ
+	LD	E, RMN
+	LD	H, RUP
+	LD	L, RTP
 
-	LD	A, (EZ80_PLT_CPUMHZ)
+	EZ80_UTIL_VER_EXCH()
+	; TODO CHECK RETURNED VERSION AND WARN IF NOT GOOD
+	; EXPECT A VERSION NUMBER > 0.1.0.0
+
+	LD	C, MEMMGR
+	LD	HL, ROMSIZE
+	LD	DE, RAMSIZE
+	EZ80_UTIL_BNK_HLP()		; INSTAL HIGH PERFORMANCE BANK SWITCHER
+	; TODO CHECK RESULT AND USE STANDARD BANK SWITCHER IF NZ RETURNED
+	; OTHERWISE USE RST.L  %18 FOR BANK SWITCH HELPER
+
+	EZ80_UTIL_GET_CPU_FQ()
+	LD	A, E
 	LD	(CB_CPUMHZ), A
-	LD	HL, (EZ80_PLT_CPUKHZ)
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
 	LD	HL, EZ80_MEM_FREQ
 	LD	DE, EZ80_IO_FREQ
 	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
-
 	LD	A, H
 	LD	(EZ80_PLT_C3CYL), A
 	LD	A, L

From 890dd1cd5effee29e22cf83a7b1167353c0f5fb1 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Wed, 24 Jul 2024 14:33:14 +1000
Subject: [PATCH 37/62] eZ80: added support for sn76489 driver

---
 Source/HBIOS/Config/RCEZ80_std.asm |  4 +-
 Source/HBIOS/Config/RCZ80_std.asm  |  6 +--
 Source/HBIOS/cfg_rcez80.asm        |  5 +-
 Source/HBIOS/ez80instr.inc         | 43 ++++++++++++++--
 Source/HBIOS/hbios.asm             |  7 +++
 Source/HBIOS/sn76489.asm           | 80 ++++++++++++++++++++++++------
 6 files changed, 120 insertions(+), 25 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 9426400f..a5245967 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -53,7 +53,7 @@ VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
@@ -67,5 +67,5 @@ IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 
-EZ80_IO_FREQ	.SET	8000
+EZ80_IO_FREQ	.SET	5250
 EZ80_MEM_FREQ	.SET	8000
diff --git a/Source/HBIOS/Config/RCZ80_std.asm b/Source/HBIOS/Config/RCZ80_std.asm
index 13689758..964a5ad5 100644
--- a/Source/HBIOS/Config/RCZ80_std.asm
+++ b/Source/HBIOS/Config/RCZ80_std.asm
@@ -50,9 +50,9 @@ VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
-AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index df4b903c..2b124873 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -47,12 +47,13 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
 EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
 EZ80_MEM_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
-EZ80_MEM_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
 EZ80_IO_CYCLES	.EQU	3		; EZ80 CYCLES FOR IO (1-15)
 EZ80_IO_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
-EZ80_IO_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
+;
+; SELECT CYCLES, OR CALCULATE CYCLES BASED ON DESIRED FREQUENCY
+EZ80_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index f64043d4..35037033 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -7,9 +7,12 @@
 ; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
 ;
 #IF (CPUFAM == CPU_EZ80)
-  #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
-  #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
-  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
+  ; RST.L $08
+  #DEFINE EZ80_IO	.DB 	$49, $CF
+  ; RST.L $10
+  #DEFINE EZ80_FN 	.DB	$49, $D7
+  ; RST.L $18
+  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH	XOR A \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
@@ -18,6 +21,7 @@
   #DEFINE EZ80_UTIL_SET_BUSFQ 	XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 	XOR A \ LD B, 5 \ EZ80_FN
   #DEFINE EZ80_UTIL_BNK_HLP 	XOR A \ LD B, 6 \ EZ80_FN
+  #DEFINE EZ80_UTIL_DEBUG 	XOR A \ LD B, 7 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
@@ -29,6 +33,33 @@
   #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_TMR_GET_FREQTICK	LD A, 2 \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_TMR_SET_FREQTICK	LD A, 2 \ LD B, 5 \ EZ80_FN
+  #DEFINE EZ80_TMR_DELAY_START	LD A, 2 \ LD B, 6 \ EZ80_FN
+  #DEFINE EZ80_TMR_DELAY_WAIT	LD A, 2 \ LD B, 7 \ EZ80_FN
+
+  #DEFINE EZ80_DELAY_START(p,store) \
+  #DEFCONT \ PUSH AF
+  #DEFCONT \ PUSH BC
+  #DEFCONT \ PUSH HL
+  #DEFCONT \ LD A, 2
+  #DEFCONT \ LD BC, (6 * 256) + p
+  #DEFCONT \ EZ80_FN
+  #DEFCONT \ LD (store), HL
+  #DEFCONT \ POP HL
+  #DEFCONT \ POP BC
+  #DEFCONT \ POP AF
+
+  #DEFINE EZ80_DELAY_WAIT(p,store) \
+  #DEFCONT \ PUSH AF
+  #DEFCONT \ PUSH BC
+  #DEFCONT \ PUSH HL
+  #DEFCONT \ LD A, 2
+  #DEFCONT \ LD BC, (7 * 256) + p
+  #DEFCONT \ LD HL, (store)
+  #DEFCONT \ EZ80_FN
+  #DEFCONT \ LD (store), HL
+  #DEFCONT \ POP HL
+  #DEFCONT \ POP BC
+  #DEFCONT \ POP AF
 
   #DEFINE EZ80_UART_IN		LD A, 3 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UART_OUT		LD A, 3 \ LD B, 1 \ EZ80_FN
@@ -74,4 +105,10 @@ IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
 
 #ELSE
   #DEFINE EZ80_IO
+
+  #DEFINE EZ80_DELAY_START(p,store)
+  #DEFINE EZ80_DELAY_WAIT(p,store)
+
+IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
+
 #ENDIF
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index f5d27a33..5e9285d1 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2162,9 +2162,16 @@ HB_CLRIVT_Z:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
+#IF (EZ80_ASSIGN == 1)
+
+	LD	H, EZ80_MEM_CYCLES
+	LD	L, EZ80_IO_CYCLES
+	EZ80_UTIL_SET_BUSTM()
+#ELSE
 	LD	HL, EZ80_MEM_FREQ
 	LD	DE, EZ80_IO_FREQ
 	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
+#ENDIF
 	LD	A, H
 	LD	(EZ80_PLT_C3CYL), A
 	LD	A, L
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index 6f31de33..9b5770b5 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -4,7 +4,7 @@
 ;	WRITTEN BY: DEAN NETHERTON
 ;======================================================================
 ;
-; SN74489 PSG CHIP NEEDS AN INPUT CLOCK FREQUENCY OF
+; SN76489 PSG CHIP NEEDS AN INPUT CLOCK FREQUENCY OF
 ; NO MORE THAN 4 MHZ.  THE CLOSEST THING THERE IS TO A STANDARD
 ; IS THE MSX FREQ OF 3.579545 MHZ.
 ;
@@ -37,6 +37,20 @@ SN76489_PORT_RIGHT	.EQU	$BF	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
 	DEVECHO	"RC"
 #ENDIF
 ;
+
+SN76489_PORT16_LEFT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_LEFT
+SN76489_PORT16_RIGHT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_RIGHT
+
+#IF (CPUFAM == CPU_EZ80)
+; The eZ80 configuration must have sufficient bus cycles configured for this driver
+; to work.  See the entries: (EZ80_ASSIGN and EZ80_IO_CYCLES or EZ80_IO_FREQ)
+;
+; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations
+; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations
+
+SN76489_IO_DELAY	.EQU	15	; 200us DELAY BETWEEN CHANNEL WRITES
+
+#ENDIF
 	DEVECHO	", IO_LEFT="
 	DEVECHO	SN76489_PORT_LEFT
 	DEVECHO	", IO_RIGHT="
@@ -102,21 +116,34 @@ SN7_VOLUME_OFF:
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 #ENDIF
 
+
 	LD	A, CHANNEL_0_SILENT
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 	LD	A, CHANNEL_1_SILENT
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 	LD	A, CHANNEL_2_SILENT
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 	LD	A, CHANNEL_3_SILENT
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -174,9 +201,12 @@ SN7_PLAY:
 	AUDTRACE_D
 	AUDTRACE_CR
 
+	EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+
 	LD	A, (SN7_PENDING_PERIOD + 1)
 	CP	$FF
 	JR	Z, SN7_PLAY1		; PERIOD IS TOO LARGE, UNABLE TO PLAY
+
 	CALL	SN7_APPLY_VOL
 	CALL	SN7_APPLY_PRD
 
@@ -281,8 +311,12 @@ SN7_APPLY_VOL:				; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
 	POP	AF
 #ENDIF
 
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -295,6 +329,7 @@ SN7_APPLY_VOL:				; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
 	RET
 
 SN7_APPLY_PRD:
+
 	PUSH	DE
 	PUSH	BC
 	PUSH	AF
@@ -326,8 +361,12 @@ SN7_APPLY_PRD:
 	POP	AF
 #ENDIF
 
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -363,8 +402,14 @@ SN7_APPLY_PRD:
 	POP	AF
 #ENDIF
 
-	OUT	(SN76489_PORT_LEFT), A
-	OUT	(SN76489_PORT_RIGHT), A
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+
+	LD	BC, SN76489_PORT16_LEFT
+	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	OUT	(C), A
+
+	LD	BC, SN76489_PORT16_RIGHT
+	OUT	(C), A
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -413,6 +458,11 @@ SN7_PENDING_VOLUME
 SN7_PENDING_DURATION	
 	.DW	0		; PENDING DURATION (16 BITS)
 
+#IF (CPUFAM == CPU_EZ80)
+SN7_DELAY_COUNTER:
+	.DW	0
+#ENDIF
+
 STR_MESSAGELT	.DB	"\r\nSN76489: LEFT IO=0x$"
 STR_MESSAGERT	.DB	", RIGHT IO=0x$"
 

From 39232f00f1130d54a9d260c1d1c872a807068317 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Wed, 24 Jul 2024 16:23:18 +1000
Subject: [PATCH 38/62] sn76489: added configuration entry SN76489CHNOUT to
 direct to only to one channel or both

---
 Source/HBIOS/cfg_duo.asm      |  1 +
 Source/HBIOS/cfg_dyno.asm     |  1 +
 Source/HBIOS/cfg_epitx.asm    |  1 +
 Source/HBIOS/cfg_heath.asm    |  1 +
 Source/HBIOS/cfg_master.asm   |  1 +
 Source/HBIOS/cfg_mbc.asm      |  1 +
 Source/HBIOS/cfg_mk4.asm      |  1 +
 Source/HBIOS/cfg_mon.asm      |  1 +
 Source/HBIOS/cfg_n8.asm       |  1 +
 Source/HBIOS/cfg_nabu.asm     |  1 +
 Source/HBIOS/cfg_rcez80.asm   |  1 +
 Source/HBIOS/cfg_rcz180.asm   |  1 +
 Source/HBIOS/cfg_rcz280.asm   |  1 +
 Source/HBIOS/cfg_rcz80.asm    |  1 +
 Source/HBIOS/cfg_rph.asm      |  1 +
 Source/HBIOS/cfg_s100.asm     |  1 +
 Source/HBIOS/cfg_sbc.asm      |  1 +
 Source/HBIOS/cfg_scz180.asm   |  1 +
 Source/HBIOS/cfg_z80retro.asm |  1 +
 Source/HBIOS/cfg_zeta.asm     |  1 +
 Source/HBIOS/cfg_zeta2.asm    |  1 +
 Source/HBIOS/sn76489.asm      | 20 +++++++++++++-------
 Source/HBIOS/std.asm          |  6 ++++++
 23 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm
index 979f32ae..3bc052ea 100644
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -306,6 +306,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index b37b2222..3cc02f97 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -285,6 +285,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm
index 8bdd7d04..240eb5b2 100644
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -317,6 +317,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm
index 2ef14948..b85556ba 100644
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -310,6 +310,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 52be3841..1ef9fe79 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -377,6 +377,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm
index 0f12e79e..80363530 100644
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -293,6 +293,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index b8464158..9eb056eb 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -289,6 +289,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm
index cfc28dcc..d8c45232 100644
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@@ -315,6 +315,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index a4979601..655894bc 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -282,6 +282,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm
index 754bce99..526d6632 100644
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@@ -320,6 +320,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 2b124873..c36f6efc 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -336,6 +336,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_LEFT	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index b229fbb0..34341f3c 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -321,6 +321,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 8d9da62b..a496f52c 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -325,6 +325,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index a3069384..8942e3a0 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -320,6 +320,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_rph.asm b/Source/HBIOS/cfg_rph.asm
index 2ecbb855..b866b733 100644
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -271,6 +271,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm
index 14e2225a..92d7829c 100644
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -305,6 +305,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 6da370f0..c6c8ed23 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -271,6 +271,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 018029b9..b334a783 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -315,6 +315,7 @@ PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
 SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
 SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm
index 8fb1c216..f6f4fd1c 100644
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -239,6 +239,7 @@ PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 0a213bb3..e35ea484 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -210,6 +210,7 @@ PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 00900b97..3a7bc05c 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -221,6 +221,7 @@ PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+SN76489CHNOUT	.EQU	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index 9b5770b5..b52d0f1b 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -48,7 +48,7 @@ SN76489_PORT16_RIGHT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_RIGHT
 ; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations
 ; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations
 
-SN76489_IO_DELAY	.EQU	15	; 200us DELAY BETWEEN CHANNEL WRITES
+SN76489_IO_DELAY	.EQU	5	; 200us DELAY BETWEEN CHANNEL WRITES
 
 #ENDIF
 	DEVECHO	", IO_LEFT="
@@ -116,7 +116,6 @@ SN7_VOLUME_OFF:
 	OUT	(RTCIO),A		; TO HALF CLOCK SPEED
 #ENDIF
 
-
 	LD	A, CHANNEL_0_SILENT
 	LD	BC, SN76489_PORT16_LEFT
 	EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
@@ -313,10 +312,13 @@ SN7_APPLY_VOL:				; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
 
 	LD	BC, SN76489_PORT16_LEFT
 	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
-
+#ENDIF
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT))
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
+#ENDIF
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -363,10 +365,13 @@ SN7_APPLY_PRD:
 
 	LD	BC, SN76489_PORT16_LEFT
 	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
-
+#ENDIF
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT))
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
+#ENDIF
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
@@ -402,14 +407,15 @@ SN7_APPLY_PRD:
 	POP	AF
 #ENDIF
 
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
-
 	LD	BC, SN76489_PORT16_LEFT
 	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
-
+#ENDIF
+#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT))
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
+#ENDIF
 
 #IFDEF SBCV2004
 	LD	A,(HB_RTCVAL)
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 3a90169d..805c8d42 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -242,6 +242,12 @@ SNMODE_RC	.EQU	1		; RCBUS SOUND MODULE
 SNMODE_VGM	.EQU	2		; VGM ECB BOARD
 SNMODE_DUO	.EQU	3		; DUODYNE MEDIA-IO BOARD
 ;
+; SN SOUND MODULE CHANNEL SELECTION
+;
+SNCHAN_BOTH	.EQU	0		; BOTH LEFT & RIGHT CHANNELS GET SAME OUTPUT
+SNCHAN_LEFT	.EQU	1		; LEFT CHANNEL ONLY
+SNCHAN_RIGHT	.EQU	2		; RIGHT CHANNEL ONLY
+;
 ; TMS VIDEO MODE SELECTIONS
 ;
 TMSMODE_NONE	.EQU	0

From 37e682adc7ede54dc0b086d19c3872159ebfa7e3 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 25 Jul 2024 11:28:30 +1000
Subject: [PATCH 39/62] ez80: some general improvements to ez80 HBIOS drivers
 and implemented a true interrupt driver timer tick driver

---
 Source/HBIOS/Config/RCEZ80_std.asm |   6 +-
 Source/HBIOS/cfg_rcez80.asm        |   4 +
 Source/HBIOS/ez80cpudrv.asm        |  76 +++++++++++
 Source/HBIOS/ez80instr.inc         |  19 +--
 Source/HBIOS/ez80rtc.asm           |   2 +-
 Source/HBIOS/ez80systmr.asm        |  81 ++++++++++++
 Source/HBIOS/ez80uart.asm          |   3 +
 Source/HBIOS/hbios.asm             | 205 +++++++++++------------------
 Source/HBIOS/std.asm               |   6 +
 Source/HBIOS/tms.asm               |   2 -
 10 files changed, 259 insertions(+), 145 deletions(-)
 create mode 100644 Source/HBIOS/ez80cpudrv.asm
 create mode 100644 Source/HBIOS/ez80systmr.asm

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index a5245967..b015b6a8 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -33,13 +33,10 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
-EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
-;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-EZ80UARTENABLE	.SET	TRUE		; EZ80UART: ENABLE EZ80 UART DRIVER (EZ80UART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
@@ -67,5 +64,8 @@ IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 
+EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
+EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
+EZ80TIMER	.SET	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
 EZ80_IO_FREQ	.SET	5250
 EZ80_MEM_FREQ	.SET	8000
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index c36f6efc..12a0eddb 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -130,6 +130,10 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 EZ80RTCENABLE	.EQU	TRUE		; EZ80 ON CHIP RTC
 ;
+EZ80TMR_INT	.EQU	1		; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
+EZ80TMR_FIRM	.EQU	2		; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
+EZ80TIMER	.EQU	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
 RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
new file mode 100644
index 00000000..1570cdab
--- /dev/null
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -0,0 +1,76 @@
+;
+;==================================================================================================
+; EZ80 50/60HZ TIMER TICK DRIVER
+;==================================================================================================
+;
+; Communicate with on-chip eZ80 firmware to:
+; 1. Exchange platform version numbers
+; 2. Configure memory banking type
+; 3. Retrieve CPU Frequency
+; 4. Set Memory and I/O Bus Timings
+; 5. Set Timer Tick Frequency
+;
+EZ80_PREINIT:
+	EZ80_TMR_INT_DISABLE()
+
+	; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
+	LD	C, 1			; RomWBW'S ASSIGNED CODE
+	LD	D, RMJ
+	LD	E, RMN
+	LD	H, RUP
+	LD	L, RTP
+
+	EZ80_UTIL_VER_EXCH()
+	; TODO CHECK RETURNED VERSION AND WARN IF NOT GOOD
+	; EXPECT A VERSION NUMBER > 0.1.0.0
+
+	LD	C, MEMMGR
+	LD	HL, ROMSIZE
+	LD	DE, RAMSIZE
+	EZ80_UTIL_BNK_HLP()		; INSTAL HIGH PERFORMANCE BANK SWITCHER
+	; TODO CHECK RESULT AND USE STANDARD BANK SWITCHER IF NZ RETURNED
+	; OTHERWISE USE RST.L  %18 FOR BANK SWITCH HELPER
+
+	EZ80_UTIL_GET_CPU_FQ()
+	LD	A, E
+	LD	(CB_CPUMHZ), A
+	LD	(CB_CPUKHZ), HL
+	LD	(HB_CPUOSC), HL
+
+#IF (EZ80_ASSIGN == 1)
+	LD	H, EZ80_MEM_CYCLES
+	LD	L, EZ80_IO_CYCLES
+	EZ80_UTIL_SET_BUSTM()
+#ELSE
+	LD	HL, EZ80_MEM_FREQ
+	LD	DE, EZ80_IO_FREQ
+	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
+#ENDIF
+	LD	A, H
+	LD	(EZ80_PLT_C3CYL), A
+	LD	A, L
+	LD	(EZ80_PLT_C2CYL), A
+
+	LD	C, TICKFREQ
+	EZ80_TMR_SET_FREQTICK
+
+	LD	A, 5			; HB_CPUTYPE = 5 FOR eZ80
+	LD	(HB_CPUTYPE),A
+	RET
+
+EZ80_RPT_TIMINGS:
+	LD	A,(EZ80_PLT_C3CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM B/C, $"
+
+	LD	A,(EZ80_PLT_C2CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" I/O B/C$"
+	RET
+
+EZ80_PLT_C3CYL:
+	.DB	EZ80_MEM_CYCLES
+EZ80_PLT_C2CYL:
+	.DB	EZ80_IO_CYCLES
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 35037033..6282eca5 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -27,14 +27,17 @@
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_RTC_SET_TIME 	LD A, 1	\ LD B, 2 \ EZ80_FN
 
-  #DEFINE EZ80_TMR_GET_TICKS	LD A, 2 \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_TMR_GET_SECONDS	LD A, 2 \ LD B, 1 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_TICKS	LD A, 2 \ LD B, 2 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B, 3 \ EZ80_FN
-  #DEFINE EZ80_TMR_GET_FREQTICK	LD A, 2 \ LD B, 4 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_FREQTICK	LD A, 2 \ LD B, 5 \ EZ80_FN
-  #DEFINE EZ80_TMR_DELAY_START	LD A, 2 \ LD B, 6 \ EZ80_FN
-  #DEFINE EZ80_TMR_DELAY_WAIT	LD A, 2 \ LD B, 7 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_TICKS	LD A, 2 \ LD B,  0 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_SECONDS	LD A, 2 \ LD B,  1 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_TICKS	LD A, 2 \ LD B,  2 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B,  3 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_FREQTICK	LD A, 2 \ LD B,  4 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_FREQTICK	LD A, 2 \ LD B,  5 \ EZ80_FN
+  #DEFINE EZ80_TMR_DELAY_START	LD A, 2 \ LD B,  6 \ EZ80_FN
+  #DEFINE EZ80_TMR_DELAY_WAIT	LD A, 2 \ LD B,  7 \ EZ80_FN
+  #DEFINE EZ80_TMR_INT_DISABLE	LD A, 2 \ LD B,  8 \ EZ80_FN
+  #DEFINE EZ80_TMR_INT_ENABLE	LD A, 2 \ LD B,  9 \ EZ80_FN
+  #DEFINE EZ80_TMR_IS_TICK_ISR	LD A, 2 \ LD B, 10 \ EZ80_FN
 
   #DEFINE EZ80_DELAY_START(p,store) \
   #DEFCONT \ PUSH AF
diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index 78fae96f..2625c278 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -18,7 +18,7 @@ EZ80RTC_INIT:
 	RET	NZ			; IF ALREADY ACTIVE, ABORT
 
 	CALL	NEWLINE			; FORMATTING
-	PRTS("EZ80 RTC: ON-CHIP $")
+	PRTS("EZ80 RTC: POWERED $")
 
 	EZ80_RTC_INIT()
 	JR	Z, RTC_POWERED
diff --git a/Source/HBIOS/ez80systmr.asm b/Source/HBIOS/ez80systmr.asm
new file mode 100644
index 00000000..dde6f072
--- /dev/null
+++ b/Source/HBIOS/ez80systmr.asm
@@ -0,0 +1,81 @@
+;
+;==================================================================================================
+; EZ80 50/60HZ TIMER TICK DRIVER
+;==================================================================================================
+;
+; Configuration options:
+; EZ80TIMER:
+;   0 -> No timer tick interrupts MARSHALLED to HBIOS.
+;	 HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented here and DELEGATED to eZ80 firmware functions
+;   1 -> Timer tick interrupts MARSHALLED to HBIOS.
+;	 HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented within HBIOS
+;
+
+#IF (EZ80TIMER == EZ80TMR_INT)
+EZ80_TMR_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("EZ80 TIMER: INTERRUPTS ENABLED$")
+
+	LD	HL,EZ80_TMR_INT		; GET INT VECTOR
+	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
+
+	EZ80_TMR_INT_ENABLE()		; INSTALL TIMER HOOK
+	RET
+
+EZ80_TMR_INT:
+	EZ80_TMR_IS_TICK_ISR()
+	RET	Z			; NOT A EZ80 TIMER TICK
+
+	CALL	HB_TIMINT		; RETURN NZ - HANDLED
+	OR	$FF
+	RET
+#ELSE
+
+EZ80_TMR_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("EZ80 TIMER: FIRMWARE$")
+	RET
+; -----------------------------------------------
+; Implementation of HBIOS SYS TIMER functions to
+; delegate to eZ80 firmware functions
+
+; GET TIMER
+;   RETURNS:
+;     DE:HL: TIMER VALUE (32 BIT)
+;
+SYS_GETTIMER:
+	EZ80_TMR_GET_TICKS()
+	RET
+;
+; GET SECONDS
+;   RETURNS:
+;     DE:HL: SECONDS VALUE (32 BIT)
+;     C: NUM TICKS WITHIN CURRENT SECOND
+;
+SYS_GETSECS:
+	EZ80_TMR_GET_SECONDS()
+
+	EZ80_UTIL_HL_TO_EHL()		; E:HL{15:0} <- HL{23:0}
+	LD	D, 0
+	RET
+;
+; SET TIMER
+;   ON ENTRY:
+;     DE:HL: TIMER VALUE (32 BIT)
+;
+SYS_SETTIMER:
+	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+	EZ80_TMR_SET_TICKS()
+	RET
+;
+; SET SECS
+;   ON ENTRY:
+;     DE:HL: SECONDS VALUE (32 BIT)
+;
+SYS_SETSECS:
+	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+
+	EZ80_TMR_SET_SECONDS()
+	RET
+
+#ENDIF
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index abc7e104..cfc624e0 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -44,6 +44,9 @@ EZUART_PREINIT:
 	RET
 
 EZUART_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("EZ80 UART: UART0$")
+
 	XOR	A
 	RET
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 5e9285d1..f3a066c2 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2135,86 +2135,6 @@ HB_CLRIVT_Z:
 ;
 	LD	HL,0		; L = 0 MEANS Z80
 ;
-
-#IF (CPUFAM == CPU_EZ80)
-
-; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
-	LD	C, 1			; RomWBW'S ASSIGNED CODE
-	LD	D, RMJ
-	LD	E, RMN
-	LD	H, RUP
-	LD	L, RTP
-
-	EZ80_UTIL_VER_EXCH()
-	; TODO CHECK RETURNED VERSION AND WARN IF NOT GOOD
-	; EXPECT A VERSION NUMBER > 0.1.0.0
-
-	LD	C, MEMMGR
-	LD	HL, ROMSIZE
-	LD	DE, RAMSIZE
-	EZ80_UTIL_BNK_HLP()		; INSTAL HIGH PERFORMANCE BANK SWITCHER
-	; TODO CHECK RESULT AND USE STANDARD BANK SWITCHER IF NZ RETURNED
-	; OTHERWISE USE RST.L  %18 FOR BANK SWITCH HELPER
-
-	EZ80_UTIL_GET_CPU_FQ()
-	LD	A, E
-	LD	(CB_CPUMHZ), A
-	LD	(CB_CPUKHZ), HL
-	LD	(HB_CPUOSC), HL
-
-#IF (EZ80_ASSIGN == 1)
-
-	LD	H, EZ80_MEM_CYCLES
-	LD	L, EZ80_IO_CYCLES
-	EZ80_UTIL_SET_BUSTM()
-#ELSE
-	LD	HL, EZ80_MEM_FREQ
-	LD	DE, EZ80_IO_FREQ
-	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
-#ENDIF
-	LD	A, H
-	LD	(EZ80_PLT_C3CYL), A
-	LD	A, L
-	LD	(EZ80_PLT_C2CYL), A
-
-	LD	C, TICKFREQ
-	EZ80_TMR_SET_FREQTICK
-
-	LD	HL, 5			; HB_CPUTYPE = 5 FOR eZ80
-
-	JR	PLT_DESCR_END
-
-PLT_DESCR:
-EZ80_PLT_EZ80VER:
-	.DB	RMJ
-	.DB	RMN
-	.DB	RUP
-	.DB	RTP
-EZ80_PLT_CPUOSC:
-	.DW	CPUOSC & $FFFF
-	.DW	CPUOSC >> 16
-EZ80_PLT_CPUMHZ:
-	.DB	PLATFORM
-EZ80_PLT_CPUKHZ:
-	.DB	MEMMGR
-	.DB	RAMSIZE & $FF
-EZ80_PLT_CHIP_ID:
-	.DB	RAMSIZE >> 8
-EZ80_PLT_RESVRD:
-	.DB	ROMSIZE & $FF
-	.DB	ROMSIZE >> 8
-	.DB	0 		; RESERVED
-	.DB	0 		; RESERVED
-
-EZ80_PLT_C3CYL:
-	.DB	EZ80_MEM_CYCLES
-EZ80_PLT_C2CYL:
-	.DB	EZ80_IO_CYCLES
-
-PLT_DESCR_END:
-
-#ENDIF
-;
 #IF (CPUFAM == CPU_Z180)
 ;
 	; TEST FOR ORIGINAL Z180 USING MLT
@@ -2265,6 +2185,10 @@ HB_CPU1:
 ; SOME DRIVERS NEED TO BE CALLED AS EARLY AS WE CAN ONE AN OPERATING
 ; ENVIRONMENT IS ESTABLISHED.
 ;
+#IF (CPUFAM == CPU_EZ80)
+	; THIS WILL RE-ASSIGN HB_CPUTYPE
+	CALL	EZ80_PREINIT
+#ENDIF
 #IF (SN76489ENABLE)
 	; SN76489 CHIP GENERATES UGLY NOISE AFTER HARDWARE RESET.
 	; WE CALL THIS DRIVER'S PREINIT ASAP TO SHUT OFF THE NOISE.
@@ -3004,10 +2928,7 @@ HB_Z280BUS1:
 ; DISPLAY MEMORY TIMINGS
 ;
 #IF (CPUFAM == CPU_EZ80)
-	LD	A,(EZ80_PLT_C3CYL)
-	CALL	PRTDECB
-	CALL	PRTSTRD
-	.TEXT	" MEM B/C, $"
+	CALL	EZ80_RPT_TIMINGS
 
 #ELSE
 #IF (CPUFAM == CPU_Z280)
@@ -3033,11 +2954,7 @@ HB_Z280BUS1:
 ; DISPLAY I/O TIMINGS
 ;
 #IF (CPUFAM == CPU_EZ80)
-	LD	A,(EZ80_PLT_C2CYL)
-	CALL	PRTDECB
-	CALL	PRTSTRD
-	.TEXT	" I/O B/C$"
-
+	; ALREADY REPORTED BY DRIVER
 #ELSE
 	LD	A,1
 #IF (CPUFAM == CPU_Z180)
@@ -3848,6 +3765,10 @@ HB_INITTBL:
 #IF (EZ80RTCENABLE)
 	.DW	EZ80RTC_INIT
 #ENDIF
+#IF (CPUFAM == CPU_EZ80)
+	; INITALISE ONE OF THE SUPPORTED SYSTEM TIMER TICKS DRIVERS
+	.DW	EZ80_TMR_INIT
+#ENDIF
 #IF (VDUENABLE)
 	.DW	VDU_INIT
 #ENDIF
@@ -5119,16 +5040,16 @@ SYS_GETFN:
 	POP	DE			; ... TO DE
 	RET				; AF STILL HAS RESULT OF CALC
 ;
+#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM))
+; IMPLEMENTED IN EZ80DRV.ASM
+;
+#ELSE
+;
 ; GET TIMER
 ;   RETURNS:
 ;     DE:HL: TIMER VALUE (32 BIT)
 ;
 SYS_GETTIMER:
-#IF (CPUFAM == CPU_EZ80)
-	EZ80_TMR_GET_TICKS()
-	RET
-
-#ELSE
 	LD	HL,HB_TICKS
 	HB_DI
 	CALL	LD32
@@ -5137,7 +5058,11 @@ SYS_GETTIMER:
 	XOR	A
 	RET
 #ENDIF
-
+;
+#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM))
+; IMPLEMENTED IN EZ80DRV.ASM
+;
+#ELSE
 ;
 ; GET SECONDS
 ;   RETURNS:
@@ -5145,14 +5070,6 @@ SYS_GETTIMER:
 ;     C: NUM TICKS WITHIN CURRENT SECOND
 ;
 SYS_GETSECS:
-#IF (CPUFAM == CPU_EZ80)
-	EZ80_TMR_GET_SECONDS()
-
-	EZ80_UTIL_HL_TO_EHL()		; E:HL{15:0} <- HL{23:0}
-	LD	D, 0
-	RET
-
-#ELSE
 	LD	HL,HB_SECS
 	HB_DI
 	CALL	LD32
@@ -5366,16 +5283,16 @@ SYS_SETBOOTINFO:
 	XOR	A
 	RET
 ;
+#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM))
+; IMPLEMENTED IN EZ80DRV.ASM
+;
+#ELSE
+;
 ; SET TIMER
 ;   ON ENTRY:
 ;     DE:HL: TIMER VALUE (32 BIT)
 ;
 SYS_SETTIMER:
-#IF (CPUFAM == CPU_EZ80)
-	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
-	EZ80_TMR_SET_TICKS()
-	RET
-#ELSE
 	LD	BC,HB_TICKS
 	HB_DI
 	CALL	ST32
@@ -5383,18 +5300,16 @@ SYS_SETTIMER:
 	XOR	A
 	RET
 #ENDIF
+#IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_FIRM))
+; IMPLEMENTED IN EZ80DRV.ASM
+;
+#ELSE
 ;
 ; SET SECS
 ;   ON ENTRY:
 ;     DE:HL: SECONDS VALUE (32 BIT)
 ;
 SYS_SETSECS:
-#IF (CPUFAM == CPU_EZ80)
-	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
-
-	EZ80_TMR_SET_SECONDS()
-	RET
-#ELSE
 	LD	BC,HB_SECS
 	HB_DI
 	CALL	ST32
@@ -8152,14 +8067,7 @@ SIZ_RP5RTC	.EQU	$ - ORG_RP5RTC
 		MEMECHO	SIZ_RP5RTC
 		MEMECHO	" bytes.\n"
 #ENDIF
-#IF (EZ80RTCENABLE)
-ORG_EZ80RTC	.EQU	$
-  #INCLUDE "ez80rtc.asm"
-SIZ_EZ80RTC	.EQU	$ - ORG_EZ80RTC
-		MEMECHO	"EZ80RTC occupies "
-		MEMECHO	SIZ_EZ80RTC
-		MEMECHO	" bytes.\n"
-#ENDIF
+;
 #IF (ASCIENABLE)
 ORG_ASCI	.EQU	$
   #INCLUDE "asci.asm"
@@ -8205,15 +8113,6 @@ SIZ_SIO		.EQU	$ - ORG_SIO
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (EZ80UARTENABLE)
-ORG_EZU	.EQU	$
-  #INCLUDE "ez80uart.asm"
-SIZ_EZU		.EQU	$ - ORG_EZU
-		MEMECHO	"EZ80 UART occupies "
-		MEMECHO	SIZ_EZU
-		MEMECHO	" bytes.\n"
-#ENDIF
-;
 #IF (ACIAENABLE)
 ORG_ACIA	.EQU	$
   #INCLUDE "acia.asm"
@@ -8560,6 +8459,50 @@ SIZ_YM2612	.EQU	$ - ORG_YM2612
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+;
+#IF (CPUFAM == CPU_EZ80)
+	MEMECHO	"EZ80 DRIVERS\n"
+ORG_EZ80DRVS	.EQU	$
+;
+ORG_EZ80CPUDRV	.EQU	$
+  #INCLUDE "ez80cpudrv.asm"
+SIZ_EZ80CPUDRV	.EQU	$ - ORG_EZ80CPUDRV
+		MEMECHO	"  EZ80 CPU DRIVER occupies "
+		MEMECHO	SIZ_EZ80CPUDRV
+		MEMECHO	" bytes.\n"
+;
+ORG_EZ80SYSTMR	.EQU	$
+  #INCLUDE "ez80systmr.asm"
+SIZ_EZ80SYSTMR	.EQU	$ - ORG_EZ80SYSTMR
+		MEMECHO	"  EZ80 SYS TIMER occupies "
+		MEMECHO	SIZ_EZ80SYSTMR
+		MEMECHO	" bytes.\n"
+;
+#IF (EZ80RTCENABLE)
+ORG_EZ80RTC	.EQU	$
+  #INCLUDE "ez80rtc.asm"
+SIZ_EZ80RTC	.EQU	$ - ORG_EZ80RTC
+		MEMECHO	"  EZ80 RTC occupies "
+		MEMECHO	SIZ_EZ80RTC
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
+#IF (EZ80UARTENABLE)
+ORG_EZU	.EQU	$
+  #INCLUDE "ez80uart.asm"
+SIZ_EZU		.EQU	$ - ORG_EZU
+		MEMECHO	"  EZ80 UART occupies "
+		MEMECHO	SIZ_EZU
+		MEMECHO	" bytes.\n"
+#ENDIF
+
+SIZ_EZ80DRVS	.EQU	$ - ORG_EZ80DRVS
+		MEMECHO	"  Total "
+		MEMECHO	SIZ_EZ80DRVS
+		MEMECHO	" bytes.\n"
+
+#ENDIF
+
 		MEMECHO	"RTCDEF="
 		MEMECHO	RTCDEF
 		MEMECHO	"\n"
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 805c8d42..9cc67735 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -609,6 +609,7 @@ TM_TMS	.EQU	2
 TM_SIMH	.EQU	3
 TM_Z180	.EQU	4
 TM_Z280	.EQU	5
+TM_EZ80	.EQU	6
 ;
 	SYSECHO "SYSTEM TIMER:"
 SYSTIM	.EQU	TM_NONE
@@ -647,6 +648,11 @@ SYSTIM	.SET	TM_Z280
 	SYSECHO	" Z280"
     #ENDIF
   #ENDIF
+;
+  #IF ((CPUFAM == CPU_EZ80) & (EZ80TIMER == EZ80TMR_INT))
+SYSTIM	.SET	TM_EZ80
+	SYSECHO	" EZ80"
+  #ENDIF
 ;
   #IF SYSTIM == TM_NONE
 	SYSECHO " NONE"
diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index fd955b16..7546d53e 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -290,12 +290,10 @@ TMS_INIT1:
   #IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80))
 	; ENABLE VDP INTERRUPTS ON NABU INTERRUPT CONTROLLER
 	LD	A,14			; PSG R14 (PORT A DATA)
-	EZ80_IO
 	OUT	(NABU_RSEL),A		; SELECT IT
 	LD	A,(NABU_CTLVAL)		; GET NABU CTL PORT SHADOW REG
 	SET	4,A			; ENABLE VDP INTERRUPTS
 	LD	(NABU_CTLVAL),A		; UPDATE SHADOW REG
-	EZ80_IO
 	OUT	(NABU_RDAT),A		; WRITE TO HARDWARE
   #ENDIF
 ;

From 0eb0855948e816a17940b1d76fdb083752f169d9 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 25 Jul 2024 13:01:07 +1000
Subject: [PATCH 40/62] ez80: ported ay38910 driver

---
 Source/HBIOS/Config/RCEZ80_std.asm | 4 ++--
 Source/HBIOS/ay38910.asm           | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index b015b6a8..f8342440 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -48,9 +48,9 @@ VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
-AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
diff --git a/Source/HBIOS/ay38910.asm b/Source/HBIOS/ay38910.asm
index c0aeebeb..5fb150e2 100644
--- a/Source/HBIOS/ay38910.asm
+++ b/Source/HBIOS/ay38910.asm
@@ -575,8 +575,10 @@ AY_WRTPSG:
 	OUT0	(Z180_DCNTL),A		; AND UPDATE DCNTL
 #ENDIF
 	LD	A,D			; SELECT THE REGISTER WE
+	EZ80_IO
 	OUT	(AY_RSEL),A		; WANT TO WRITE TO
 	LD	A,E			; WRITE THE VALUE TO
+	EZ80_IO
 	OUT	(AY_RDAT),A		; THE SELECTED REGISTER
 #IF (CPUFAM == CPU_Z180)
 	POP	AF			; GET SAVED DCNTL VALUE
@@ -606,7 +608,9 @@ AY_RDPSG:
 	OUT0	(Z180_DCNTL),A		; AND UPDATE DCNTL
 #ENDIF
 	LD	A,D			; SELECT THE REGISTER WE
+	EZ80_IO
 	OUT	(AY_RSEL),A		; WANT TO READ
+	EZ80_IO
 	IN	A,(AY_RIN)		; READ SELECTED REGISTER
 	LD	E,A
 #IF (CPUFAM == CPU_Z180)

From 55d8c6ce7d18440d04f4fd1985830664d1e6e8b3 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 2 Aug 2024 16:52:26 +1000
Subject: [PATCH 41/62] ez80: ported ppide.asm driver

---
 Source/HBIOS/Config/RCEZ80_std.asm |  8 ++++--
 Source/HBIOS/ppide.asm             | 45 ++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index f8342440..f0620f12 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -30,7 +30,7 @@ CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -48,7 +48,7 @@ VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
-AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
@@ -56,7 +56,7 @@ FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
@@ -69,3 +69,5 @@ EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
 EZ80TIMER	.SET	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
 EZ80_IO_FREQ	.SET	5250
 EZ80_MEM_FREQ	.SET	8000
+EZ80_ASSIGN	.EQU	1		; 0 -> USE FREQ, 1 -> USE CYCLES
+EZ80_IO_CYCLES	.EQU	5		; EZ80 CYCLES FOR IO (1-15)
diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm
index de956828..246b74da 100644
--- a/Source/HBIOS/ppide.asm
+++ b/Source/HBIOS/ppide.asm
@@ -487,11 +487,14 @@ PPIDE_DETECT:
 ;
 	LD	A,PPIDE_DIR_WRITE	; SET DATA BUS DIRECTION TO WRITE
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 ;
 	LD	C,(IY+PPIDE_DATALO)	; PPI PORT A, DATALO
 	LD	A,$A5			; TEST VALUE
+	EZ80_IO
 	OUT	(C),A			; PUSH VALUE TO PORT
+	EZ80_IO
 	IN	A,(C)			; GET PORT VALUE
 #IF (PPIDETRACE >= 3)
 	CALL	PC_SPACE
@@ -1131,12 +1134,14 @@ PPIDE_GET:
 	LD	A,PPIDE_DIR_READ	; SET DATA BUS DIRECTION TO READ
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 ;
 	; SELECT READ/WRITE IDE REGISTER
 	LD	A,PPIDE_REG_DATA	; DATA REGISTER
 	;OUT	(PPIDE_REG_CTL),A	; DO IT
 	LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
+	EZ80_IO
 	OUT	(C),A			; DO IT
 	LD	E,A			; E := READ UNASSERTED
 	XOR	PPIDE_CTL_DIOR		; SWAP THE READ LINE BIT
@@ -1159,19 +1164,25 @@ PPIDE_GET2:
 ;
 PPIDE_GET8:	; 8 BIT WIDE READ LOOP
 	; ENTER W/ C = PPIDE_REG_CTL
+	EZ80_IO
 	OUT	(C),D			; ASSERT READ
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	INI				; READ FROM LSB
 	INC	C			; LSB -> MSB
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),E			; DEASSERT READ
+	EZ80_IO
 	OUT	(C),D			; ASSERT READ
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	INI				; READ FROM LSB
 	INC	C			; LSB -> MSB
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),E			; DEASSERT READ
 	DEC	A
 	JR	NZ,PPIDE_GET8		; LOOP UNTIL DONE
@@ -1179,13 +1190,17 @@ PPIDE_GET8:	; 8 BIT WIDE READ LOOP
 ;
 PPIDE_GET16:	; 16 BIT WIDE READ LOOP
 	; ENTER W/ C = PPIDE_REG_CTL
+	EZ80_IO
 	OUT	(C),D			; ASSERT READ
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	INI				; READ FROM LSB
 	INC	C			; LSB -> MSB
+	EZ80_IO
 	INI				; READ MSB FOR 16 BIT
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),E			; DEASSERT READ
 	DEC	A
 	JR	NZ,PPIDE_GET16		; LOOP UNTIL DONE
@@ -1217,12 +1232,14 @@ PPIDE_PUT:
 	LD	A,PPIDE_DIR_WRITE	; SET DATA BUS DIRECTION TO WRITE
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 ;
 	; SELECT READ/WRITE IDE REGISTER
 	LD	A,PPIDE_REG_DATA	; DATA REGISTER
 	;OUT	(PPIDE_REG_CTL),A	; DO IT
 	LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
+	EZ80_IO
 	OUT	(C),A			; DO IT
 	LD	E,A			; E := WRITE UNASSERTED
 	XOR	PPIDE_CTL_DIOW		; SWAP THE READ LINE BIT
@@ -1247,17 +1264,23 @@ PPIDE_PUT2:
 PPIDE_PUT8:	; 8 BIT WIDE WRITE LOOP
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	OUTI				; WRITE NEXT BYTE (LSB)
 	INC	C			; LSB -> MSB
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),D			; ASSERT WRITE
+	EZ80_IO
 	OUT	(C),E			; DEASSERT WRITE
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	OUTI				; WRITE NEXT BYTE (LSB)
 	INC	C			; LSB -> MSB
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),D			; ASSERT WRITE
+	EZ80_IO
 	OUT	(C),E			; DEASSERT WRITE
 	DEC	A
 	JR	NZ,PPIDE_PUT8		; LOOP UNTIL DONE
@@ -1266,11 +1289,15 @@ PPIDE_PUT8:	; 8 BIT WIDE WRITE LOOP
 PPIDE_PUT16:	; 16 BIT WIDE WRITE LOOP
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	OUTI				; WRITE NEXT BYTE (LSB)
 	INC	C			; LSB -> MSB
+	EZ80_IO
 	OUTI				; WRITE NEXT BYTE (MSB)
 	INC	C			; MSB -> CTL
+	EZ80_IO
 	OUT	(C),D			; ASSERT WRITE
+	EZ80_IO
 	OUT	(C),E			; DEASSERT WRITE
 	DEC	A
 	JR	NZ,PPIDE_PUT16		; LOOP UNTIL DONE
@@ -1320,6 +1347,7 @@ PPIDE_RESET:
 	LD	A,PPIDE_DIR_READ	; SET DATA BUS DIRECTION TO READ
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 ;
 ; IF A DSKYNG IS ACTIVE AND IS ON THE SAME PPI PORT AS THE PPIDE BEING
@@ -1348,11 +1376,13 @@ PPIDE_RESET:
 	LD	A,PPIDE_CTL_RESET
 	;OUT	(PPIDE_REG_CTL),A
 	LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
+	EZ80_IO
 	OUT	(C),A
 	LD	DE,20			; DELAY 320US (SPEC IS >= 25US)
 	CALL	VDELAY
 	XOR	A
 	;OUT	(PPIDE_REG_CTL),A
+	EZ80_IO
 	OUT	(C),A
 	LD	DE,20
 	CALL	VDELAY
@@ -1889,24 +1919,29 @@ PPIDE_IN:
 	LD	A,PPIDE_DIR_READ	; SET DATA BUS DIRECTION TO READ	; 7TS
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD			; 19TS
+	EZ80_IO
 	OUT	(C),A			; WRITE IT				; 12TS
 ;
 	LD	B,(HL)			; GET CTL PORT VALUE			; 7TS
 	;LD	C,PPIDE_REG_CTL		; SETUP PORT TO WRITE
 	;LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
 	DEC	C			; SET IDE ADDRESS			; 4TS
+	EZ80_IO
 	OUT	(C),B			; SET ADDRESS LINES			; 12TS
 	SET	6,B			; TURN ON READ BIT			; 8TS
+	EZ80_IO
 	OUT	(C),B			; ASSERT READ LINE			; 12TS
 ;
 	;IN	A,(PPIDE_REG_DATALO)	; GET DATA VALUE FROM DEVICE
 	DEC	C								; 4TS
 	DEC	C								; 4TS
+	EZ80_IO
 	IN	A,(C)			; GET DATA VALUE FROM DEVICE		; 12
 	INC	C								; 4TS
 	INC	C								; 4TS
 ;
 	RES	6,B			; CLEAR READ BIT			; 8TS
+	EZ80_IO
 	OUT	(C),B			; DEASSERT READ LINE			; 12TS
 	POP	BC			; RECOVER INCOMING BC			; 10TS
 	INC	HL			; POINT PAST PARM			; 6TS
@@ -1923,6 +1958,7 @@ PPIDE_OUT:
 	LD	A,PPIDE_DIR_WRITE	; SET DATA BUS DIRECTION TO WRITE
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 	POP	AF			; RECOVER VALUE TO WRITE
 ;
@@ -1930,18 +1966,22 @@ PPIDE_OUT:
 	;LD	C,PPIDE_REG_CTL		; SETUP PORT TO WRITE
 	;LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
 	DEC	C			; SET IDE ADDRESS
+	EZ80_IO
 	OUT	(C),B			; SET ADDRESS LINES
 	SET	5,B			; TURN ON WRITE BIT
+	EZ80_IO
 	OUT	(C),B			; ASSERT WRITE LINE
 ;
 	DEC	C
 	DEC	C
 	;OUT	(PPIDE_REG_DATALO),A	; SEND DATA VALUE TO DEVICE
+	EZ80_IO
 	OUT	(C),A			; SEND DATA VALUE TO DEVICE
 	INC	C
 	INC	C
 ;
 	RES	5,B			; CLEAR WRITE BIT
+	EZ80_IO
 	OUT	(C),B			; DEASSERT WRITE LINE
 	POP	BC			; RECOVER INCOMING BC
 	INC	HL			; POINT PAST PARM
@@ -2084,6 +2124,7 @@ PPIDE_REGDUMP:
 	LD	A,PPIDE_DIR_READ	; SET DATA BUS DIRECTION TO READ
 	;OUT	(PPIDE_REG_PPI),A	; DO IT
 	LD	C,(IY+PPIDE_PPI)	; PPI CONTROL WORD
+	EZ80_IO
 	OUT	(C),A			; WRITE IT
 	LD	C,(IY+PPIDE_CTL)	; SET IDE ADDRESS
 	LD	E,PPIDE_REG_CMD
@@ -2091,19 +2132,23 @@ PPIDE_REGDUMP:
 PPIDE_REGDUMP1:
 	LD	A,E			; REGISTER ADDRESS
 	;OUT	(PPIDE_REG_CTL),A	; SET IT
+	EZ80_IO
 	OUT	(C),A			; REGISTER ADDRESS
 	XOR	PPIDE_CTL_DIOR		; SET BIT TO ASSERT READ LINE
 	;OUT	(PPIDE_REG_CTL),A	; ASSERT READ
+	EZ80_IO
 	OUT	(C),A			; ASSERT READ
 	;IN	A,(PPIDE_REG_DATALO)	; GET VALUE
 	DEC	C			; CTL -> MSB
 	DEC	C			; MSB -> LSB
+	EZ80_IO
 	IN	A,(C)			; GET VALUE
 	INC	C			; LSB -> MSB
 	INC	C			; MSB -> CTL
 	CALL	PRTHEXBYTE		; DISPLAY IT
 	;LD	A,C			; RELOAD ADDRESS W/ READ UNASSERTED
 	;OUT	(PPIDE_REG_CTL),A	; AND SET IT
+	EZ80_IO
 	OUT	(C),E			; RELOAD ADDRESS W/ READ UNASSERTED
 	;DEC	C			; NEXT LOWER REGISTER
 	DEC	E			; NEXT LOWER REGISTER

From 9898309f292d66edd1a2a7ca0cadaf4e4fe31114 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 3 Aug 2024 13:33:28 +1000
Subject: [PATCH 42/62] ez80: ported fd.asm driver

---
 Source/HBIOS/Config/RCEZ80_std.asm |  8 +---
 Source/HBIOS/cfg_rcez80.asm        |  6 +--
 Source/HBIOS/ez80instr.inc         | 72 ++++++++++++++++++------------
 Source/HBIOS/fd.asm                | 36 +++++++--------
 Source/HBIOS/hbios.asm             | 36 +++++++++++++++
 Source/HBIOS/sn76489.asm           | 16 +++----
 6 files changed, 110 insertions(+), 64 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index f0620f12..3f178e68 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -26,7 +26,7 @@
 ;
 #include "cfg_rcez80.asm"
 ;
-CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
@@ -52,7 +52,7 @@ AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
@@ -67,7 +67,3 @@ PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
 EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
 EZ80TIMER	.SET	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
-EZ80_IO_FREQ	.SET	5250
-EZ80_MEM_FREQ	.SET	8000
-EZ80_ASSIGN	.EQU	1		; 0 -> USE FREQ, 1 -> USE CYCLES
-EZ80_IO_CYCLES	.EQU	5		; EZ80 CYCLES FOR IO (1-15)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 12a0eddb..0ab3f277 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -46,11 +46,11 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
 EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
-EZ80_MEM_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_MEM_FREQ	.EQU	16000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
-EZ80_IO_CYCLES	.EQU	3		; EZ80 CYCLES FOR IO (1-15)
-EZ80_IO_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_IO_CYCLES	.EQU	4		; EZ80 CYCLES FOR IO (1-15)
+EZ80_IO_FREQ	.EQU	5250		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
 ;
 ; SELECT CYCLES, OR CALCULATE CYCLES BASED ON DESIRED FREQUENCY
 EZ80_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 6282eca5..4d495a3b 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -14,32 +14,33 @@
   ; RST.L $18
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF
 
-  #DEFINE EZ80_UTIL_VER_EXCH	XOR A \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
-  #DEFINE EZ80_UTIL_HL_TO_EHL	XOR A \ LD B, 2 \ EZ80_FN
-  #DEFINE EZ80_UTIL_SET_BUSTM 	XOR A \ LD B, 3 \ EZ80_FN
-  #DEFINE EZ80_UTIL_SET_BUSFQ 	XOR A \ LD B, 4 \ EZ80_FN
-  #DEFINE EZ80_UTIL_GET_CPU_FQ 	XOR A \ LD B, 5 \ EZ80_FN
-  #DEFINE EZ80_UTIL_BNK_HLP 	XOR A \ LD B, 6 \ EZ80_FN
-  #DEFINE EZ80_UTIL_DEBUG 	XOR A \ LD B, 7 \ EZ80_FN
-
-  #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
-  #DEFINE EZ80_RTC_SET_TIME 	LD A, 1	\ LD B, 2 \ EZ80_FN
-
-  #DEFINE EZ80_TMR_GET_TICKS	LD A, 2 \ LD B,  0 \ EZ80_FN
-  #DEFINE EZ80_TMR_GET_SECONDS	LD A, 2 \ LD B,  1 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_TICKS	LD A, 2 \ LD B,  2 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_SECONDS	LD A, 2 \ LD B,  3 \ EZ80_FN
-  #DEFINE EZ80_TMR_GET_FREQTICK	LD A, 2 \ LD B,  4 \ EZ80_FN
-  #DEFINE EZ80_TMR_SET_FREQTICK	LD A, 2 \ LD B,  5 \ EZ80_FN
-  #DEFINE EZ80_TMR_DELAY_START	LD A, 2 \ LD B,  6 \ EZ80_FN
-  #DEFINE EZ80_TMR_DELAY_WAIT	LD A, 2 \ LD B,  7 \ EZ80_FN
-  #DEFINE EZ80_TMR_INT_DISABLE	LD A, 2 \ LD B,  8 \ EZ80_FN
-  #DEFINE EZ80_TMR_INT_ENABLE	LD A, 2 \ LD B,  9 \ EZ80_FN
-  #DEFINE EZ80_TMR_IS_TICK_ISR	LD A, 2 \ LD B, 10 \ EZ80_FN
-
-  #DEFINE EZ80_DELAY_START(p,store) \
+  #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_EHL_TO_HL		XOR A \ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_UTIL_HL_TO_EHL		XOR A \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
+  #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
+  #DEFINE EZ80_UTIL_BNK_HLP 		XOR A \ LD B, 6 \ EZ80_FN
+  #DEFINE EZ80_UTIL_DEBUG 		XOR A \ LD B, 7 \ EZ80_FN
+
+  #DEFINE EZ80_RTC_INIT 		LD A, 1 \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_RTC_GET_TIME 		LD A, 1	\ LD B, 1 \ EZ80_FN
+  #DEFINE EZ80_RTC_SET_TIME 		LD A, 1	\ LD B, 2 \ EZ80_FN
+
+  #DEFINE EZ80_TMR_GET_TICKS		LD A, 2 \ LD B,  0 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_SECONDS		LD A, 2 \ LD B,  1 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_TICKS		LD A, 2 \ LD B,  2 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_SECONDS		LD A, 2 \ LD B,  3 \ EZ80_FN
+  #DEFINE EZ80_TMR_GET_FREQTICK		LD A, 2 \ LD B,  4 \ EZ80_FN
+  #DEFINE EZ80_TMR_SET_FREQTICK		LD A, 2 \ LD B,  5 \ EZ80_FN
+  #DEFINE EZ80_TMR_THROTTLE_START	LD A, 2 \ LD B,  6 \ EZ80_FN
+  #DEFINE EZ80_TMR_THROTTLE_WAIT	LD A, 2 \ LD B,  7 \ EZ80_FN
+  #DEFINE EZ80_TMR_INT_DISABLE		LD A, 2 \ LD B,  8 \ EZ80_FN
+  #DEFINE EZ80_TMR_INT_ENABLE		LD A, 2 \ LD B,  9 \ EZ80_FN
+  #DEFINE EZ80_TMR_IS_TICK_ISR		LD A, 2 \ LD B, 10 \ EZ80_FN
+  #DEFINE EZ80_TMR_DELAY		LD A, 2 \ LD B, 11 \ EZ80_FN
+
+  #DEFINE EZ80_THROTTLE_START(p,store) \
   #DEFCONT \ PUSH AF
   #DEFCONT \ PUSH BC
   #DEFCONT \ PUSH HL
@@ -51,7 +52,7 @@
   #DEFCONT \ POP BC
   #DEFCONT \ POP AF
 
-  #DEFINE EZ80_DELAY_WAIT(p,store) \
+  #DEFINE EZ80_THROTTLE_WAIT(p,store) \
   #DEFCONT \ PUSH AF
   #DEFCONT \ PUSH BC
   #DEFCONT \ PUSH HL
@@ -106,12 +107,25 @@
 
 IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
 
+  #DEFINE OUT_NN_A(addr) \
+  #DEFCONT \ PUSH	BC
+  #DEFCONT \ LD	BC, IO_SEGMENT << 8 | addr
+  #DEFCONT \ OUT	(C), A
+  #DEFCONT \ POP	BC
+
+  #DEFINE IN_A_NN(addr) \
+  #DEFCONT \ LD A, IO_SEGMENT
+  #DEFCONT \ IN A, (addr)
+
 #ELSE
   #DEFINE EZ80_IO
 
-  #DEFINE EZ80_DELAY_START(p,store)
-  #DEFINE EZ80_DELAY_WAIT(p,store)
+  #DEFINE EZ80_THROTTLE_START(p,store)
+  #DEFINE EZ80_THROTTLE_WAIT(p,store)
 
 IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
 
+  #DEFINE OUT_NN_A(addr) OUT (addr), A
+  #DEFINE IN_A_NN(addr)  IN A, (addr)
+
 #ENDIF
diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm
index 5888f4a1..8092fad0 100644
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@@ -883,15 +883,15 @@ FD_DETECT:
 	LD	(FST_DOR),A	; AND PUT IN SHADOW REGISTER
 	CALL	FC_RESETFDC	; RESET FDC
 	
-	IN	A,(FDC_MSR)	; READ MSR
+	IN_A_NN(FDC_MSR)	; READ MSR
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
 	
 	CP	$D0		; SPECIAL CASE: DATA PENDING?
 	JR	NZ,FD_DETECT1	; NOPE, MOVE ALONG
-	IN	A,(FDC_DATA)	; SWALLOW THE PENDING DATA
+	IN_A_NN(FDC_DATA)	; SWALLOW THE PENDING DATA
 	CALL	DLY32		; SETTLE
-	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
+	IN_A_NN(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
 
@@ -902,7 +902,7 @@ FD_DETECT1:
 	; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
 	; DESIRED VALUE, SO TRY ONE MORE TIME
 	CALL	DLY32		; WAIT A BIT
-	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
+	IN_A_NN(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
 	CP	$80		; CHECK FOR CORRECT VALUE
@@ -1452,7 +1452,7 @@ FC_SETUPSPECIFY:
 ;
 FC_SETDOR:
 	LD	(FST_DOR),A
-	OUT	(FDC_DOR),A
+	OUT_NN_A(FDC_DOR)
 #IF (FDTRACE >= 3)
 	CALL	NEWLINE
 	LD	DE,FDSTR_DOR
@@ -1471,7 +1471,7 @@ FC_SETDOR:
 ;
 FC_SETDCR
 	LD	(FST_DCR),A
-	OUT	(FDC_DCR),A
+	OUT_NN_A(FDC_DCR)
 #IF (FDTRACE >= 3)
 	CALL	NEWLINE
 	LD	DE,FDSTR_DCR
@@ -1644,11 +1644,11 @@ FOP:
 	LD	B,0			; B IS LOOP COUNTER
 FOP_CLR1:
 	CALL	DELAY			; FDC MAY TAKE UP TO 12us TO UPDATE MSR
-	IN	A,(FDC_MSR)		; GET STATUS
+	IN_A_NN(FDC_MSR)		; GET STATUS
 	AND	0C0H			; ISOLATE HIGH NIBBLE, RQM/DIO/NDM/CB
 	CP	0C0H			; LOOKING FOR RQM=1, DIO=1, BYTES PENDING
 	JR	NZ,FOP_CMD1		; NO BYTES PENDING, GO TO NEXT PHASE
-	IN	A,(FDC_DATA)		; GET THE PENDING BYTE AND DISCARD
+	IN_A_NN(FDC_DATA)		; GET THE PENDING BYTE AND DISCARD
 	DJNZ	FOP_CLR1
 	JP	FOP_TOFDCRDY		; OTHERWISE, TIMEOUT
 ;
@@ -1664,7 +1664,7 @@ FOP_CMD2:	; START OF LOOP TO SEND NEXT BYTE
 
 FOP_CMD4:	; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE
 	CALL	DELAY			; FDC MAY TAKE UP TO 12us TO UPDATE MSR
-	IN	A,(FDC_MSR)		; READ MAIN STATUS REGISTER
+	IN_A_NN(FDC_MSR)		; READ MAIN STATUS REGISTER
 	AND	0C0H			; ISOLATE RQM/DIO
 	CP	080H			; LOOKING FOR RQM=1, DIO=0 (FDC READY FOR A BYTE)
 	JR	Z,FOP_CMD6		; GOOD, GO TO SEND BYTE
@@ -1675,7 +1675,7 @@ FOP_CMD4:	; START OF STATUS LOOP, WAIT FOR FDC TO BE READY FOR BYTE
 
 FOP_CMD6:	; SEND NEXT BYTE
 	LD	A,(HL)			; POINT TO NEXT BYTE TO SEND
-	OUT	(FDC_DATA),A		; PUSH IT TO FDC
+	OUT_NN_A(FDC_DATA)		; PUSH IT TO FDC
 	INC	HL			; INCREMENT POINTER FOR NEXT TIME
 	DEC	D			; DECREMENT NUM BYTES LEFT TO SEND
 	JR	NZ,FOP_CMD2		; DO NEXT BYTE
@@ -1706,7 +1706,7 @@ FXR_NULL:
 	LD	BC,$7000		; LOOP COUNTER, $7000 * 16us = ~485ms
 FXR_NULL1:
 	CALL	DELAY			; FDC MAY TAKE UP TO 12us TO UPDATE MSR
-	IN	A,(FDC_MSR)		; GET MSR
+	IN_A_NN(FDC_MSR)		; GET MSR
 	AND	0E0H			; ISOLATE RQM/DIO/NDM
 	CP	0C0H			; WE WANT RQM=1,DIO=1,NDM=0 (READY TO READ A BYTE W/ EXEC INACTIVE)
 	JP	Z,FOP_RES		; EXEC DONE, EXIT CLEAN W/O PULSING TC
@@ -1737,13 +1737,13 @@ FXR_READ:
 	LD	(FCD_TO),A		; INIT TIMEOUT COUNTER
 FXRR1	LD	C,0			; OUTER LOOP TIMEOUT COUNTER
 FXRR2:	LD	B,0			; SETUP FOR 256 ITERATIONS
-FXRR3:	IN	A,(FDC_MSR)		; GET MSR
+FXRR3:	IN_A_NN(FDC_MSR)		; GET MSR
 	CP	0F0H			; WE WANT RQM=1,DIO=1,NDM=1,BUSY=1 (READY TO RECEIVE A BYTE W/ EXEC ACTIVE)
 	JR	Z,FXRR4			; GOT IT, DO BYTE READ
 	DJNZ	FXRR3			; NOT READY, LOOP IF COUNTER NOT ZERO
 	JR	FXRR5			; COUNTER ZERO, GO TO OUTER LOOP LOGIC
 
-FXRR4:	IN	A,(FDC_DATA)		; GET PENDING BYTE
+FXRR4:	IN_A_NN(FDC_DATA)		; GET PENDING BYTE
 	LD	(HL),A			; STORE IT IN BUFFER
 	INC	HL			; INCREMENT THE BUFFER POINTER
 	DEC	DE			; DECREMENT BYTE COUNT
@@ -1780,13 +1780,13 @@ FXR_WRITE:
 	LD	(FCD_TO),A
 FXRW1	LD	C,0			; OUTER LOOP TIMEOUT COUNTER
 FXRW2:	LD	B,0			; SETUP FOR 256 ITERATIONS
-FXRW3:	IN	A,(FDC_MSR)		; GET MSR
+FXRW3:	IN_A_NN(FDC_MSR)		; GET MSR
 	CP	0B0H			; WE WANT RQM=1,DIO=0,NDM=1,BUSY=1 (READY TO SEND A BYTE W/ EXEC ACTIVE)
 	JR	Z,FXRW4			; GOT IT, DO BYTE WRITE
 	DJNZ	FXRW3			; NOT READY, LOOP IF COUNTER NOT ZERO
 	JR	FXRW5			; COUNTER ZERO, GO TO OUTER LOOP LOGIC
 FXRW4:	LD	A,(HL)			; GET NEXT BYTE TO WRITE
-	OUT	(FDC_DATA),A		; WRITE IT
+	OUT_NN_A(FDC_DATA)		; WRITE IT
 	INC	HL			; INCREMENT THE BUFFER POINTER
 	DEC	DE			; DECREMENT LOOP COUNTER
 	LD	A,D
@@ -1830,7 +1830,7 @@ FOP_RES0:
 
 FOP_RES1:
 	CALL	DELAY			; FDC MAY TAKE UP TO 12us TO UPDATE MSR
-	IN	A,(FDC_MSR)		; READ MAIN STATUS REGISTER
+	IN_A_NN(FDC_MSR)		; READ MAIN STATUS REGISTER
 	AND	0F0H			; ISOLATE RQM/DIO/EXEC/BUSY
 	CP	0D0H			; LOOKING FOR RQM/DIO/BUSY
 	JR	Z,FOP_RES2		; GOOD, GO TO RECEIVE BYTE
@@ -1848,7 +1848,7 @@ FOP_RES2:	; PROCESS NEXT PENDING BYTE
 	LD	A,FRB_SIZ		; GET BUF SIZE
 	CP	D			; REACHED MAX?
 	JR	Z,FOP_BUFMAX		; HANDLE BUF MAX/EXIT
-	IN	A,(FDC_DATA)		; GET THE BYTE
+	IN_A_NN(FDC_DATA)		; GET THE BYTE
 	LD	(HL),A			; SAVE VALUE
 	INC	HL			; INCREMENT BUF POS
 	INC	D			; INCREMENT BYTES RECEIVED
@@ -2225,4 +2225,4 @@ FCD_FDCRDY	.DB	0		; FALSE MEANS FDC RESET NEEDED
 FD_DSKBUF	.DW	0
 FD_CURGEOM	.EQU	$		; TWO BYTES BELOW
 FD_CURSPT	.DB	0		; CURRENT SECTORS PER TRACK
-FD_CURHDS	.DB	0		; CURRENT HEADS
\ No newline at end of file
+FD_CURHDS	.DB	0		; CURRENT HEADS
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index f3a066c2..fc6fdd19 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2846,6 +2846,42 @@ PSCNX	.EQU	$ + 1
 	DJNZ	PSCN1
 ;
 #ENDIF
+
+#IF (CPUFAM == CPU_EZ80)
+;
+;--------------------------------------------------------------------------------------------------
+; DELAY LOOP TEST CALIBRATION
+;--------------------------------------------------------------------------------------------------
+;
+; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE
+; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
+; AND BUS CYCLES
+;
+#IF FALSE
+
+PC_DR:		.equ	$009E
+PC_DDR:		.equ	$009F
+
+	; ENABLE PC5 GPIO AS OUTPUT
+	LD	BC, PC_DDR
+	XOR	A
+	OUT	(C), A
+	PUSH	AF
+
+	LD	BC, PC_DR
+	LD	D, 0
+LOOP:
+	POP	AF
+	OUT	(C), A
+	CPL
+	PUSH	AF
+
+	LD	DE, 2
+	CALL	VDELAY
+	JR	LOOP
+#ENDIF
+#ENDIF
+
 ;
 ;--------------------------------------------------------------------------------------------------
 ; CPU SPEED DETECTION ALIGNMENT TEST
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index b52d0f1b..89352826 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -118,28 +118,28 @@ SN7_VOLUME_OFF:
 
 	LD	A, CHANNEL_0_SILENT
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 	OUT	(C), A
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
 
 	LD	A, CHANNEL_1_SILENT
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 	OUT	(C), A
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
 
 	LD	A, CHANNEL_2_SILENT
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 	OUT	(C), A
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
 
 	LD	A, CHANNEL_3_SILENT
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 	OUT	(C), A
 	LD	BC, SN76489_PORT16_RIGHT
 	OUT	(C), A
@@ -200,7 +200,7 @@ SN7_PLAY:
 	AUDTRACE_D
 	AUDTRACE_CR
 
-	EZ80_DELAY_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 
 	LD	A, (SN7_PENDING_PERIOD + 1)
 	CP	$FF
@@ -311,7 +311,7 @@ SN7_APPLY_VOL:				; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS
 #ENDIF
 
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 #IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
 #ENDIF
@@ -364,7 +364,7 @@ SN7_APPLY_PRD:
 #ENDIF
 
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 #IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
 #ENDIF
@@ -408,7 +408,7 @@ SN7_APPLY_PRD:
 #ENDIF
 
 	LD	BC, SN76489_PORT16_LEFT
-	EZ80_DELAY_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
+	EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER)
 #IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT))
 	OUT	(C), A
 #ENDIF

From b3bab80342eeccdef553e08efa6b5dbbf18cc677 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 4 Aug 2024 15:08:12 +1000
Subject: [PATCH 43/62] ez80: supply the required min value for BUS CYCLES when
 using frequency calculation

---
 Source/HBIOS/Config/RCEZ80_std.asm | 2 ++
 Source/HBIOS/cfg_rcez80.asm        | 2 ++
 Source/HBIOS/ez80cpudrv.asm        | 5 ++++-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 3f178e68..e71a921f 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -67,3 +67,5 @@ PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
 EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
 EZ80TIMER	.SET	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 0ab3f277..45a0a9d8 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -47,10 +47,12 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
 EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
 EZ80_MEM_FREQ	.EQU	16000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_MEM_MINCYC	.EQU	1		; EZ80 MINIMUM CYCLES FOR MEMORY WHEN CALCULATING FROM EZ80_MEM_FREQ
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
 EZ80_IO_CYCLES	.EQU	4		; EZ80 CYCLES FOR IO (1-15)
 EZ80_IO_FREQ	.EQU	5250		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_IO_MINCYC	.EQU	4		; EZ80 MINIMUM CYCLES FOR IO WHEN CALCULATING FROM EZ80_IO_FREQ
 ;
 ; SELECT CYCLES, OR CALCULATE CYCLES BASED ON DESIRED FREQUENCY
 EZ80_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 1570cdab..13af3f4c 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -44,7 +44,10 @@ EZ80_PREINIT:
 #ELSE
 	LD	HL, EZ80_MEM_FREQ
 	LD	DE, EZ80_IO_FREQ
-	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
+	EXX
+	LD	HL, EZ80_MEM_MINCYC << 8 | EZ80_IO_MINCYC
+	EXX
+	EZ80_UTIL_SET_BUSFQ()
 #ENDIF
 	LD	A, H
 	LD	(EZ80_PLT_C3CYL), A

From 7d5dc565f38e8db55a146316f44dc89466e8dd37 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 4 Aug 2024 15:09:21 +1000
Subject: [PATCH 44/62] ez80: tms driver - minor update/refactor

---
 Source/HBIOS/Config/RCEZ80_std.asm |  2 +-
 Source/HBIOS/tms.asm               | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index e71a921f..bd8a9527 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -40,7 +40,7 @@ DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
 MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index 7546d53e..25b48e53 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -252,6 +252,12 @@ TMS_INIT:
 	RET
 ;
 TMS_INIT1:
+#IF (TMSTIMENABLE)
+	EZ80_UTIL_DEBUG
+
+	PRTS(" INTERRUPT ENABLED$")
+
+#ENDIF
 	CALL 	TMS_CRTINIT		; SETUP THE TMS CHIP REGISTERS
 	CALL	TMS_LOADFONT		; LOAD FONT DATA FROM ROM TO TMS STRORAGE
 	CALL	TMS_CLEAR		; CLEAR SCREEN, HOME CURSOR
@@ -814,7 +820,7 @@ TMS_SETCUR1:				; READ GLYPH LOOP
 	IN	A,(TMS_DATREG)		; GET NEXT BYTE
 	TMS_IODELAY			; IO DELAY
 	LD	(HL),A			; SAVE VALUE IN BUF
-	INC	HL					; BUMP BUF POINTER
+	INC	HL			; BUMP BUF POINTER
 	DJNZ	TMS_SETCUR1		; LOOP FOR 8 BYTES
 ;
 	; NOW WRITE INVERTED GLYPH INTO FONT INDEX 255
@@ -1098,12 +1104,7 @@ TMS_Z180IOX:
 
 #IF (TMSTIMENABLE & (INTMODE > 0))
 TMS_TSTINT:
-#IF (CPUFAM == CPU_EZ80)
-	LD	BC, IO_SEGMENT<<8 | TMS_CMDREG
-	IN	A,(C)			; TEST FOR INT FLAG
-#ELSE
-	IN	A,(TMS_CMDREG)		; TEST FOR INT FLAG
-#ENDIF
+	IN_A_NN(TMS_CMDREG)
 	AND	$80
 	JR	NZ,TMS_INTHNDL
 	AND	$00			; RETURN Z - NOT HANDLED

From 141c79ef90b7ee5d1a359a3873785c2e08cc642b Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 10 Aug 2024 16:03:40 +1000
Subject: [PATCH 45/62] ez80: ported msx keyboard driver (mky.asm)

---
 Source/HBIOS/Config/RCEZ80_std.asm | 4 ++--
 Source/HBIOS/mky.asm               | 9 +++++++++
 Source/HBIOS/tms.asm               | 7 -------
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index bd8a9527..0800c3b1 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -43,10 +43,10 @@ LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
-MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYENABLE	.SET	TRUE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
diff --git a/Source/HBIOS/mky.asm b/Source/HBIOS/mky.asm
index 34650e82..5cddbcfb 100644
--- a/Source/HBIOS/mky.asm
+++ b/Source/HBIOS/mky.asm
@@ -211,8 +211,10 @@ MKY_INIT:
 	; C - OUTPUT (ROW LINE SELECTION)
 
 	LD	A, PPICMD_COMMAND | PPICMD_GA_MODE_0 | PPICMD_GB_MODE_0 | PPICMD_A_IN | PPICMD_B_IN | PPICMD_CLOW_OUT | PPICMD_CHIGH_OUT
+	EZ80_IO
 	OUT	(MKY_REGCMD), A
 	LD	A, 64			; CAPS OFF
+	EZ80_IO
 	OUT	(MKY_REGC), A
 	RET
 ;
@@ -368,8 +370,10 @@ MKY_SETLEDS:
 ; TURN THE CAPS LED LIGHT ON
 ;
 MKY_LEDCAPSON:
+	EZ80_IO
 	IN	A, (MKY_REGC)
 	RES	6, A
+	EZ80_IO
  	OUT	(MKY_REGC), A
 	RET
 ;
@@ -378,8 +382,10 @@ MKY_LEDCAPSON:
 ; TURN THE CAPS LED LIGHT OFF
 ;
 MKY_LEDCAPSOFF:
+	EZ80_IO
 	IN	A, (MKY_REGC)
 	SET	6, A
+	EZ80_IO
  	OUT	(MKY_REGC), A
 	RET
 
@@ -740,6 +746,7 @@ MKY_INTSCAN1:
 
 ; SCAN KEYBOARD AND STORE ALL COLUMN RESULTS PER ROW AT MKY_NEWKEY
 ;
+	EZ80_IO
 	IN      A, (MKY_REGC)			; READ AND MASK THE CURRENT STATE OF PPI PORT C
 	AND     $F0
 	LD      D, A
@@ -747,7 +754,9 @@ MKY_INTSCAN1:
 	LD      HL, MKY_NEWKEY
 	LD	C, MKY_REGC
 MKY_SCAN_LP:
+	EZ80_IO
 	OUT     (C), D				; SET ACTIVE ROW
+	EZ80_IO
 	IN      A, (MKY_REGB)			; READ ACTIVE COLUMN DATA
 	LD      (HL), A				; STORE COLUMN READ VALUE
 	INC     HL
diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index 25b48e53..114fd001 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -253,8 +253,6 @@ TMS_INIT:
 ;
 TMS_INIT1:
 #IF (TMSTIMENABLE)
-	EZ80_UTIL_DEBUG
-
 	PRTS(" INTERRUPT ENABLED$")
 
 #ENDIF
@@ -1111,11 +1109,6 @@ TMS_TSTINT:
 	RET
 
 TMS_INTHNDL:
-
-;#IF MKYENABLE
-;	CALL	MKY_INT
-;#ENDIF
-
 	CALL	HB_TIMINT		; RETURN NZ - HANDLED
 	OR	$FF
 	RET

From fa6b0f1d8238dff5d3ea904702378d5b8693cc6e Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 5 Sep 2024 21:00:31 +1000
Subject: [PATCH 46/62] ez80: deprecated EZ80_UTIL_EHL_TO_HL - now using local
 implementation EZ80_CPY_EHL_TO_UHL

---
 Source/HBIOS/ez80cpudrv.asm | 16 ++++++++++++++++
 Source/HBIOS/ez80instr.inc  |  3 ++-
 Source/HBIOS/ez80systmr.asm |  4 ++--
 Source/HBIOS/ez80uart.asm   |  2 +-
 4 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 13af3f4c..45ebed71 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -77,3 +77,19 @@ EZ80_PLT_C3CYL:
 	.DB	EZ80_MEM_CYCLES
 EZ80_PLT_C2CYL:
 	.DB	EZ80_IO_CYCLES
+
+
+; ez80 helper functions/instructions
+
+_EZ80_CPY_EHL_TO_UHL:
+	PUSH	IX
+	PUSH	AF
+	.DB $5B, $DD, $21, $00, $00, $00		; LD.LIL	IX, 0
+	.DB $49, $DD, $39				; ADD.L		IX, SP
+	.DB $49, $E5					; PUSH.L	HL
+	.DB $5B, $DD, $73, $FF				; LD.LIL	(IX-1), E
+	.DB $49, $E1					; POP.L		HL
+	POP	AF
+	POP	IX
+	RET
+
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 4d495a3b..5026de24 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -15,7 +15,6 @@
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_UTIL_EHL_TO_HL		XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_HL_TO_EHL		XOR A \ LD B, 2 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
@@ -117,6 +116,8 @@ IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
   #DEFCONT \ LD A, IO_SEGMENT
   #DEFCONT \ IN A, (addr)
 
+#define EZ80_CPY_EHL_TO_UHL 	CALL _EZ80_CPY_EHL_TO_UHL
+
 #ELSE
   #DEFINE EZ80_IO
 
diff --git a/Source/HBIOS/ez80systmr.asm b/Source/HBIOS/ez80systmr.asm
index dde6f072..4e73e971 100644
--- a/Source/HBIOS/ez80systmr.asm
+++ b/Source/HBIOS/ez80systmr.asm
@@ -64,7 +64,7 @@ SYS_GETSECS:
 ;     DE:HL: TIMER VALUE (32 BIT)
 ;
 SYS_SETTIMER:
-	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+	EZ80_CPY_EHL_TO_UHL		; HL{23:0} <- E:HL{15:0}
 	EZ80_TMR_SET_TICKS()
 	RET
 ;
@@ -73,7 +73,7 @@ SYS_SETTIMER:
 ;     DE:HL: SECONDS VALUE (32 BIT)
 ;
 SYS_SETSECS:
-	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+	EZ80_CPY_EHL_TO_UHL		; HL{23:0} <- E:HL{15:0}
 
 	EZ80_TMR_SET_SECONDS()
 	RET
diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index cfc624e0..c113c577 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -144,7 +144,7 @@ NOT_RESET:
 	LD	DE, 75			; BAUD RATE DECODE CONSTANT
 	CALL	DECODE			; DE:HL := BAUD RATE
 
-	EZ80_UTIL_EHL_TO_HL()		; HL{23:0} <- E:HL{15:0}
+	EZ80_CPY_EHL_TO_UHL		; HL{23:0} <- E:HL{15:0}
 
 	POP	DE			; RESTORE REQUESTED LINE CHARACTERISTICS
 	LD	A, E

From 5c10f1881d3f928b5bd88b728406217a4c63b09a Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Thu, 5 Sep 2024 21:16:00 +1000
Subject: [PATCH 47/62] ez80: deprecated EZ80_UTIL_HL_TO_EHL - now using local
 implementation EZ80_CPY_UHL_TO_EHL

---
 Source/HBIOS/ez80cpudrv.asm | 19 ++++++++++++++-----
 Source/HBIOS/ez80instr.inc  |  2 +-
 Source/HBIOS/ez80systmr.asm |  2 +-
 3 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 45ebed71..98906270 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -84,12 +84,21 @@ EZ80_PLT_C2CYL:
 _EZ80_CPY_EHL_TO_UHL:
 	PUSH	IX
 	PUSH	AF
-	.DB $5B, $DD, $21, $00, $00, $00		; LD.LIL	IX, 0
-	.DB $49, $DD, $39				; ADD.L		IX, SP
-	.DB $49, $E5					; PUSH.L	HL
-	.DB $5B, $DD, $73, $FF				; LD.LIL	(IX-1), E
-	.DB $49, $E1					; POP.L		HL
+	.DB 	$5B, $DD, $21, $00, $00, $00		; LD.LIL	IX, 0
+	.DB 	$49, $DD, $39				; ADD.L		IX, SP
+	.DB 	$49, $E5				; PUSH.L	HL
+	.DB 	$5B, $DD, $73, $FF			; LD.LIL	(IX-1), E
+	.DB 	$49, $E1				; POP.L		HL
 	POP	AF
 	POP	IX
 	RET
 
+_EZ80_CPY_UHL_TO_EHL:
+	PUSH	IX
+	.DB	$5B, $DD, $21, $00, $00, $00		; LD.LIL	IX, 0
+	.DB	$49, $DD, $39				; ADD.L		IX, SP
+	.DB	$49, $E5				; PUSH.L	HL
+	.DB	$5B, $DD, $5E, $FF			; LD.LIL	E, (IX-1)
+	.DB	$49, $E1				; POP.L		HL
+	POP	IX
+	RET
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 5026de24..6919a481 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -15,7 +15,6 @@
   #DEFINE EZ80_BNKSEL 	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
-  #DEFINE EZ80_UTIL_HL_TO_EHL		XOR A \ LD B, 2 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
@@ -117,6 +116,7 @@ IO_SEGMENT	.EQU		$FF		; THE UPPER 8-BIT ADDRESS FOR I/O
   #DEFCONT \ IN A, (addr)
 
 #define EZ80_CPY_EHL_TO_UHL 	CALL _EZ80_CPY_EHL_TO_UHL
+#define EZ80_CPY_UHL_TO_EHL	CALL _EZ80_CPY_UHL_TO_EHL
 
 #ELSE
   #DEFINE EZ80_IO
diff --git a/Source/HBIOS/ez80systmr.asm b/Source/HBIOS/ez80systmr.asm
index 4e73e971..580ba4a1 100644
--- a/Source/HBIOS/ez80systmr.asm
+++ b/Source/HBIOS/ez80systmr.asm
@@ -55,7 +55,7 @@ SYS_GETTIMER:
 SYS_GETSECS:
 	EZ80_TMR_GET_SECONDS()
 
-	EZ80_UTIL_HL_TO_EHL()		; E:HL{15:0} <- HL{23:0}
+	EZ80_CPY_UHL_TO_EHL		; E:HL{15:0} <- HL{23:0}
 	LD	D, 0
 	RET
 ;

From 479c50f05282367e9cf74790a3573e137546c768 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Fri, 6 Sep 2024 18:28:02 +1000
Subject: [PATCH 48/62] ez80: updated to deprecate use of RST.L %18 for bank
 switching and direct access using 16bit i/o

---
 Source/HBIOS/ez80instr.inc |  2 --
 Source/HBIOS/hbios.asm     | 14 ++++++++++++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 6919a481..11094e60 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,8 +11,6 @@
   #DEFINE EZ80_IO	.DB 	$49, $CF
   ; RST.L $10
   #DEFINE EZ80_FN 	.DB	$49, $D7
-  ; RST.L $18
-  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index fc6fdd19..7af4f151 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -617,8 +617,18 @@ HBX_ROM:
 #IF (MEMMGR == MM_Z2)
 
 #IF (CPUFAM == CPU_EZ80)
-	EZ80_BNKSEL
-	RET
+	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
+	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
+	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+	ADD	A,16			; ADD 16 x 32K - RAM STARTS FROM 512K
+;
+HBX_ROM:
+	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
+	OUT_NN_A(MPGSEL_0)		; BANK_0: 0K - 16K
+	INC	A			;
+	OUT_NN_A(MPGSEL_1)		; BANK_1: 16K - 32K
+	RET				; DONE
+
 #ELSE
 
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE

From 64d60f744b02a813d6f9d6fd79b4de2fcc898044 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 8 Sep 2024 13:53:57 +1000
Subject: [PATCH 49/62] ez80: updated to report firmware version, build date,
 and if operating under the alt image

---
 Source/HBIOS/Config/RCEZ80_std.asm | 14 ++---
 Source/HBIOS/ez80cpudrv.asm        | 84 ++++++++++++++++++++++++++----
 Source/HBIOS/ez80instr.inc         |  1 -
 Source/HBIOS/hbios.asm             |  5 ++
 4 files changed, 87 insertions(+), 17 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index 0800c3b1..a8ff8340 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -30,7 +30,7 @@ CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 ;
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -43,20 +43,22 @@ LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 TMSMODE		.SET	TMSMODE_MSX9958	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
-MKYENABLE	.SET	TRUE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
 VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
 ;
 AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
+FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FD0TYPE		.EQU	FDT_5HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
@@ -66,6 +68,6 @@ PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 
 EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
 EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
-EZ80TIMER	.SET	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+EZ80TIMER	.SET	EZ80TMR_FIRM	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
 ;
 CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 98906270..77729ae3 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -21,15 +21,24 @@ EZ80_PREINIT:
 	LD	L, RTP
 
 	EZ80_UTIL_VER_EXCH()
-	; TODO CHECK RETURNED VERSION AND WARN IF NOT GOOD
-	; EXPECT A VERSION NUMBER > 0.1.0.0
+	; TODO: MAP THE FIRMWARE CPU TO HBIOS (eZ80 ONLY HAS ONE CPU TYPE AS OF NOW)
+	LD	A, 5
+	LD	(HB_CPUTYPE),A
+
+	; DETECT IF USING ALT-FIRMWARE
+	LD	A, C
+	AND	$80
+	LD	(EZ80_ALT_FIRM), A
+	LD	(EZ80_PLT_VERSION), HL
+	LD	(EZ80_PLT_VERSION+2), DE
 
-	LD	C, MEMMGR
-	LD	HL, ROMSIZE
-	LD	DE, RAMSIZE
-	EZ80_UTIL_BNK_HLP()		; INSTAL HIGH PERFORMANCE BANK SWITCHER
-	; TODO CHECK RESULT AND USE STANDARD BANK SWITCHER IF NZ RETURNED
-	; OTHERWISE USE RST.L  %18 FOR BANK SWITCH HELPER
+	EXX
+	LD	A, C
+	LD	(EZ80_BUILD_DATE), A		; DAY
+	LD	A, D
+	LD	(EZ80_BUILD_DATE+1), A		; MONTH
+	LD	A, E
+	LD	(EZ80_BUILD_DATE+2), A		; YEAR
 
 	EZ80_UTIL_GET_CPU_FQ()
 	LD	A, E
@@ -57,8 +66,6 @@ EZ80_PREINIT:
 	LD	C, TICKFREQ
 	EZ80_TMR_SET_FREQTICK
 
-	LD	A, 5			; HB_CPUTYPE = 5 FOR eZ80
-	LD	(HB_CPUTYPE),A
 	RET
 
 EZ80_RPT_TIMINGS:
@@ -73,11 +80,68 @@ EZ80_RPT_TIMINGS:
 	.TEXT	" I/O B/C$"
 	RET
 
+EZ80_RPT_FIRMWARE:
+	CALL	PRTSTRD
+	.TEXT	"\r\neZ80 Firmware: $"
+
+	LD	A, (EZ80_PLT_VERSION+3) 	; MAJOR VERSION NUMBER
+	CALL	PRTDECB
+	CALL	PC_PERIOD
+	LD	A, (EZ80_PLT_VERSION+2) 	; MINOR VERSION NUMBER
+	CALL	PRTDECB
+	CALL	PC_PERIOD
+	LD	A, (EZ80_PLT_VERSION+1) 	; REVISION NUMBER
+	CALL	PRTDECB
+	CALL	PC_PERIOD
+	LD	A, (EZ80_PLT_VERSION) 		; PATCH NUMBER
+	CALL	PRTDECB
+
+	CALL	PRTSTRD
+	.TEXT	" 20$"
+	LD	A, (EZ80_BUILD_DATE+2)		; YEAR
+	CALL	PRTDECB
+	CALL	PC_DASH
+	LD	A, (EZ80_BUILD_DATE+1)		; MONTH
+	CALL	PC_LEADING_ZERO
+	CALL	PRTDECB
+	CALL	PC_DASH
+	LD	A, (EZ80_BUILD_DATE)		; DAY
+	CALL	PC_LEADING_ZERO
+	CALL	PRTDECB
+
+	LD	A, (EZ80_ALT_FIRM)
+	OR	A
+	RET	Z
+	CALL	PRTSTRD
+	.TEXT	" (ALT)$"
+	RET
+
+PC_LEADING_ZERO:
+	CP	10
+	RET	NC
+
+	PUSH	AF
+	LD 	A, '0'
+	JP	PC_PRTCHR
+
+PC_DASH:
+	PUSH	AF
+	LD	A, '-'
+	JP	PC_PRTCHR
+
 EZ80_PLT_C3CYL:
 	.DB	EZ80_MEM_CYCLES
 EZ80_PLT_C2CYL:
 	.DB	EZ80_IO_CYCLES
 
+EZ80_PLT_VERSION:
+	.DB	0, 0, 0, 0
+
+EZ80_ALT_FIRM:
+	.DB	0
+
+EZ80_BUILD_DATE:
+	.DB	0, 0, 0					; DAY, MONTH, YEAR
 
 ; ez80 helper functions/instructions
 
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 11094e60..880fc6d3 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -16,7 +16,6 @@
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
-  #DEFINE EZ80_UTIL_BNK_HLP 		XOR A \ LD B, 6 \ EZ80_FN
   #DEFINE EZ80_UTIL_DEBUG 		XOR A \ LD B, 7 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 		LD A, 1 \ LD B, 0 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 7af4f151..333c19cd 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2964,6 +2964,11 @@ HB_Z280BUS:
 HB_Z280BUS1:
 	PRTS("MHz$")			; SUFFIX
 #ENDIF
+
+#IF (CPUFAM == CPU_EZ80)
+	CALL	EZ80_RPT_FIRMWARE
+#ENDIF
+
 ;
 ;--------------------------------------------------------------------------------------------------
 ; DISPLAY CPU CONFIGURATION

From 162348ea6682d4d695eb93b0a411bf23c973855a Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sun, 4 Aug 2024 13:39:44 -0700
Subject: [PATCH 50/62] Implement SIOINTS Setting in SIO Driver

- SIOINTS allows disabling use of interrupts in the SIO driver when interrupts are enabled globally.  It will not allow you to enable SIO interrupts if interrupts are globally disabled (INTMODE 0).
---
 Source/HBIOS/cfg_duo.asm      |   1 +
 Source/HBIOS/cfg_dyno.asm     |   1 +
 Source/HBIOS/cfg_epitx.asm    |   1 +
 Source/HBIOS/cfg_heath.asm    |   1 +
 Source/HBIOS/cfg_master.asm   |   1 +
 Source/HBIOS/cfg_mbc.asm      |   1 +
 Source/HBIOS/cfg_mk4.asm      |   1 +
 Source/HBIOS/cfg_mon.asm      |   1 +
 Source/HBIOS/cfg_n8.asm       |   1 +
 Source/HBIOS/cfg_nabu.asm     |   1 +
 Source/HBIOS/cfg_rcez80.asm   |   1 +
 Source/HBIOS/cfg_rcz180.asm   |   1 +
 Source/HBIOS/cfg_rcz280.asm   |   1 +
 Source/HBIOS/cfg_rcz80.asm    |   1 +
 Source/HBIOS/cfg_s100.asm     |   1 +
 Source/HBIOS/cfg_sbc.asm      |   1 +
 Source/HBIOS/cfg_scz180.asm   |   1 +
 Source/HBIOS/cfg_z80retro.asm |   1 +
 Source/HBIOS/sio.asm          | 137 +++++++++++++++++-----------------
 19 files changed, 87 insertions(+), 68 deletions(-)

diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm
index 3bc052ea..9d4cfe8d 100644
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -150,6 +150,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 3cc02f97..912d9200 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -163,6 +163,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm
index 240eb5b2..00cf849f 100644
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -165,6 +165,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm
index b85556ba..218bd52b 100644
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -168,6 +168,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 1ef9fe79..7632256f 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -208,6 +208,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm
index 80363530..81d37064 100644
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -147,6 +147,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 9eb056eb..275ef074 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -157,6 +157,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm
index d8c45232..5cc7f56f 100644
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@@ -163,6 +163,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 655894bc..7590884b 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -159,6 +159,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm
index 526d6632..9bb6c4f1 100644
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@@ -168,6 +168,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 45a0a9d8..0b89a9e9 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -190,6 +190,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 34341f3c..f5ae9229 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -169,6 +169,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index a496f52c..9e3af1dc 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -173,6 +173,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 8942e3a0..c3eb0c93 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -168,6 +168,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm
index 92d7829c..101d36d4 100644
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -163,6 +163,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index c6c8ed23..b7d860c3 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -147,6 +147,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index b334a783..0a3919a9 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -163,6 +163,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm
index f6f4fd1c..73b38f04 100644
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -145,6 +145,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 0274a66e..c7e23e01 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -24,13 +24,13 @@ SIO_SIO		.EQU	1
 SIO_RTSON	.EQU	$EA
 SIO_RTSOFF	.EQU	$E8
 ;
-#IF (INTMODE == 0)
-SIO_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 SIO_WR1VAL	.EQU	$18		; WR1 VALUE FOR INT ON RECEIVED CHARS
+#ELSE
+SIO_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
 #ENDIF
 ;
-#IF ((INTMODE == 2) | (INTMODE == 3))
+#IF ((SIOINTS) & (INTMODE >= 2))
 ;
 SIO0_IVT	.EQU	IVT(INT_SIO0)
 SIO1_IVT	.EQU	IVT(INT_SIO1)
@@ -146,7 +146,7 @@ SIO_PREINIT2:
 	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	SIO_PREINIT0		; LOOP UNTIL DONE
 ;
-#IF (INTMODE >= 1)
+#IF ((SIOINTS) & (INTMODE > 0))
 	; SETUP INT VECTORS AS APPROPRIATE
 	LD	A,(SIO_DEV)		; GET DEVICE COUNT
 	OR	A			; SET FLAGS
@@ -223,7 +223,7 @@ SIO_INIT1:
 ;
 ; RECEIVE INTERRUPT HANDLER
 ;
-#IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 ; IM1 ENTRY POINT
 ;
@@ -354,17 +354,7 @@ SIO_FNTBL:
 ;
 ;
 ;
-#IF (INTMODE == 0)
-;
-SIO_IN:
-	CALL	SIO_IST			; CHAR WAITING?
-	JR	Z,SIO_IN		; LOOP IF NOT
-	LD	C,(IY+4)		; DATA PORT
-	IN	E,(C)			; GET CHAR
-	XOR	A			; SIGNAL SUCCESS
-	RET
-;
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 SIO_IN:
 	CALL	SIO_IST			; SEE IF CHAR AVAILABLE
@@ -411,6 +401,17 @@ SIO_IN2:
 	HB_EI				; INTERRUPTS OK AGAIN
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND DONE
+;
+#ELSE
+;
+SIO_IN:
+	CALL	SIO_IST			; CHAR WAITING?
+	JR	Z,SIO_IN		; LOOP IF NOT
+	LD	C,(IY+4)		; DATA PORT
+	IN	E,(C)			; GET CHAR
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
 #ENDIF
 ;
 ;
@@ -425,7 +426,17 @@ SIO_OUT:
 ;
 ;
 ;
-#IF (INTMODE == 0)
+#IF ((SIOINTS) & (INTMODE > 0))
+;
+SIO_IST:
+	LD	L,(IY+7)		; GET ADDRESS
+	LD	H,(IY+8)		; ... OF RECEIVE BUFFER
+	LD	A,(HL)			; BUFFER UTILIZATION COUNT
+	OR	A			; SET FLAGS
+	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
+	RET
+;
+#ELSE
 ;
 SIO_IST:
 	LD	C,(IY+3)		; CMD PORT
@@ -438,16 +449,6 @@ SIO_IST:
 	INC	A			; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING
 	RET				; DONE
 ;
-#ELSE
-;
-SIO_IST:
-	LD	L,(IY+7)		; GET ADDRESS
-	LD	H,(IY+8)		; ... OF RECEIVE BUFFER
-	LD	A,(HL)			; BUFFER UTILIZATION COUNT
-	OR	A			; SET FLAGS
-	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	RET
-;
 #ENDIF
 ;
 ;
@@ -853,7 +854,7 @@ SIO_INITGO:
 ;
 ; SET INTERRUPT VECTOR OFFSET WR2
 ;
-#IF ((INTMODE == 2) | (INTMODE == 3))
+#IF ((SIOINTS) & (INTMODE >= 2))
 	LD	A,(IY+2)		; CHIP / CHANNEL
 	SRL	A			; SHIFT AWAY CHANNEL BIT
 	LD	L,SIO0_VEC		; ASSUME CHIP 0
@@ -893,7 +894,7 @@ SIO_INITPRT:
 	LD	B,SIO_INITLEN		; COUNT OF BYTES TO WRITE
 	OTIR				; WRITE ALL VALUES
 ;
-#IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 	; RESET THE RECEIVE BUFFER
 	LD	E,(IY+7)
@@ -1108,17 +1109,7 @@ SIO_STR_SIO	.DB	"SIO$"
 SIO_DEV		.DB	0		; DEVICE NUM USED DURING INIT
 SIO_MAP		.DB	0		; CHIP PRESENCE BITMAP
 ;
-#IF (INTMODE == 0)
-;
-SIO0A_RCVBUF	.EQU	0
-SIO0B_RCVBUF	.EQU	0
-;
-  #IF (SIOCNT >= 2)
-SIO1A_RCVBUF	.EQU	0
-SIO1B_RCVBUF	.EQU	0
-  #ENDIF
-;
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 ; SIO0 CHANNEL A RECEIVE BUFFER
 SIO0A_RCVBUF:
@@ -1152,6 +1143,16 @@ SIO1B_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
 ;
   #ENDIF
 ;
+#ELSE
+;
+SIO0A_RCVBUF	.EQU	0
+SIO0B_RCVBUF	.EQU	0
+;
+  #IF (SIOCNT >= 2)
+SIO1A_RCVBUF	.EQU	0
+SIO1B_RCVBUF	.EQU	0
+  #ENDIF
+;
 #ENDIF
 ;
 ; SIO PORT TABLE
@@ -1191,9 +1192,9 @@ SIO0A_CFG:
 	DEVECHO	", IO="
 	DEVECHO	SIO0BASE
 	DEVECHO	", CHANNEL A"
-  #IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
-  #ENDIF
+#ENDIF
 		DEVECHO	"\n"
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
@@ -1231,9 +1232,9 @@ SIO0B_CFG:
 	DEVECHO	", IO="
 	DEVECHO	SIO0BASE
 	DEVECHO	", CHANNEL B"
-  #IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
-  #ENDIF
+#ENDIF
 		DEVECHO	"\n"
 ;
 #IF (SIOCNT >= 2)
@@ -1253,26 +1254,26 @@ SIO1A_CFG:
 	.DB	SIO1MODE		; MODE
 ;
 	DEVECHO	"SIO MODE="
-#IF (SIO1MODE == SIOMODE_STD)
+  #IF (SIO1MODE == SIOMODE_STD)
 	DEVECHO	"STD"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_RC)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_RC)
 	DEVECHO	"RC"
-#ENDIF	
-
-#IF (SIO1MODE == SIOMODE_SMB)
+  #ENDIF	
+;
+  #IF (SIO1MODE == SIOMODE_SMB)
 	DEVECHO	"SMB"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_ZP)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_ZP)
 	DEVECHO	"ZP"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_Z80R)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
 	DEVECHO	"Z80R"
-#ENDIF
+  #ENDIF
 	DEVECHO	", IO="
 	DEVECHO	SIO1BASE
 	DEVECHO	", CHANNEL A"
-  #IF (INTMODE > 0)
+  #IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
   #ENDIF
 		DEVECHO	"\n"
@@ -1292,25 +1293,25 @@ SIO1B_CFG:
 	.DB	SIO1MODE		; MODE
 ;
 	DEVECHO	"SIO MODE="
-#IF (SIO1MODE == SIOMODE_STD)
+  #IF (SIO1MODE == SIOMODE_STD)
 	DEVECHO	"STD"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_RC)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_RC)
 	DEVECHO	"RC"
-#ENDIF	
-#IF (SIO1MODE == SIOMODE_SMB)
+  #ENDIF	
+  #IF (SIO1MODE == SIOMODE_SMB)
 	DEVECHO	"SMB"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_ZP)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_ZP)
 	DEVECHO	"ZP"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_Z80R)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
 	DEVECHO	"Z80R"
-#ENDIF
+  #ENDIF
 	DEVECHO	", IO="
 	DEVECHO	SIO1BASE
 	DEVECHO	", CHANNEL B"
-  #IF (INTMODE > 0)
+  #IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
   #ENDIF
 		DEVECHO	"\n"

From 3880d8fca03f8eea2292c03d56eb4dc5d1568799 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 14 Sep 2024 15:54:11 +1000
Subject: [PATCH 51/62] tsm: for v9958 - configure interrupt rate (HSYNC) as
 per TICKFREQ config setting

---
 Source/HBIOS/tms.asm | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index 114fd001..d8116d14 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -1214,7 +1214,11 @@ TMS_INITVDU_REG_1:
 	.DB	$00		; REG 6 - NO SPRITE GENERATOR TABLE
 	.DB	$F0		; REG 7 - WHITE ON BLACK
 	.DB	$88		; REG 8 - COLOUR BUS INPUT, DRAM 64K
+#IF (TICKFREQ == 50)
+	.DB	$02		; REG 9
+#ELSE
 	.DB	$00		; REG 9
+#ENDIF
 	.DB	$00		; REG 10 - COLOUR TABLE A14-A16 (TMS_FNTVADDR - $1000)
 ;
 #ELSE 		; _______TMS9918 REGISTER SET_______

From b5d4e7ddf9713c62eefac8e13831ac2e8735bd1c Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 14 Sep 2024 15:56:10 +1000
Subject: [PATCH 52/62] ez80: added new EZ80TIMER type - EZ80TMR_NONE

---
 Source/HBIOS/cfg_rcez80.asm | 1 +
 Source/HBIOS/ez80systmr.asm | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 0b89a9e9..f18df695 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -132,6 +132,7 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 EZ80RTCENABLE	.EQU	TRUE		; EZ80 ON CHIP RTC
 ;
+EZ80TMR_NONE	.EQU	0		; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS
 EZ80TMR_INT	.EQU	1		; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
 EZ80TMR_FIRM	.EQU	2		; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
 EZ80TIMER	.EQU	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
diff --git a/Source/HBIOS/ez80systmr.asm b/Source/HBIOS/ez80systmr.asm
index 580ba4a1..00f1b6f6 100644
--- a/Source/HBIOS/ez80systmr.asm
+++ b/Source/HBIOS/ez80systmr.asm
@@ -29,7 +29,8 @@ EZ80_TMR_INT:
 	CALL	HB_TIMINT		; RETURN NZ - HANDLED
 	OR	$FF
 	RET
-#ELSE
+#ENDIF
+#IF (EZ80TIMER == EZ80TMR_FIRM)
 
 EZ80_TMR_INIT:
 	CALL	NEWLINE			; FORMATTING
@@ -79,3 +80,7 @@ SYS_SETSECS:
 	RET
 
 #ENDIF
+#IF (EZ80TIMER == EZ80TMR_NONE)
+EZ80_TMR_INIT:
+	RET
+#ENDIF

From af030bf76dac198da1ad9c8a00af651dedc798dd Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 08:39:24 +1000
Subject: [PATCH 53/62] ez80: use new firmware interface for w/s config
 settings

---
 Source/HBIOS/cfg_rcez80.asm | 20 +++++----
 Source/HBIOS/ez80cpudrv.asm | 89 +++++++++++++++++++++++++++++--------
 Source/HBIOS/ez80instr.inc  |  6 +++
 Source/HBIOS/sn76489.asm    |  2 +-
 Source/HBIOS/std.asm        |  6 +++
 5 files changed, 95 insertions(+), 28 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index f18df695..f427886a 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -45,17 +45,21 @@ MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
-EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
-EZ80_MEM_FREQ	.EQU	16000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
-EZ80_MEM_MINCYC	.EQU	1		; EZ80 MINIMUM CYCLES FOR MEMORY WHEN CALCULATING FROM EZ80_MEM_FREQ
+EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
+EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
+EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
-EZ80_IO_CYCLES	.EQU	4		; EZ80 CYCLES FOR IO (1-15)
-EZ80_IO_FREQ	.EQU	5250		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
-EZ80_IO_MINCYC	.EQU	4		; EZ80 MINIMUM CYCLES FOR IO WHEN CALCULATING FROM EZ80_IO_FREQ
+EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
+EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+
+; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
+EZ80_ASSIGN	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
 ;
-; SELECT CYCLES, OR CALCULATE CYCLES BASED ON DESIRED FREQUENCY
-EZ80_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 77729ae3..73b70bf5 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -46,22 +46,51 @@ EZ80_PREINIT:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
-#IF (EZ80_ASSIGN == 1)
-	LD	H, EZ80_MEM_CYCLES
+#IF (EZ80_ASSIGN == EZ80WSMD_CYCLES)
+	LD	L, EZ80_MEM_CYCLES
+	OR	$80
+	EZ80_UTIL_MEMTM_SET()
+	LD	A, L
+	LD	(EZ80_PLT_MEMWS), A
+
 	LD	L, EZ80_IO_CYCLES
-	EZ80_UTIL_SET_BUSTM()
-#ELSE
-	LD	HL, EZ80_MEM_FREQ
-	LD	DE, EZ80_IO_FREQ
-	EXX
-	LD	HL, EZ80_MEM_MINCYC << 8 | EZ80_IO_MINCYC
-	EXX
-	EZ80_UTIL_SET_BUSFQ()
+	OR	$80
+	EZ80_UTIL_IOTM_SET()
+	LD	A, L
+	LD	(EZ80_PLT_IOWS), A
+
+	RET
+#ENDIF
+
+#IF (EZ80_ASSIGN == EZ80WSMD_CALC)
+	LD	HL, EZ80_MEM_MIN_NS
+	LD	E, 0
+	EZ80_CPY_EHL_TO_UHL
+	LD	E, EZ80_MEM_MIN_WS
+	EZ80_UTIL_MEMTMFQ_SET
+	LD	A, L
+	LD	(EZ80_PLT_MEMWS), A
+
+	LD	HL, EZ80_IO_MIN_NS
+	LD	E, 0
+	EZ80_CPY_EHL_TO_UHL
+	LD	E, EZ80_IO_MIN_WS
+	EZ80_UTIL_IOTMFQ_SET
+
+	LD	A, L
+	LD	(EZ80_PLT_IOWS), A
 #ENDIF
-	LD	A, H
-	LD	(EZ80_PLT_C3CYL), A
+#IF (EZ80_ASSIGN == EZ80WSMD_WAIT)
+	LD	L, EZ80_MEM_WS
+	EZ80_UTIL_MEMTM_SET()
 	LD	A, L
-	LD	(EZ80_PLT_C2CYL), A
+	LD	(EZ80_PLT_MEMWS), A
+
+	LD	L, EZ80_IO_WS
+	EZ80_UTIL_IOTM_SET()
+	LD	A, L
+	LD	(EZ80_PLT_IOWS), A
+#ENDIF
 
 	LD	C, TICKFREQ
 	EZ80_TMR_SET_FREQTICK
@@ -69,12 +98,34 @@ EZ80_PREINIT:
 	RET
 
 EZ80_RPT_TIMINGS:
-	LD	A,(EZ80_PLT_C3CYL)
+	LD	A, (EZ80_PLT_MEMWS)
+	BIT	7, A
+	JR	NZ, EZ80_RPT_MCYC
+
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM W/S, $"
+	JR	EZ80_RPT_IOTIMING
+
+EZ80_RPT_MCYC:
+	AND	$7F
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" MEM B/C, $"
 
-	LD	A,(EZ80_PLT_C2CYL)
+
+EZ80_RPT_IOTIMING:
+	LD	A, (EZ80_PLT_IOWS)
+	BIT	7, A
+	JR	NZ, EZ80_RPT_ICYC
+
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" I/O W/S$"
+	RET
+
+EZ80_RPT_ICYC:
+	AND	$7F
 	CALL	PRTDECB
 	CALL	PRTSTRD
 	.TEXT	" I/O B/C$"
@@ -129,10 +180,10 @@ PC_DASH:
 	LD	A, '-'
 	JP	PC_PRTCHR
 
-EZ80_PLT_C3CYL:
-	.DB	EZ80_MEM_CYCLES
-EZ80_PLT_C2CYL:
-	.DB	EZ80_IO_CYCLES
+EZ80_PLT_MEMWS:
+	.DB	EZ80_MEM_WS
+EZ80_PLT_IOWS:
+	.DB	EZ80_IO_WS
 
 EZ80_PLT_VERSION:
 	.DB	0, 0, 0, 0
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index 880fc6d3..ce0b0ba9 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -17,6 +17,12 @@
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
   #DEFINE EZ80_UTIL_DEBUG 		XOR A \ LD B, 7 \ EZ80_FN
+  #DEFINE EZ80_UTIL_MEMTM_SET 		XOR A \ LD B, 8 \ EZ80_FN
+  #DEFINE EZ80_UTIL_IOTM_SET 		XOR A \ LD B, 9 \ EZ80_FN
+  #DEFINE EZ80_UTIL_MEMTM_GET 		XOR A \ LD B, 10 \ EZ80_FN
+  #DEFINE EZ80_UTIL_IOTM_GET 		XOR A \ LD B, 11 \ EZ80_FN
+  #DEFINE EZ80_UTIL_MEMTMFQ_SET		XOR A \ LD B, 12 \ EZ80_FN
+  #DEFINE EZ80_UTIL_IOTMFQ_SET		XOR A \ LD B, 13 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 		LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 		LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index 89352826..fe363778 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -43,7 +43,7 @@ SN76489_PORT16_RIGHT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_RIGHT
 
 #IF (CPUFAM == CPU_EZ80)
 ; The eZ80 configuration must have sufficient bus cycles configured for this driver
-; to work.  See the entries: (EZ80_ASSIGN and EZ80_IO_CYCLES or EZ80_IO_FREQ)
+; to work.  See the entries: (EZ80_ASSIGN and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS)
 ;
 ; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations
 ; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 9cc67735..87eccfb9 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -548,6 +548,12 @@ SCSI_CMD_RDCAP		.EQU	$25
 SCSI_CMD_READ10		.EQU	$28
 SCSI_CMD_WRITE10	.EQU	$2A
 ;
+; EZ80 BUS MODES
+;
+EZ80WSMD_CALC	.EQU	0
+EZ80WSMD_CYCLES	.EQU	1
+EZ80WSMD_WAIT	.EQU	2
+;
 #INCLUDE "build.inc"		; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
 ; INCLUDE Z180 REGISTER DEFINITIONS

From 2176c9d1af2fbb0f10f9d331bc26fa7ea1d89835 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 10:17:10 +1000
Subject: [PATCH 54/62] ez80: new firmware feature to configure on-chip flash
 w/s

---
 Source/HBIOS/cfg_rcez80.asm | 24 ++++++++++++++---------
 Source/HBIOS/ez80cpudrv.asm | 38 ++++++++++++++++++++++++++++++-------
 Source/HBIOS/ez80instr.inc  |  3 +++
 Source/HBIOS/sn76489.asm    |  2 +-
 4 files changed, 50 insertions(+), 17 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index f427886a..69755013 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -45,20 +45,26 @@ MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
-EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
-EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
-EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
-EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
 ;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
-EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CYCLES
-EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_WAIT
-EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_ASSIGN = EZ80WSMD_CALC
-EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_ASSIGN = EZ80WSMD_CALC
+EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
 ; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
-EZ80_ASSIGN	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
+EZ80_WSMD_TYP	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
+;
+; BUS TIMING FOR ON CHIP ROM
+;
+EZ80_FLSH_WS	.EQU	1		; WAIT STATES FOR ON CHIP FLASH (0-7)
+EZ80_FLSH_MIN_NS .EQU	60	; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_FWSMD_TYP	.EQU	EZ80WSMD_CALC	; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)
 ;
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 73b70bf5..7f5eb6e8 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -46,7 +46,24 @@ EZ80_PREINIT:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
-#IF (EZ80_ASSIGN == EZ80WSMD_CYCLES)
+#IF (EZ80_FWSMD_TYP == EZ80WSMD_WAIT)
+	LD	L, EZ80_FLSH_WS
+	EZ80_UTIL_FLSHWS_SET()
+	LD	A, L
+	LD	(EZ80_PLT_FLSHWS), A
+#ENDIF
+
+#IF (EZ80_FWSMD_TYP == EZ80WSMD_CALC)
+	LD	HL, EZ80_FLSH_MIN_NS
+	LD	E, 0
+	EZ80_CPY_EHL_TO_UHL
+	EZ80_UTIL_FLSHFQ_SET()
+	LD	A, L
+	LD	(EZ80_PLT_FLSHWS), A
+#ENDIF
+
+
+#IF (EZ80_WSMD_TYP == EZ80WSMD_CYCLES)
 	LD	L, EZ80_MEM_CYCLES
 	OR	$80
 	EZ80_UTIL_MEMTM_SET()
@@ -62,7 +79,7 @@ EZ80_PREINIT:
 	RET
 #ENDIF
 
-#IF (EZ80_ASSIGN == EZ80WSMD_CALC)
+#IF (EZ80_WSMD_TYP == EZ80WSMD_CALC)
 	LD	HL, EZ80_MEM_MIN_NS
 	LD	E, 0
 	EZ80_CPY_EHL_TO_UHL
@@ -80,7 +97,7 @@ EZ80_PREINIT:
 	LD	A, L
 	LD	(EZ80_PLT_IOWS), A
 #ENDIF
-#IF (EZ80_ASSIGN == EZ80WSMD_WAIT)
+#IF (EZ80_WSMD_TYP == EZ80WSMD_WAIT)
 	LD	L, EZ80_MEM_WS
 	EZ80_UTIL_MEMTM_SET()
 	LD	A, L
@@ -113,7 +130,6 @@ EZ80_RPT_MCYC:
 	CALL	PRTSTRD
 	.TEXT	" MEM B/C, $"
 
-
 EZ80_RPT_IOTIMING:
 	LD	A, (EZ80_PLT_IOWS)
 	BIT	7, A
@@ -121,14 +137,20 @@ EZ80_RPT_IOTIMING:
 
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" I/O W/S$"
-	RET
+	.TEXT	" I/O W/S, $"
+	JR	EZ80_RPT_FSH_TIMINGS
 
 EZ80_RPT_ICYC:
 	AND	$7F
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" I/O B/C$"
+	.TEXT	" I/O B/C, $"
+
+EZ80_RPT_FSH_TIMINGS:
+	LD	A, (EZ80_PLT_FLSHWS)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" FSH W/S$"
 	RET
 
 EZ80_RPT_FIRMWARE:
@@ -184,6 +206,8 @@ EZ80_PLT_MEMWS:
 	.DB	EZ80_MEM_WS
 EZ80_PLT_IOWS:
 	.DB	EZ80_IO_WS
+EZ80_PLT_FLSHWS:
+	.DB	EZ80_FLSH_WS
 
 EZ80_PLT_VERSION:
 	.DB	0, 0, 0, 0
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index ce0b0ba9..d52d744a 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -23,6 +23,9 @@
   #DEFINE EZ80_UTIL_IOTM_GET 		XOR A \ LD B, 11 \ EZ80_FN
   #DEFINE EZ80_UTIL_MEMTMFQ_SET		XOR A \ LD B, 12 \ EZ80_FN
   #DEFINE EZ80_UTIL_IOTMFQ_SET		XOR A \ LD B, 13 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHWS_SET		XOR A \ LD B, 14 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHWS_GET		XOR A \ LD B, 15 \ EZ80_FN
+  #DEFINE EZ80_UTIL_FLSHFQ_SET		XOR A \ LD B, 16 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 		LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 		LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm
index fe363778..b356f91c 100644
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -43,7 +43,7 @@ SN76489_PORT16_RIGHT	.EQU	(IO_SEGMENT*256) + SN76489_PORT_RIGHT
 
 #IF (CPUFAM == CPU_EZ80)
 ; The eZ80 configuration must have sufficient bus cycles configured for this driver
-; to work.  See the entries: (EZ80_ASSIGN and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS)
+; to work.  See the entries: (EZ80_WSMD_TYP and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS)
 ;
 ; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations
 ; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations

From 324c0bf0fbb0aea583cf3f73fc48ef8b9c4f1075 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 15:19:05 +1000
Subject: [PATCH 55/62] ez80: fix due to auto merging fault - #IF ((PLATFORM ==
 PLT_S100) & TRUE)

---
 Source/HBIOS/hbios.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index c53416ed..bf1e2892 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1858,7 +1858,7 @@ ROMRESUME:
 ; THEN IT MEANS THE S100 MONITOR IS ATTEMPTING TO REBOOT INTO ROMWBW
 ; HBIOS AND WE ABORT THE TRANSITION TO THE S100 MONITOR.
 ;
-#IF (PLATFORM == PLT_S100)
+#IF ((PLATFORM == PLT_S100) & TRUE)
 	; CHECK S100 BOARD DIP SWITCH, BIT 1
 	IN	A,($75)			; READ SWITCHES
 	BIT	1,A			; CHECK BIT 1

From 12df99084e9bee5b88b277e6a4c8860ae27e8682 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 15:21:49 +1000
Subject: [PATCH 56/62] ez80: removing additional comments on #ENDIF - to
 reduce number of 'diff' in large merge commit

---
 Source/HBIOS/hbios.asm | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index bf1e2892..fd9109a8 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1203,7 +1203,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 HBX_RETI:
 	RETI
 ;
-  #ELSE ; (MEMMGR == MM_Z280)
+  #ELSE
 ;
 ; COMMON INTERRUPT DISPATCHING CODE
 ; SETUP AND CALL HANDLER IN BIOS BANK
@@ -1255,13 +1255,13 @@ HBX_INT_SP	.EQU	$ - 2
 #ENDIF
 
 ;
-  #ENDIF ; END ELSE IF (MEMMGR == MM_Z280)
+  #ENDIF
 ;
-#ELSE ; #IF (INTMODE > 0)
+#ELSE
 ;
 	RET
 ;
-#ENDIF ; #END ELSE IF (INTMODE > 0)
+#ENDIF
 ;
 ; SMALL TEMPORARY STACK FOR USE BY HBX_BNKCPY
 ;

From 32301ba6a9b5aadab4b2d6504016eaf3a942fd98 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 15:24:04 +1000
Subject: [PATCH 57/62] ez80: fix auto mergine fault DIAG_DISP	.EQU
 DIAG_PROG

---
 Source/HBIOS/hbios.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index 2c6448e3..7c27b975 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -191,7 +191,7 @@ DIAG_7SEG	.EQU	4		; 7-SEGMENT
 DIAG_FLASH	.EQU	5		; FLASH
 DIAG_TRIG	.EQU	6		; TRIGGER
 ;
-DIAG_DISP	.EQU	DIAG_BINARY	; DEFAULT
+DIAG_DISP	.EQU	DIAG_PROG	; DEFAULT
 ;
 #IF (DIAG_DISP == DIAG_PROG)
 DIAG_00 .EQU 00000000B	

From e7937d47e382f20a9356494a17af96312d667ac0 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 15:26:37 +1000
Subject: [PATCH 58/62] ez80: revert whitespace introduced in recent large
 merge commit

---
 Source/HBIOS/tms.asm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm
index 0dd2fc33..00998e9a 100644
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -208,9 +208,9 @@ TMS_PREINIT:
 	; DISABLE INTERRUPT GENERATION UNTIL AFTER INTERRUPT HANDLER
 	; HAS BEEN INSTALLED.
 	LD	A, (TMS_INITVDU_REG_1)
-	RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
+        RES	TMSINTEN, A             ; RESET INTERRUPT ENABLE BIT
 	LD	(TMS_INITVDU_REG_1), A
-	LD	C, TMSCTRL1
+        LD	C, TMSCTRL1
 	JP	TMS_SET
 ;
 TMS_INIT:

From 7157d7f11d2ef1b710df8287b276a62414fbae28 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 15:30:05 +1000
Subject: [PATCH 59/62] ez80: delete bin (WDATE.COM and timer.com) within
 Source directroy incorrectly introduced in recent merge commit

---
 Source/RomDsk/ROM_384KB/WDATE.COM | Bin 2816 -> 0 bytes
 Source/RomDsk/ROM_384KB/timer.com | Bin 937 -> 0 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 Source/RomDsk/ROM_384KB/WDATE.COM
 delete mode 100644 Source/RomDsk/ROM_384KB/timer.com

diff --git a/Source/RomDsk/ROM_384KB/WDATE.COM b/Source/RomDsk/ROM_384KB/WDATE.COM
deleted file mode 100644
index c7ab78e304f4e190a716a56aebc7e2cfb0da4fa9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2816
zcmd^ATWl0n7(P2YGka?b+d?~~P|mnShg-W8gu3c9U_%MeR$&nXsb$*^-2&Zd_R{XQ
zuwr5~KA4dBV4{gWXd;S<0^(v~V%BESNplEmToX++PRQ^8LMXc6gPHoDnU;$r>Vt_7
z?q<&So$tS#vuFPEFGBzO&twH_h?iMX=ETqFsB4B8<SYUM`Hmys&>4`)H^K81N1A;m
z`a))OO?;Ijjf|y@&S?cY<@xkjfJ>VQ-_r9CDI<-vGuo^zOJtr@@wUSa%Rw`}L04H0
zl1tolNz~a|)JtyiuxwE?$cG+lH-?F%3bQikCRc2sEVogA*vDM~atJiYF22r9HZo^}
zPI8W^__UP*q&mQaKIR5Pr#aOKo#NC7k^h3LKHQ^|uifNr2ExEhUbe_-j(jjnLT9LG
zWe$CEhvw#7Z)fuBELqOO57xCpiLT~9!NG9^0)a(5s;VPDF=K%mN*|?^1R1@U*Z$t|
z&oTETr|J6VGCQg&?$D)k^!}yq${47b-3J+V@rayvNl)dZI&%x=3C~Qv!J1D4TS(dD
zJ1m<vU9G(M95?w8LmFJBLt0>n`>kq$!@FH36Gllq!PTN?meh|Gb>aPV%SkSDl7o8S
z$Tdb-W->tbIE4n&3FHN*P;K%+a!$cxm!e&Els7VBVz&Nnn}mxPW7HhQiKse;qspNX
zoK(`uN^kS1EsZMi#E=@R^rAH_Yu7!zenTtTm52-~Av`t^Nh)}6b9A%^@14jfk@yij
zF|5XtQNV#n=132oh^i?|9g3xr$`QObq4cY<fgTL$?C@aIn#d~Lua0EmLxa&Imim{s
z1Y6ePZOZ6S3~y4^n6e6YJh>f@u5AiJ)TYP)j-`hClz0eR6LlmB+iOB$RmH=RSO!Pp
zgQ;O9mP|CEE*0+xKY_YaNv!V2@kne?xxYtkhQOeRD74tH)`s;WszQWAWw{dWf$XIh
zL^BHIQWet+a&bDZYh|d->`f&3Kr=wp1HyGE#A&T8W6Qs6dRtxRHdy?ebtj=n%i$hz
z7jNH6cs<j4Q7f0Hn(gnUd8C$~wny#unU@OX_D*@eh|pB)RDIA<e`WcV$MG-I`JzTG
zpr?6v-PHqEcYtmF&AR4}%$9qFjos7Xo_#}k&F~|X%}H#aM)(anR4H3+Pi__ItWX|5
zjh*B@emsX=6Q%<*LakB1GCviXYAAVovrMA6(%Aq$H(+h+Znk&!9rSw<$?y~Bf{ar}
z%;7T<BmAtxI;6nEwKNL$l1mK{{GR2ZOMDxIHnqSg^d00;w<p|_hm-q3cEFK>tBi!3
z1*6oPJ}GetUqFDJ<u#bNveiD=by*vReTqkszuWCNipV~f*zL{+9@y?~>2k}c<$@dL
zp)PkvZ!N0Nni#ueG`5n%ztRn_*iKEkuc*Ed*yD3CV4x|4A7RkWlXqQ~Tj+v2CoKWn
zY#vB1T$~NFmdw$NS+iN<&DHR$>tzSH1PYsJuDSG%TpA96W~f|`s6m$<IcVgw_8hJN
zZ9M`}2Q?s+?yu7SLV-gzj+oA%qhZswQs2Q^)X2h1_Oy5E;hqxA24H4DMP1!w<ckIH
z@E>!4RLoPC)rL{%<dN9z^<?w<z9IT9ihE#yKo_kQ`ZA1?VaMp>r=>-Pe}GmI<u!(%
zo#Twa72&`%7~sEeohK)G#-Z!6@)F^ZacG-C(<!YoS!tQc!NW_7O&2_FNiaRqeA5e$
zPjZ_Tl3QLZxaCHHm6r-gg9gfqC%qa}I4hn7gpA_nfKI?K0a?HzAP4w8AP=Z}HSscV
z8nYLW#`FWym_vXxCJsnr(ttGPFrW+Yc|bSdi+~=$R{*_$uL1f1-vX=vJZ`UnoD7GY
zoP*^Vc55V-io`Q$v(gv0NM|J8A4MBS;zNf}XC#BRreX>VhcakmYA}^ZqMgb}QlVWE
zb@wM#ie2icEwn5BHrbhqL6=6I(2xPbDJ4O1w=xj3SvZ=CThiwE5Vh=#BvWxp+S=NX
zvBI3mn!B+#kTs8EHjvdd>-Aip(F)y{u1~dfOtnq59qq_mns+p>6?kveOvSO_?;yMc
zpO5mIJVUN|bJAl_Wd1Y0ELrTU4%GYu5YPB{k#Ig*KJv_5nstzd$F^*gv&7>Y3;gvs
MZH3#{>R(y^4-_PiqyPW_

diff --git a/Source/RomDsk/ROM_384KB/timer.com b/Source/RomDsk/ROM_384KB/timer.com
deleted file mode 100644
index 8c39f2ffdba8a94794391aee9906a377cf8497fb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 937
zcmbtRUr19?7(e%@vj$E^1h*c>CrZwk&P{|IaTQ0|piI>8K}2rurX$^5cYkn7LP7Kv
zz12exJqA4tDHtS*e=t1CY1_j<h#n*s^)PA=vp?!x-*qBUk9}}|=lg#5e81m!&dG;$
z>guZCX9TF?ZUG2iqWM{!GF+|5J1BoI=)!8AO6_kD6RhqY;aha`vY<Ox=LP;$SQfwX
z1#0?XNvAvqG$|4H0R@w1k1pC9@4ELWZ=igTTAx&+81BlXu##GMEsgUIYJG0do_(6M
zn=K|=iC2-N{Z)e1&m}i>*w8yS=LOxn`C8EXHy4Dp&vfl0-7UHIsrX?%mo1upTGCcR
z>Ig|;nmI}fnVl7J(Q{DJ*WmPdy)>sEKu!Ieo`Y)PS7l0~3`uEd2`u%}izPT=Dp*KL
z5?F$*XLF+#ibL#VR#@?H$^x!6IBkJt&nE3A%ub2B8CJ}4na*G}i(dveP2*{d6BSTo
zh5KmEfE6~xLv(be8UvFd_Nn&m<HmPgjVyPLsQf<NVMX-hk0=@zn5|X#w#{EsLEJa+
zSqagyi(n&`lH|O2^1^<;dtt*y(9?LK@??@3%K|&RvE_R4yDo3*v+1n_d!VKp*ca==
z3ejxssuZiNN~K8ft?<ToON@{b`R^F?UAxo|F;|Pr0j}2OUNzS2Zgq9kn7wK!t_8*?
zB4GD6fx$UoNR9^;L@hF*1Rc=Rdjop<u0pJh+z89#iU-PS!%puA3_CkVYRmx2bjuM9
z$6@ye!l6ky4r5VGQ-TqQ1f~=XV)A5EX)>COC~G-8%N4+JQ%upq0W}D6&<|0=_wN?(
zKP`Xg!<ZV31cFgD8lH?dkv>_Ir<4e~E1ITiU_Z9Kg;iOe_=02VR7j2lZcZxD?Ylkz
m`0r>82V6O1Vr?z$pec8v0Zs7}7z~Wv4m*IrfP#kpF!>FJ%u>_<


From c31f9de905a09eba067ccbdb52fca007b48718d8 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 18:44:15 +1000
Subject: [PATCH 60/62] ez80: some additional comments for the ez80 cpu driver

---
 Source/HBIOS/ez80cpudrv.asm | 25 +++++++++++++++++++------
 Source/HBIOS/ez80rtc.asm    |  2 +-
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 7f5eb6e8..b972e272 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -1,15 +1,28 @@
 ;
 ;==================================================================================================
-; EZ80 50/60HZ TIMER TICK DRIVER
+; RCBUS EZ80 CPU DRIVER
 ;==================================================================================================
 ;
-; Communicate with on-chip eZ80 firmware to:
+; Driver code designed for the RCBus eZ80 CPU Module.  
+; The driver expects the eZ80 firmware to manage the initial booting of the system.
+; Details for the platform and the software for the on-chip firmware can be found at:
+; https://github.com/dinoboards/rc2014-ez80
+;
+; Although the eZ80 firmware is booted before HBIOS, the eZ80 CPU driver is still required
+; to communicate with the firmware to perform a number of initialisation tasks.
+; See also the associated ez80 platform drivers (ez80rtc, ez80systmr, ez80uart).
+;
+; The driver 'exports' two key functions:
+; 1. EZ80_PREINIT - This function is called by the HBIOS boot code to initialise the eZ80 firmware.
+; 2. EZ80_RPT_TIMINGS - This function is called by the HBIOS boot code to report the platform timings.
+;
+; EZ80_PREINIT performs the following:
 ; 1. Exchange platform version numbers
-; 2. Configure memory banking type
-; 3. Retrieve CPU Frequency
-; 4. Set Memory and I/O Bus Timings
-; 5. Set Timer Tick Frequency
+; 2. Retrieve CPU Frequency
+; 3. Set Memory and I/O Bus Timings
+; 4. Set Timer Tick Frequency
 ;
+
 EZ80_PREINIT:
 	EZ80_TMR_INT_DISABLE()
 
diff --git a/Source/HBIOS/ez80rtc.asm b/Source/HBIOS/ez80rtc.asm
index 2625c278..8576962f 100644
--- a/Source/HBIOS/ez80rtc.asm
+++ b/Source/HBIOS/ez80rtc.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-; EZ80 ON-CHIP CLOCK DRIVER
+; EZ80 ON-CHIP RTC DRIVER
 ;==================================================================================================
 ;
 EZ80RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)

From 0982b5d4622b80161b8ac62b2a49df0c969ca920 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 19:11:14 +1000
Subject: [PATCH 61/62] ez80: align cfg/std configuration files as per recent
 changes

---
 Source/HBIOS/Config/RCEZ80_std.asm     | 100 ++--
 Source/HBIOS/Config/RCZ80_easy_std.asm |   2 +-
 Source/HBIOS/Config/RCZ80_tiny_std.asm |   2 +-
 Source/HBIOS/cfg_DUO.asm               |   4 +-
 Source/HBIOS/cfg_DYNO.asm              |   4 +-
 Source/HBIOS/cfg_EPITX.asm             |   4 +-
 Source/HBIOS/cfg_FZ80.asm              |   4 +-
 Source/HBIOS/cfg_GMZ180.asm            |   4 +-
 Source/HBIOS/cfg_HEATH.asm             |   4 +-
 Source/HBIOS/cfg_MBC.asm               |   4 +-
 Source/HBIOS/cfg_MK4.asm               |   4 +-
 Source/HBIOS/cfg_MON.asm               |   4 +-
 Source/HBIOS/cfg_N8.asm                |   4 +-
 Source/HBIOS/cfg_NABU.asm              |   4 +-
 Source/HBIOS/cfg_RCZ180.asm            |   4 +-
 Source/HBIOS/cfg_RCZ280.asm            |   4 +-
 Source/HBIOS/cfg_RCZ80.asm             |   4 +-
 Source/HBIOS/cfg_RPH.asm               |   4 +-
 Source/HBIOS/cfg_S100.asm              |   4 +-
 Source/HBIOS/cfg_SBC.asm               |   4 +-
 Source/HBIOS/cfg_SCZ180.asm            |   4 +-
 Source/HBIOS/cfg_Z80RETRO.asm          |   4 +-
 Source/HBIOS/cfg_ZETA.asm              |   4 +-
 Source/HBIOS/cfg_ZETA2.asm             |   4 +-
 Source/HBIOS/cfg_rcez80.asm            | 767 +++++++++++++------------
 25 files changed, 509 insertions(+), 446 deletions(-)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index f0a7cd92..a36b51ac 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -1,74 +1,82 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS EZ80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
 ;
-#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
 ;
-#include "cfg_rcez80.asm"
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
 ;
-CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
 ;
-CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
 ;
-FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
-UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+#INCLUDE "cfg_rcez80.asm"
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 ;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-;
-AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
-FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FD0TYPE		.EQU	FDT_5HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 ;
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
-SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
 IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-
-EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
-EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
-EZ80TIMER	.SET	EZ80TMR_FIRM	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
diff --git a/Source/HBIOS/Config/RCZ80_easy_std.asm b/Source/HBIOS/Config/RCZ80_easy_std.asm
index c9a526a1..d77c57dc 100644
--- a/Source/HBIOS/Config/RCZ80_easy_std.asm
+++ b/Source/HBIOS/Config/RCZ80_easy_std.asm
@@ -48,7 +48,7 @@
 ;
 #INCLUDE "cfg_RCZ80.asm"
 ;
-PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 ;
 CPUOSC		.SET	10000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
diff --git a/Source/HBIOS/Config/RCZ80_tiny_std.asm b/Source/HBIOS/Config/RCZ80_tiny_std.asm
index 1e6f2cab..d03c28be 100644
--- a/Source/HBIOS/Config/RCZ80_tiny_std.asm
+++ b/Source/HBIOS/Config/RCZ80_tiny_std.asm
@@ -48,7 +48,7 @@
 ;
 #INCLUDE "cfg_RCZ80.asm"
 ;
-PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
 ;
 CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm
index 80d62dcd..8a2dfe92 100644
--- a/Source/HBIOS/cfg_DUO.asm
+++ b/Source/HBIOS/cfg_DUO.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm
index 29e533c7..b73e8d52 100644
--- a/Source/HBIOS/cfg_DYNO.asm
+++ b/Source/HBIOS/cfg_DYNO.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm
index f9ba6fb3..7442aa60 100644
--- a/Source/HBIOS/cfg_EPITX.asm
+++ b/Source/HBIOS/cfg_EPITX.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_FZ80.asm b/Source/HBIOS/cfg_FZ80.asm
index 1b5d2bf5..dc5c7848 100644
--- a/Source/HBIOS/cfg_FZ80.asm
+++ b/Source/HBIOS/cfg_FZ80.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_FZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_FZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm
index fbee4244..02d10263 100644
--- a/Source/HBIOS/cfg_GMZ180.asm
+++ b/Source/HBIOS/cfg_GMZ180.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm
index 0bc354ed..d5b38754 100644
--- a/Source/HBIOS/cfg_HEATH.asm
+++ b/Source/HBIOS/cfg_HEATH.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm
index 83fefef7..48bf0f40 100644
--- a/Source/HBIOS/cfg_MBC.asm
+++ b/Source/HBIOS/cfg_MBC.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm
index 8f51dcaa..ba3674a3 100644
--- a/Source/HBIOS/cfg_MK4.asm
+++ b/Source/HBIOS/cfg_MK4.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm
index 885fcf07..b786e4c3 100644
--- a/Source/HBIOS/cfg_MON.asm
+++ b/Source/HBIOS/cfg_MON.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm
index ae3b6df9..8c6c06ca 100644
--- a/Source/HBIOS/cfg_N8.asm
+++ b/Source/HBIOS/cfg_N8.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm
index 01174339..14e77dfd 100644
--- a/Source/HBIOS/cfg_NABU.asm
+++ b/Source/HBIOS/cfg_NABU.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm
index b90567fb..e6ea12cb 100644
--- a/Source/HBIOS/cfg_RCZ180.asm
+++ b/Source/HBIOS/cfg_RCZ180.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm
index e9e6e629..3b803233 100644
--- a/Source/HBIOS/cfg_RCZ280.asm
+++ b/Source/HBIOS/cfg_RCZ280.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm
index 56279490..3fb1e537 100644
--- a/Source/HBIOS/cfg_RCZ80.asm
+++ b/Source/HBIOS/cfg_RCZ80.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm
index 41021e1b..bb5f3e7e 100644
--- a/Source/HBIOS/cfg_RPH.asm
+++ b/Source/HBIOS/cfg_RPH.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm
index fbffdab6..a5a3b380 100644
--- a/Source/HBIOS/cfg_S100.asm
+++ b/Source/HBIOS/cfg_S100.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm
index fc569260..9a539be0 100644
--- a/Source/HBIOS/cfg_SBC.asm
+++ b/Source/HBIOS/cfg_SBC.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm
index 38416754..8234fbc9 100644
--- a/Source/HBIOS/cfg_SCZ180.asm
+++ b/Source/HBIOS/cfg_SCZ180.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm
index b2640ee3..99356548 100644
--- a/Source/HBIOS/cfg_Z80RETRO.asm
+++ b/Source/HBIOS/cfg_Z80RETRO.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm
index e832496a..a57b02e6 100644
--- a/Source/HBIOS/cfg_ZETA.asm
+++ b/Source/HBIOS/cfg_ZETA.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm
index caaa9bbe..44f12023 100644
--- a/Source/HBIOS/cfg_ZETA2.asm
+++ b/Source/HBIOS/cfg_ZETA2.asm
@@ -46,8 +46,8 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+PLATFORM	.SET	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 69755013..e9ed81c1 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -1,373 +1,428 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZE80
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
-;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
-;
-PLATFORM	.EQU	PLT_RCEZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
-EZ80IOBASE	.EQU	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
-;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
-;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (EZ80 operates with IM 2 - simulating IM 1)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
-;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+#INCLUDE "cfg_MASTER.asm"
+;
+PLATFORM	.SET	PLT_RCEZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+;
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+;
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
+;
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+
+; EZ80 SETTINGS
 ;
+EZ80TMR_NONE	.SET	0		; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS
+EZ80TMR_INT	.SET	1		; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
+EZ80TMR_FIRM	.SET	2		; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
+
+EZ80UARTENABLE	.SET	TRUE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
+EZ80RTCENABLE	.SET	TRUE		; EZ80 ON CHIP RTC
+EZ80TIMER	.SET	EZ80TMR_FIRM	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+EZ80IOBASE	.SET	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
+
 ; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
-EZ80_MEM_CYCLES	.EQU	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
-EZ80_MEM_MIN_NS	.EQU	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
-EZ80_MEM_WS	.EQU	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
-EZ80_MEM_MIN_WS	.EQU	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_MEM_CYCLES	.SET	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_MEM_MIN_NS	.SET	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_MEM_WS	.SET	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_MEM_MIN_WS	.SET	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
-;
 ; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
-EZ80_IO_CYCLES	.EQU	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
-EZ80_IO_WS	.EQU	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
-EZ80_IO_MIN_NS	.EQU	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
-EZ80_IO_MIN_WS	.EQU	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_CYCLES	.SET	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_IO_WS	.SET	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.SET	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_MIN_WS	.SET	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
 
 ; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
 EZ80_WSMD_TYP	.EQU	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
 ;
 ; BUS TIMING FOR ON CHIP ROM
 ;
-EZ80_FLSH_WS	.EQU	1		; WAIT STATES FOR ON CHIP FLASH (0-7)
-EZ80_FLSH_MIN_NS .EQU	60	; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
-EZ80_FWSMD_TYP	.EQU	EZ80WSMD_CALC	; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)
-;
-;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
-;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
-;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
-;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
-;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
-;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
-;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
-;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
-;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
-;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
-;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
-;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
-;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
-;
-EZ80RTCENABLE	.EQU	TRUE		; EZ80 ON CHIP RTC
-;
-EZ80TMR_NONE	.EQU	0		; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS
-EZ80TMR_INT	.EQU	1		; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
-EZ80TMR_FIRM	.EQU	2		; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
-EZ80TIMER	.EQU	EZ80TMR_INT	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
-;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
-;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
-;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
-;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
-;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
-;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
-;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
-;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
-;
-EZ80UARTENABLE	.EQU	TRUE		; EZ80UART: ENABLE EZ80 UART SERIAL DRIVER (EZ80UART.ASM)
-;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
-;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80]
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
-;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
-;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
-;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$88		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
-;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
-;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
-;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
-;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
-;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
-;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
-;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
-;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
-;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
-;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-SN76489CHNOUT	.EQU	SNCHAN_LEFT	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
-;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
-;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
-;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
-;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+EZ80_FLSH_WS	.SET	1		; WAIT STATES FOR ON CHIP FLASH (0-7)
+EZ80_FLSH_MIN_NS .SET	60		; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_FWSMD_TYP	.SET	EZ80WSMD_CALC	; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)

From 3121e3ee9d59ea35db8cadc7cd032dc123de0fe2 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sun, 15 Sep 2024 19:13:05 +1000
Subject: [PATCH 62/62] ez80: renamed cfg_rcez80 to uppercase cfg_RCEZ80.asm

---
 Source/HBIOS/Config/RCEZ80_std.asm              | 2 +-
 Source/HBIOS/{cfg_rcez80.asm => cfg_RCEZ80.asm} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename Source/HBIOS/{cfg_rcez80.asm => cfg_RCEZ80.asm} (100%)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index a36b51ac..93129cff 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -44,7 +44,7 @@
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-#INCLUDE "cfg_rcez80.asm"
+#INCLUDE "cfg_RCEZ80.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 ;
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_RCEZ80.asm
similarity index 100%
rename from Source/HBIOS/cfg_rcez80.asm
rename to Source/HBIOS/cfg_RCEZ80.asm