Minor Z280 Fixes

- Fixed the ROM VERIFY functionality on Z280.  It was indicating errors incorrectly.
- Revised the way that ZZRCC is built to remove a bunch of complexity that was causing issues.  An implication of this is that ZZRCC now treats the data loaded from the CF Card as a ROM disk instead of a RAM disk.
- Updated the assemblers to handle some more Z280 instructions used in HBIOS.
- When building ZZRCC, checks have been added to ensure the ROM image is exactly 256K.  The build defaults to 512K and that causes the ZZRCC disk image to be corrupted.  This will stop the build if the user fails to specify a 256K ROM size.

Tools/tasm32/TASM280.TAB

@@ -127,8 +127,8 @@ DEC  L       2D   1 NOP 1
 DEC  SP      3B   1 NOP 1
 DI   ""      F3   1 NOP 1
 DJNZ *       10   2 R1  1
-
 EI   ""      FB   1 NOP 1
+EI   *       7FED 3 NOP 1	/* Z280 */
 EX   (SP),HL E3   1 NOP 1
 EX   (SP),IX E3DD 2 NOP 1
 EX   (SP),IY E3FD 2 NOP 1
@@ -158,6 +158,8 @@ IN   L,(C)   68ED 2 NOP 1
 
 IN   A,(*)   DB   2 NOP 1
 
+INW  HL,(C)  B7ED 2 NOP 1	/* Z280 */
+
 IN0   A,(*)  38ED 3 NOP 2
 IN0   B,(*)  00ED 3 NOP 2
 IN0   C,(*)  08ED 3 NOP 2
@@ -342,6 +344,8 @@ LD   SP,HL   F9   1 NOP 1
 LD   SP,IX   F9DD 2 NOP 1
 LD   SP,IY   F9FD 2 NOP 1
 LD   SP,*    31   3 NOP 1
+LDUD  A,(HL) 86ED 2 NOP 1	/* Z280 */
+LDUP  A,(HL) 96ED 2 NOP 1	/* Z280 */
 LDCTL (C),HL 6EED 2 NOP 1	/* Z280 */
 LDCTL HL,(C) 66ED 2 NOP 1	/* Z280 */
 LDCTL USP,HL 8FED 2 NOP 1	/* Z280 */
@@ -378,6 +382,7 @@ OTDR ""      BBED 2 NOP 1
 OTIM ""      83ED 2 NOP 2
 OTIMR ""     93ED 2 NOP 2
 OTIR ""      B3ED 2 NOP 1
+OTIRW ""     93ED 2 NOP 1	/* Z280 */
 
 OUT  (C),A   79ED 2 NOP 1
 OUT  (C),B   41ED 2 NOP 1
@@ -524,6 +529,9 @@ SBC  HL,DE   52ED 2 NOP 1
 SBC  HL,HL   62ED 2 NOP 1
 SBC  HL,SP   72ED 2 NOP 1
 SBC  A,*     DE   2 NOP 1
+
+SC   *       71ED 4 NOP 1	/* Z280 */
+
 SCF  ""      37   1 NOP 1
 
 SET  *,(HL)  C6CB 2 ZBIT 1

Tools/unix/uz80as/z80.c

@@ -210,6 +210,13 @@ static const struct matchtab s_matchtab_z80[] = {
 	{ "MULTU A,a", "FD.ED.F9.d0.", 4, 0 },
 	{ "OUTW (C),HL", "ED.BF.", 4, 0 },
 	{ "RETIL", "ED.55.", 4, 0 },
+	{ "EI a", "ED.7F.d0.", 4, 0 },
+	{ "SC a", "ED.71.e0", 4, 0 },
+	{ "OTIRW", "ED.93.", 4, 0 },
+	{ "LDUD A,(HL)", "ED.86.", 4, 0 },
+	{ "LDUP A,(HL)", "ED.96.", 4, 0 },
+	{ "ADD HL,A", "ED.6D.", 4, 0 },
+	{ "INW HL,(C)", "ED.B7.", 4, 0 },
 	{ NULL, NULL },
 };