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Merge pull request #12 from wwarthen/dev 

Dev
pull/290/head
b1ackmai1er 4 years ago
committed by GitHub
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4af5d457eb 1b34dc0941
commit
c046f0365c
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
29 changed files with 639 additions and 158 deletions
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  1. 228
      Source/Apps/Test/ps2info/ps2info.asm
  2. 11
      Source/Apps/rtc.asm
  3. 1
      Source/HBIOS/Build.cmd
  4. 2
      Source/HBIOS/Build.ps1
  5. 1
      Source/HBIOS/Build.sh
  6. 47
      Source/HBIOS/Config/RPH_std.asm
  7. 2
      Source/HBIOS/Makefile
  8. 58
      Source/HBIOS/asci.asm
  9. 5
      Source/HBIOS/cfg_dyno.asm
  10. 4
      Source/HBIOS/cfg_ezz80.asm
  11. 10
      Source/HBIOS/cfg_master.asm
  12. 4
      Source/HBIOS/cfg_mbc.asm
  13. 5
      Source/HBIOS/cfg_mk4.asm
  14. 5
      Source/HBIOS/cfg_n8.asm
  15. 5
      Source/HBIOS/cfg_rcz180.asm
  16. 4
      Source/HBIOS/cfg_rcz280.asm
  17. 4
      Source/HBIOS/cfg_rcz80.asm
  18. 249
      Source/HBIOS/cfg_rph.asm
  19. 4
      Source/HBIOS/cfg_sbc.asm
  20. 5
      Source/HBIOS/cfg_scz180.asm
  21. 2
      Source/HBIOS/cfg_una.asm
  22. 4
      Source/HBIOS/cfg_zeta.asm
  23. 4
      Source/HBIOS/cfg_zeta2.asm
  24. 36
      Source/HBIOS/dsrtc.asm
  25. 89
      Source/HBIOS/hbios.asm
  26. 1
      Source/HBIOS/hbios.inc
  27. 3
      Source/HBIOS/std.asm
  28. 2
      Source/ver.inc
  29. 2
      Source/ver.lib

228
Source/Apps/Test/ps2info/ps2info.asm
View File

@ -6,12 +6,20 @@
; Simple utility that performs simple tests of an 8242 PS/2 controller,
; keyboard, and mouse.
;
; WBW 2022-03-28: Add menu driven port selection
; Add support for RHYOPHYRE
; WBW 2022-04-01: Add menu for test functions
;
;=======================================================================
;
; PS/2 Keyboard/Mouse controller port addresses (adjust as needed)
;
iocmd .equ $E3 ; PS/2 controller command port address
iodat .equ $E2 ; PS/2 controller data port address
; MBC:
iocmd_mbc .equ $E3 ; PS/2 controller command port address
iodat_mbc .equ $E2 ; PS/2 controller data port address
; RPH:
iocmd_rph .equ $8D ; PS/2 controller command port address
iodat_rph .equ $8C ; PS/2 controller data port address
;
cpumhz .equ 8 ; for time delay calculations (not critical)
;
@ -37,6 +45,8 @@ bdos .equ $0005 ; BDOS invocation vector
call crlf
ld de,str_banner ; banner
call prtstr
;
call setup
;
call main ; do the real work
;
@ -50,52 +60,95 @@ exit:
ld sp,(stksav) ; restore stack
jp restart ; return to CP/M via restart
;
;
;=======================================================================
; Main Program
; Select and setup for hardware
;=======================================================================
;
main:
;
; Display active controller port addresses
;
setup:
call crlf2
ld de,str_hwmenu
call prtstr
setup1:
ld c,$06 ; BDOS direct console I/O
ld e,$FF ; Subfunction = read
call bdos
cp 0
jr z,setup1
call upcase
call prtchr
cp '1' ; MBC
jr z,setup_mbc
cp '2' ; RHYOPHYRE
jr z,setup_rph
cp 'X'
jr z,exit
jr setup
;
setup_mbc:
ld a,iocmd_mbc
ld (iocmd),a
ld a,iodat_mbc
ld (iodat),a
ld de,str_mbc
jr setup2
;
setup_rph:
ld a,iocmd_rph
ld (iocmd),a
ld a,iodat_rph
ld (iodat),a
ld de,str_rph
jr setup2
;
setup2:
call prtstr
call crlf2
ld de,str_cmdport
call prtstr
ld a,iocmd
;ld a,iocmd
ld a,(iocmd)
call prthex
call crlf
ld de,str_dataport
call prtstr
ld a,iodat
;ld a,iodat
ld a,(iodat)
call prthex
;
call test_ctlr
jr z,main0 ; continue if ctlr OK
ld de,str_kbd_failed
call crlf2
call prtstr
jr mainz ; bail out if ctlr fails
xor a
ret
;
main0:
call test_kbd
jr z,main1 ; completed all tests, continue
ld de,str_kbd_failed
call crlf2
call prtstr
;=======================================================================
; Main Program
;=======================================================================
;
main1:
call test_mse
jr z,main2 ; completed all tests, continue
ld de,str_mse_failed
main:
call crlf2
ld de,str_menu
call prtstr
main1:
ld c,$06 ; BDOS direct console I/O
ld e,$FF ; Subfunction = read
call bdos
cp 0
jr z,main1
call upcase
call prtchr
cp 'X'
jp z,exit
call main2
jr main
;
main2:
call test_kbdmse
;
mainz:
xor a
; Dispatch to test functions
cp 'C' ; Test Controller
jp z,test_ctlr
cp 'K' ; Test Keyboard
jp z,test_kbd
cp 'M' ; Test Mouse
jp z,test_mse
cp 'B' ; Test Both
jp z,test_kbdmse
ret
;
; Test 8242 PS/2 Controller
@ -109,10 +162,8 @@ test_ctlr:
ret nz
;
call ctlr_test_p1
;ret nz
;
call ctlr_test_p2
;ret nz
;
ret
;
@ -123,13 +174,15 @@ test_kbd:
; First, we attempt to contact the controller and keyboard, then
; print the keyboard identity and scan codes supported
;
; Run test series with translation off
call crlf2
ld de,str_basic
call prtstr
;
call ctlr_test
jr nz,test_kbd_fail
;
call test_kbd_basic
ret nz
jr nz,test_kbd_fail
;
; We make two passes through the test series with different controller
; setup values. The first time is with scan code translation off and
@ -155,59 +208,83 @@ test_kbd:
;
ret
;
test_kbd_fail:
ld de,str_kbd_failed
call crlf2
call prtstr
ret
;
; Test Mouse
;
test_mse:
call crlf2
ld de,str_basic_mse
call prtstr
;
call ctlr_test
jr nz,test_mse_fail
;
ld a,$10 ; kbd disabled, mse enabled, no ints
call ctlr_setup
ret nz
jr nz,test_mse_fail
;
call mse_reset
ret nz
jr nz,test_mse_fail
;
call mse_ident
ret nz
jr nz,test_mse_fail
;
call mse_stream
ret nz
jr nz,test_mse_fail
;
call mse_echo
;
xor a ; signal success
ret
;
test_mse_fail:
ld de,str_mse_failed
call crlf2
call prtstr
ret
;
; Test Everything
;
test_kbdmse:
call crlf2
ld de,str_kbdmse
call prtstr
;
call ctlr_test
jr nz,test_kbdmse_fail
;
ld a,$00 ; kbd enabled, mse enabled, no ints
call ctlr_setup
ret nz
jr nz,test_kbdmse_fail
;
call kbd_reset
ret nz
jr nz,test_kbdmse_fail
;
ld a,2
call kbd_setsc
;
call mse_reset
ret nz
jr nz,test_kbdmse_fail
;
call mse_stream
ret nz
jr nz,test_kbdmse_fail
;
call kbdmse_echo
;
xor a ; signal success
ret
;
test_kbdmse_fail:
ld de,str_kbdmse_failed
call crlf2
call prtstr
ret
;
; Perform basic keyboard tests, display keyboard identity, and
; inventory the supported scan code sets.
;
@ -782,7 +859,9 @@ wait_write:
ld a,(timeout) ; setup timeout constant
ld b,a
wait_write1:
in a,(iocmd) ; get status
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
in a,(c) ; get status
ld c,a ; save status
and $02 ; isolate input buf status bit
ret z ; 0 means ready, all done
@ -804,7 +883,9 @@ wait_read:
ld a,(timeout) ; setup timeout constant
ld b,a
wait_read1:
in a,(iocmd) ; get status
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
in a,(c) ; get status
ld c,a ; save status
and $01 ; isolate input buf status bit
xor $01 ; invert so 0 means ready
@ -824,7 +905,9 @@ check_read:
; Check for data ready to read
; A=0 indicates data available (ZF set)
;
in a,(iocmd) ; get status
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
in a,(c) ; get status
and $01 ; isolate input buf status bit
xor $01 ; invert so 0 means ready
ret
@ -834,7 +917,9 @@ check_read_kbd:
; Check for keyboard data ready to read
; A=0 indicates data available (ZF set)
;
in a,(iocmd) ; get status
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
in a,(c) ; get status
and %00100001 ; isolate input buf status bit
cp %00000001 ; data ready, not mouse
ret
@ -844,7 +929,9 @@ check_read_mse:
; Check for mouse data ready to read
; A=0 indicates data available (ZF set)
;
in a,(iocmd) ; get status
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
in a,(c) ; get status
and %00100001 ; isolate input buf status bit
cp %00100001 ; data ready, is mouse
ret
@ -860,8 +947,10 @@ put_cmd:
scf ; else, signal timeout error
ret ; and bail out
put_cmd1:
ld a,(iocmd) ; cmd port
ld c,a ; ... to C
ld a,e ; recover value to write
out (iocmd),a ; write it
out (c),a ; write it
or a ; clear CF for success
ret
;
@ -889,8 +978,10 @@ put_data:
scf ; else, signal timeout error
ret ; and bail out
put_data1:
ld a,(iodat) ; data port
ld c,a ; ... to C
ld a,e ; recover value to write
out (iodat),a ; write it
out (c),a ; write it
or a ; clear CF for success
ret
;
@ -947,7 +1038,9 @@ get_data:
scf ; else signal timeout error
ret ; and bail out
get_data1:
in a,(iodat) ; get data byte
ld a,(iodat) ; data port
ld c,a ; ... to C
in a,(c) ; get data byte
or a ; clear CF for success
ret
;
@ -1020,7 +1113,6 @@ err_ret:
; Utility Routines
;=======================================================================
;
;
; Print character in A without destroying any registers
;
prtchr:
@ -1044,6 +1136,16 @@ prtdot:
pop af ; restore af
ret ; done
;
; Uppercase character in A
;
upcase:
cp 'a' ; below 'a'?
ret c ; if so, nothing to do
cp 'z'+1 ; above 'z'?
ret nc ; if so, nothing to do
and ~$20 ; convert character to lower
ret ; done
;
; Print a zero terminated string at (de) without destroying any registers
;
prtstr:
@ -1239,7 +1341,21 @@ delay1:
; Constants
;=======================================================================
;
str_banner .db "PS/2 Keyboard/Mouse Information v0.4, 7-Jan-2022",0
str_banner .db "PS/2 Keyboard/Mouse Information v0.6, 1-Apr-2022",0
str_hwmenu .db "PS/2 Controller Port Options:\r\n\r\n"
.db " 1 - MBC\r\n"
.db " 2 - RHYOPHYRE\r\n"
.db " X - Exit Application\r\n"
.db "\r\nSelection? ",0
str_mbc .db "MBC",0
str_rph .db "RHYOPHYRE",0
str_menu .db "PS/2 Testing Options:\r\n\r\n"
.db " C - Test PS/2 Controller\r\n"
.db " K - Test PS/2 Keyboard\r\n"
.db " M - Test PS/2 Mouse\r\n"
.db " B - Test Both PS/2 Keyboard and Mouse Together\r\n"
.db " X - Exit Application\r\n"
.db "\r\nSelection? ",0
str_exit .db "Done, Thank you for using PS/2 Keyboard/Mouse Information!",0
str_cmdport .db "Controller Command Port: ",0
str_dataport .db "Controller Data Port: ",0
@ -1312,6 +1428,11 @@ str_mse_failed .db "***** MOUSE HARDWARE ERROR *****",13,10,13,10
.db "the completion of the full set of mouse tests.",13,10
.db "Check your hardware and verify the port",13,10
.db "addresses being used for the controller",0
str_kbdmse_failed .db "***** KEYBOARD/MOUSE HARDWARE ERROR *****",13,10,13,10
.db "A basic hardware or configuration issue prevented",13,10
.db "the completion of the full set of keyboard/mouse tests.",13,10
.db "Check your hardware and verify the port",13,10
.db "addresses being used for the controller",0
;
;=======================================================================
; Working data
@ -1321,6 +1442,9 @@ stksav .dw 0 ; stack pointer saved at start
.fill stksiz,0 ; stack
stack .equ $ ; stack top
;
iocmd .db 0
iodat .db 0
;
workbuf .fill 8
workbuf_len .db 0
;

11
Source/Apps/rtc.asm
View File

@ -29,6 +29,8 @@
;
;[2021/07/10] v1.7 Support MBC (AJL)
;
;[2022/03/27] v1.8 Support RHYOPHYRE
;
; Constants
;
mask_data .EQU %10000000 ; RTC data line
@ -46,6 +48,7 @@ PORT_SCZ180 .EQU $0C ; RTC port for SCZ180
PORT_DYNO .EQU $0C ; RTC port for DYNO
PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280
PORT_MBC .EQU $70 ; RTC port for MBC
PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE
BDOS .EQU 5 ; BDOS invocation vector
@ -1126,6 +1129,11 @@ HINIT:
LD DE,PLT_MBC
CP 13 ; MBC
JR Z,RTC_INIT2
;
LD C,PORT_RPH
LD DE,PLT_RPH
CP 14 ; RHYOPHYRE
JR Z,RTC_INIT2
;
; Unknown platform
LD DE,PLTERR ; BIOS error message
@ -1622,7 +1630,7 @@ TESTING_BIT_DELAY_OVER:
RTC_HELP_MSG:
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "RTC: Version 1.7"
.TEXT "RTC: Version 1.8"
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp"
.DB 0Ah, 0Dh ; line feed and carriage return
@ -1751,6 +1759,7 @@ PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$"
PLT_RCZ280 .TEXT ", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$"
PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$"
;
; Generic FOR-NEXT loop algorithm

1
Source/HBIOS/Build.cmd
View File

@ -211,5 +211,6 @@ call Build EZZ80 std 512 || exit /b
call Build EZZ80 tz80 512 || exit /b
call Build DYNO std 512 || exit /b
call Build UNA std 512 || exit /b
call Build RPH std 512 || exit /b
goto :eof

2
Source/HBIOS/Build.ps1
View File

@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
#
$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
$PlatformListZ280 = "RCZ280"
#

1
Source/HBIOS/Build.sh
View File

@ -27,6 +27,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh
ROM_PLATFORM="RPH"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh

47
Source/HBIOS/Config/MBC_ddw.asm → Source/HBIOS/Config/RPH_std.asm
View File

@ -1,6 +1,6 @@
;
;==================================================================================================
; MBC CONFIGURATION
; RHYOPHYRE STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
@ -22,35 +22,20 @@
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#DEFINE PLATFORM_NAME "Multi Board Computer"
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
;
#include "cfg_mbc.asm"
;
CPUOSC .EQU 4000000 ; CPU OSC FREQ IN MHZ
;
BATCOND .SET FALSE
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
DSKYENABLE .SET TRUE ; ENABLES DSKY
DSKYMODE .SET DSKYMODE_NG ; DSKY VERTSION: DSKYMODE_[V1|NG]
DSKYOSC .SET 100000
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
;DIAGLVL .EQU DL_VERBOSE
DMAENABLE .EQU TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
INTMODE .SET 2
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
AY38910ENABLE .EQU TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU CPUOSC / 2 ; DEFAULT TO CPUOSC / 4
AYMODE .EQU AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
#include "cfg_rph.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
;
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

2
Source/HBIOS/Makefile
View File

@ -12,7 +12,7 @@ include $(TOOLS)/Makefile.inc
FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO),)
ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO RPH),)
TASM=$(BINDIR)/uz80as -t hd64180
endif

58
Source/HBIOS/asci.asm
View File

@ -75,10 +75,14 @@ ASCI1_BASE .EQU Z180_BASE + 1 ; RELATIVE TO Z180 INTERNAL IO PORTS
;
ASCI_RTS .EQU %00010000 ; ~RTS BIT OF CNTLA REG
;
#IF (INTMODE == 2)
#IF (ASCIINTS)
;
#IF (INTMODE == 2)
;
ASCI0_IVT .EQU IVT(INT_SER0)
ASCI1_IVT .EQU IVT(INT_SER1)
;
#ENDIF
;
#ENDIF
;
@ -115,25 +119,29 @@ ASCI_PREINIT2:
ADD IY,DE ; BUMP IY TO NEXT ENTRY
DJNZ ASCI_PREINIT0 ; LOOP UNTIL DONE
;
#IF (INTMODE >= 1)
#IF (ASCIINTS)
;
#IF (INTMODE >= 1)
; SETUP INT VECTORS AS APPROPRIATE
LD A,(ASCI_DEV) ; GET DEVICE COUNT
OR A ; SET FLAGS
JR Z,ASCI_PREINIT3 ; IF ZERO, NO ASCI DEVICES, ABORT
;
#IF (INTMODE == 1)
#IF (INTMODE == 1)
; ADD IM1 INT CALL LIST ENTRY
LD HL,ASCI_INT ; GET INT VECTOR
CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST
#ENDIF
#ENDIF
;
#IF (INTMODE == 2)
#IF (INTMODE == 2)
; SETUP IM2 VECTORS
LD HL,ASCI_INT0
LD (ASCI0_IVT),HL ; IVT INDEX
LD HL,ASCI_INT1
LD (ASCI1_IVT),HL ; IVT INDEX
#ENDIF
#ENDIF
;
#ENDIF
;
#ENDIF
;
@ -188,7 +196,9 @@ ASCI_INIT1:
;
; RECEIVE INTERRUPT HANDLER
;
#IF (INTMODE > 0)
#IF (ASCIINTS)
;
#IF (INTMODE > 0)
;
; IM1 ENTRY POINT
;
@ -232,10 +242,10 @@ ASCI_INTRCV1:
ADD A,8 ; BUMP TO RDR PORT
LD C,A ; PUT IN C, B IS STILL ZERO
IN A,(C) ; READ PORT
#IF (ASCIBOOT != 0)
#IF (ASCIBOOT != 0)
CP ASCIBOOT ; REBOOT REQUEST?
JP Z,SYS_RESCOLD ; IF SO, DO IT, NO RETURN
#ENDIF
#ENDIF
LD B,A ; SAVE BYTE READ
LD L,(IY+6) ; SET HL TO
LD H,(IY+7) ; ... START OF BUFFER STRUCT
@ -292,6 +302,8 @@ ASCI_INTRCV3:
ASCI_INTRCV4:
OR $FF ; NZ SET TO INDICATE INT HANDLED
RET ; AND RETURN
;
#ENDIF
;
#ENDIF
;
@ -309,7 +321,7 @@ ASCI_FNTBL:
.ECHO "*** INVALID ASCI FUNCTION TABLE ***\n"
#ENDIF
;
#IF (INTMODE == 0)
#IF ((!ASCIINTS) | (INTMODE == 0))
;
ASCI_IN:
CALL ASCI_IST ; CHECK FOR CHAR READY
@ -395,7 +407,7 @@ ASCI_OUT:
;
;
;
#IF (INTMODE == 0)
#IF ((!ASCIINTS) | (INTMODE == 0))
;
ASCI_IST:
CALL ASCI_ICHK ; ASCI INPUT CHECK
@ -522,7 +534,7 @@ ASCI_INITGO:
OUT (C),L ; WRITE CNTLB VALUE
INC C ; BUMP TO
INC C ; ... STAT REG, B IS STILL 0
#IF (INTMODE > 0)
#IF ((ASCIINTS) & (INTMODE > 0))
LD A,$08 ; SET RIE BIT ON
#ELSE
XOR A ; CLEAR RIE/TIE
@ -534,7 +546,7 @@ ASCI_INITGO:
LD A,$66 ; STATIC VALUE FOR ASEXT
OUT (C),A ; WRITE ASEXT REG
;
#IF (INTMODE > 0)
#IF ((ASCIINTS) & (INTMODE > 0))
;
; RESET THE RECEIVE BUFFER
LD E,(IY+6)
@ -609,6 +621,24 @@ ASCI_DETECT:
; DUE TO ENCODING BAUD IS ALWAYS DIVISIBLE BY 75
; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
;
; CNTLB= XXPXDSSS
; FAILSAVE = 00100000
;
; PS (PRESCALE): 0=/10, 1=/30
; DR (DIVIDE RATIO): 0=/16, 1=/64
; SS2 SS1 SS0
; --- --- ---
; 0 0 0 /1
; 0 0 1 /2
; 0 1 0 /4
; 0 1 1 /8
; 1 0 0 /16
; 1 0 1 /32
; 1 1 0 /64
;
; FAILSAFE: CLOCK / 30 / 16 / 1 = CLOCK / 480
; IF CLOCK=18432000, BAUD=38400
;
; X := CPU_HZ / 160 / 75 ==> SIMPLIFIED ==> X := CPU_KHZ / 12
; X := X / (BAUD / 75)
; IF X % 3 == 0, THEN (PS := 1, X := X / 3) ELSE PS=0
@ -769,7 +799,7 @@ ASCI_STR_ASCIB .DB "ASCI W/BRG$"
;
ASCI_DEV .DB 0 ; DEVICE NUM USED DURING INIT
;
#IF (INTMODE == 0)
#IF ((!ASCIINTS) | (INTMODE == 0))
;
ASCI0_RCVBUF .EQU 0
ASCI1_RCVBUF .EQU 0

5
Source/HBIOS/cfg_dyno.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@ -100,6 +100,7 @@ DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_ezz80.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

10
Source/HBIOS/cfg_master.asm
View File

@ -12,7 +12,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -30,7 +30,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
@ -60,6 +60,11 @@ N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
RPH_DEFACR .EQU $00 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR
@ -153,6 +158,7 @@ UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_mbc.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;

5
Source/HBIOS/cfg_mk4.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
@ -122,6 +122,7 @@ UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

5
Source/HBIOS/cfg_n8.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
;
@ -124,6 +124,7 @@ UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

5
Source/HBIOS/cfg_rcz180.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@ -125,6 +125,7 @@ UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

4
Source/HBIOS/cfg_rcz280.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_rcz80.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

249
Source/HBIOS/cfg_rph.asm
View File

@ -0,0 +1,249 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "RHYOPHYRE"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
RPH_DEFACR .EQU $20 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
RTCIO .EQU RPH_RTC ; RTC LATCH REGISTER ADR
;
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
;
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
;
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
;
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC]
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY
DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG]
DSKYPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF DSKY PPI
DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
;
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
;
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
;
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
;
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
;
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0BASE .EQU RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
;
CENENABLE .EQU FALSE ; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
;
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
SN7CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
SNMODE .EQU SNMODE_NONE ; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
;
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)

4
Source/HBIOS/cfg_sbc.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;

5
Source/HBIOS/cfg_scz180.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
;
@ -120,6 +120,7 @@ UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

2
Source/HBIOS/cfg_una.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "../UBIOS/ubios.inc"
;
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE

4
Source/HBIOS/cfg_zeta.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
;

4
Source/HBIOS/cfg_zeta2.asm
View File

@ -15,7 +15,7 @@
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

36
Source/HBIOS/dsrtc.asm
View File

@ -66,28 +66,28 @@
; RTC LATCH WRITE
; ---------------
;
; BIT SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126 MBC
; ----- ------- ------- ------- ------- ------- ------- ------- ------- --------------- -------
; D7 RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT,I2C_SDA RTC_OUT
; D6 RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK RTC_CLK
; D5 /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE /RTC_WE
; D4 RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE RTC_CE
; D3 NC CLKSEL /RTC_CE NC NC NC -- -- /SPI_CS2 CLKSEL
; D2 NC SPK RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1 SPK
; D1 -- -- RTC_WE SPI_CLK NC NC -- -- FS LED1
; D0 -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL LED0
; BIT SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126 MBC RPH
; ----- ------- ------- ------- ------- ------- ------- ------- ------- --------------- ------- -------
; D7 RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT,I2C_SDA RTC_OUT RTC_OUT
; D6 RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK RTC_CLK RTC_CLK
; D5 /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE /RTC_WE /RTC_WE
; D4 RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE RTC_CE RTC_CE
; D3 NC CLKSEL /RTC_CE NC NC NC -- -- /SPI_CS2 CLKSEL --
; D2 NC SPK RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1 SPK --
; D1 -- -- RTC_WE SPI_CLK NC NC -- -- FS LED1 --
; D0 -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL LED0 --
;
; RTC LATCH READ
; --------------
;
; D7 -- -- -- -- -- -- -- -- I2C_SDA --
; D6 CFG CFG -- SPI_DO CFG -- -- -- -- CFG
; D5 -- -- -- -- -- -- -- -- -- --
; D4 -- -- -- -- -- -- -- -- -- --
; D3 -- -- -- -- -- -- -- -- -- --
; D2 -- -- -- -- -- -- -- -- -- --
; D1 ---- -- -- -- -- -- -- -- -- CLKSEL
; D0 RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN -- -- RTC_IN RTC_IN
; D7 -- -- -- -- -- -- -- -- I2C_SDA -- --
; D6 CFG CFG -- SPI_DO CFG -- -- -- -- CFG --
; D5 -- -- -- -- -- -- -- -- -- -- --
; D4 -- -- -- -- -- -- -- -- -- -- --
; D3 -- -- -- -- -- -- -- -- -- -- --
; D2 -- -- -- -- -- -- -- -- -- -- --
; D1 ---- -- -- -- -- -- -- -- -- CLKSEL --
; D0 RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN -- -- RTC_IN RTC_IN RTC_IN
;
#IF (DSRTCMODE == DSRTCMODE_STD)
;

89
Source/HBIOS/hbios.asm
View File

@ -556,6 +556,28 @@ HBX_RAMX:
HBX_MMA .DB 0 ; TEMPORARY STORAGE FOR REG A
#ENDIF
;
#IF (MEMMGR == MM_RPH)
BIT 7,A ; TEST BIT 7 FOR RAM VS. ROM
JR Z,HBX_ROM ; IF NOT SET, SELECT ROM PAGE
;
HBX_RAM:
AND %00011111 ; AVOID WRAPPING BITS
RLCA ; SCALE SELECTOR TO
RLCA ; ... GO FROM Z180 4K PAGE SIZE
RLCA ; ... TO DESIRED 32K PAGE SIZE
OUT0 (Z180_BBR),A ; WRITE TO BANK BASE
LD A,RPH_DEFACR | 80H ; SELECT RAM BY SETTING BIT 7
OUT0 (RPH_ACR),A ; ... IN RPH ACR REGISTER
RET ; DONE
;
HBX_ROM:
OR RPH_DEFACR ; COMBINE WITH DEFAULT BITS
OUT0 (RPH_ACR),A ; BANK INDEX TO RPH ACR REGISTER
XOR A ; ZERO ACCUM
OUT0 (Z180_BBR),A ; ZERO BANK BASE
RET ; DONE
#ENDIF
;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; Copy Data - Possibly between banks. This resembles CP/M 3, but
; usage of the HL and DE registers is reversed.
@ -1101,6 +1123,11 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n
OUT0 (N8_ACR),A ; ... REGISTER IS INITIALIZED
#ENDIF
;
#IF (PLATFORM == PLT_RPH)
LD A,RPH_DEFACR ; ENSURE RPH ACR
OUT0 (RPH_ACR),A ; ... REGISTER IS INITIALIZED
#ENDIF
;
#IF (DIAGENABLE)
LD A,%00000001
OUT (DIAGPORT),A
@ -1238,7 +1265,7 @@ Z280_INITZ:
LD A,$F0
OUT0 (Z180_DCNTL),A
#IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
#IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8) | (MEMMGR == MM_RPH))
; Z180 MMU SETUP
LD A,$80
OUT0 (Z180_CBAR),A ; SETUP FOR 32K/32K BANK CONFIG
@ -1919,20 +1946,20 @@ HB_CPUSPD2:
;
LD HL,(HB_CPUOSC) ; INIT HL TO CPU OSC FREQ (KHZ)
;
#IF (Z180_CLKDIV == 0)
; ADJUST HL TO REFLECT HALF SPEED OPERATION
SRL H ; ADJUST HL ASSUMING
RR L ; HALF SPEED OPERATION
#ENDIF
;
#IF (Z180_CLKDIV == 1)
#IF (Z180_CLKDIV >= 1)
LD A,(HB_CPUTYPE) ; GET CPU TYPE
CP 2 ; Z8S180 REV K OR BETTER?
JR C,HB_CPU3 ; IF NOT, NOT POSSIBLE!
; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
LD A,$80
OUT0 (Z180_CCR),A
; HL ALREADY REFLECTS FULL SPEED OPERATION
; ADJUST HL TO REFLECT FULL SPEED OPERATION
SLA L
RL H
#ENDIF
;
#IF (Z180_CLKDIV >= 2)
@ -2419,6 +2446,9 @@ HB_Z280BUS1:
#ENDIF
#IF (MEMMGR == MM_MBC)
.TEXT "MBC$"
#ENDIF
#IF (MEMMGR == MM_RPH)
.TEXT "RPH$"
#ENDIF
CALL PRTSTRD
.TEXT " MMU$"
@ -4072,19 +4102,33 @@ SYS_GETCPUSPD1:
#ENDIF
;
#IF (CPUFAM == CPU_Z180)
IN0 A,(Z180_CMR) ; GET CLOCK MULTIPLIER
RLCA ; ROTATE BIT TO BIT 0
AND %00000001 ; ISOLATE IT
LD H,A ; SAVE IN H
LD HL,0 ; INIT CPU SPEED TO HALF
LD A,(HB_CPUTYPE) ; LOAD CPUTYPE
CP 2 ; S-CLASS OR ABOVE?
JR C,SYS_GETCPUSPD1 ; IF NOT, NO CCR/CMR
;
; GET CCR BIT
IN0 A,(Z180_CCR) ; GET CLOCK CONTROL
RLCA ; ROTATE BIT TO BIT 0
AND %00000001 ; ISOLATE IT
LD L,A ; SAVE IN L
;
LD A,(HB_CPUTYPE) ; LOAD CPUTYPE
CP 3 ; REV. N?
JR C,SYS_GETCPUSPD1 ; IF NOT, NO CMR
;
; GET CMR BIT
IN0 A,(Z180_CMR) ; GET CLOCK MULTIPLIER
RLCA ; ROTATE BIT TO BIT 0
AND %00000001 ; ISOLATE IT
LD H,A ; SAVE IN H
;
SYS_GETCPUSPD1:
; CALC FINAL MULTIPLIER TO L
XOR A ; CLEAR ACCUM
ADD A,H ; ADD IN CMR BIT
ADD A,L ; ADD IN CCR BIT
LD L,A ; SAVE RESULT IN L
;
; DCNTL = MMII????
IN0 A,(Z180_DCNTL) ; GET WAIT STATES
RLCA ; ROTATE MEM WS BITS
@ -4348,6 +4392,29 @@ SYS_SETCPUSPD3:
#ENDIF
;
#IF (CPUFAM == CPU_Z180)
; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE
LD A,L ; GET SPEED REQUESTED
CP $FF ; NO CHANGE?
JR Z,SYS_SETCPUSPD0A ; SKIP CHECK
LD A,(HB_CPUTYPE) ; 1=ORIG, 2=REVK, 3=REVN
INC L ; 1=HALF,2=FULL,3=DOUBLE
CP L ; TOO HIGH FOR CPU TYPE?
JP C,SYS_SETCPUSPD_ERR ; CPU CAN'T DO SPD MULT
DEC L ; RESTORE ORIG REQUEST
SYS_SETCPUSPD0A:
LD A,D ; MEM WS
CP $FF ; NO CHANGE?
JR Z,SYS_SETCPUSPD0B ; SKIP CHECK
CP 4 ; TOO HIGH?
JP NC,SYS_SETCPUSPD_ERR ; >3 IS TOO HIGH
SYS_SETCPUSPD0B:
LD A,D ; I/O WS
CP $FF ; NO CHANGE?
JR Z,SYS_SETCPUSPD0C ; SKIP CHECK
CP 4 ; TOO HIGH?
JP NC,SYS_SETCPUSPD_ERR ; >3 IS TOO HIGH
SYS_SETCPUSPD0C:
;
PUSH DE ; SAVE WAIT STATES FOR NOW
; BEFORE IMPLEMENTING THE NEW CPU SPEED, WE SWITCH THE
; WAIT STATES TO MAXIMUM BECAUSE WE MAY BE IMPLEMENTING
@ -4374,11 +4441,11 @@ SYS_SETCPUSPD1:
LD C,%10000000 ; SET CCR BIT
SYS_SETCPUSPD2:
;
; IMPLEMENT THE NEW CPU SPEED
IN0 A,(Z180_CMR)
AND ~%10000000
OR B
OUT0 (Z180_CMR),A
;
IN0 A,(Z180_CCR)
AND ~%10000000
OR C

1
Source/HBIOS/hbios.inc
View File

@ -136,6 +136,7 @@ PLT_SCZ180 .EQU 10 ; SCZ180
PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280
PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER
PLT_RPH .EQU 14 ; RHYOPHYRE GRAPHICS COMPUTER
;
; HBIOS GLOBAL ERROR RETURN VALUES
;

3
Source/HBIOS/std.asm
View File

@ -15,6 +15,7 @@
; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard
; 12. RCZ280 Z280 CPU on RC2014 or ZZ80MB
; 13. MBC Andrew Lynch's Multi Board Computer
; 14. RPH Andrew Lynch's RHYOPHYRE Graphics Computer
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
@ -70,6 +71,7 @@ MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER
MM_ZRC .EQU 6 ; ZRC BANK SWITCHING
MM_MBC .EQU 7 ; MBC MEMORY MANAGER
MM_RPH .EQU 8 ; Z180 WITH RPH EXTENSIONS
;
; BOOT STYLE
;
@ -170,6 +172,7 @@ PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
PPIDEMODE_RPH .EQU 7 ; RHYOPHYRE (RPH)
;
; SD MODE SELECTIONS
;

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.165"
#DEFINE BIOSVER "3.1.1-pre.168"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.165"
db "3.1.1-pre.168"
endm

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