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This check-in includes some refactoring of the configuration files.
This commit is contained in:
Wayne Warthen
2023-02-12 19:26:23 -08:00
parent 3034fb6b5b
commit c157d52c1d
42 changed files with 329 additions and 527 deletions
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69
Source/Doc/UserGuide.md
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@@ -182,15 +182,13 @@ below, **carefully** pick the appropriate ROM image for your hardware.
| [RetroBrew N8 Z180 SBC]^1^ (date code >= 2312) | ECB | N8_std.rom | 38400 |
| [RetroBrew Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, DUART | RCBus | RCZ80_duart.rom | 115200 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, MT011 | RCBus | RCZ80_mt.rom | 115200 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, KIO | RCBus | RCZ80_kio.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 |
| [Easy Z80 SBC]^2^ | RCBus | EZZ80_std.rom | 115200 |
| [Tiny Z80 EIPC SBC]^2^ | RCBus | EZZ80_tz80.rom | 115200 |
| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy.rom | 115200 |
| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny.rom | 115200 |
| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz.rom | 115200 |
| [SC126 Z180 SBC]^5^ | BP80 | SCZ180_126.rom | 115200 |
| [SC130 Z180 SBC]^5^ | RCBus | SCZ180_130.rom | 115200 |
@@ -3276,17 +3274,18 @@ to the user to ensure that no conflicting hardware is in use.
|-------------------|---------------|
| ROM Image File | RCZ80_std.rom |
| Console Baud Rate | 115200 |
| Interrupt Mode | 1 |
- CPU speed is detected at startup if DS1302 RTC is active
- Otherwise 7.3728 MHz assumed
- Requires 512K RAM/ROM module
- Requires 512K RAM/ROM Module
- Hardware auto-detected:
- DS1302 RTC
- RP5C01 RTC
- ACIA Serial Interface Module
- SIO Serial Interface Module
- EP Dual UART Serial Interface Module
- WDC Floppy Disk Controller w/ 3.5" HD Drives
- AY-3-8910/YM2149 Sound Module
- IDE Hard Disk Interface Module
- PPIDE Hard Disk Interface Module
- Serial baud rate is usually determined by hardware for ACIA and
@@ -3296,29 +3295,14 @@ to the user to ensure that no conflicting hardware is in use.
|-------------------|---------------|
| ROM Image File | RCZ80_kio.rom |
| Console Baud Rate | 38400 |
| Interrupt Mode | 2 |
- Equivalent to RCZ80_std w/ support for KIO Module:
- Equivalent to RCZ80_std w/ following modifications:
- KIO-SIO Serial Interface uses KIO port standards
- KIO-CTC generates system timer
- SIO Serial baud rate managed by KIO-CTC
| | |
|-------------------|-----------------|
| ROM Image File | RCZ80_duart.rom |
| Console Baud Rate | 115200 |
- Equivalent to RCZ80_std w/ support for DUART Module:
- DUART serial interfaces supported
| | |
|-------------------|---------------|
| ROM Image File | RCZ80_mt.rom |
| Console Baud Rate | 115200 |
- Equivalent to RCZ80_std w/ support for MT011 Module:
- MT011 SD Card interface supported
- MT011 provides a WizNet network interface which can be utilized
by the supplied RomwWBW CP/NET client software.
- Use of Interrupt Mode 2 requires proper IEI/IEO configuration
for all peripherals generating interrupts
`\clearpage`{=latex}
@@ -3329,34 +3313,35 @@ to the user to ensure that no conflicting hardware is in use.
| ROM Image Files | RCZ180_ext.rom |
| | RCZ180_nat.rom |
| Console Baud Rate | 115200 |
| Interrupt Mode | 2 |
- CPU speed is detected at startup if DS1302 RTC is active
- Otherwise 18.432 MHz assumed
- System timer is generated by Z180 CPU
- Hardware auto-detected:
- DS1302 RTC
- Z180 ASCI Serial Ports
- ACIA Serial Interface Module
- SIO Serial Interface Module
- EP Dual UART Serial Interface Module
- WDC Floppy Disk Controller w/ 3.5" HD Drives
- IDE Hard Disk Interface Module
- PPIDE Hard Disk Interface Module
- Serial baud rate is usually determined by hardware for ACIA and
SIO interfaces
- Requires 512K RAM/ROM module
- Specific ROM image determined by memory module used:
- RCZ180_ext - Bank switching on memory module (external of CPU)
- RCZ180_nat - Linear memory module (native CPU bank switching)
- Use of Interrupt Mode 2 requires proper IEI/IEO configuration
for all peripherals generating interrupts
`\clearpage`{=latex}
### RCBus Z280 CPU Module
| | |
|-------------------|----------------|
| ROM Image Files | RCZ280_ext.rom |
| | RCZ280_nat.rom |
| Console Baud Rate | 115200 |
| | |
|-------------------|-------------------|
| ROM Image Files | RCZ280_ext.rom |
| | RCZ280_nat.rom |
| Console Baud Rate | 115200 |
| Interrupt Mode | 1 (ext) / 3 (nat) |
- CPU speed is assumed to be 12 MHz (24 MHz oscillator)
- Hardware auto-detected:
@@ -3377,14 +3362,13 @@ to the user to ensure that no conflicting hardware is in use.
`\clearpage`{=latex}
`\clearpage`{=latex}
### Easy Z80 SBC
| | |
|-------------------|---------------|
| ROM Image File | EZZ80_std.rom |
| Console Baud Rate | 115200 |
| | |
|-------------------|----------------|
| ROM Image File | RCZ80_easy.rom |
| Console Baud Rate | 115200 |
| Interrupt Mode | 2 |
- CPU speed is detected at startup if DS1302 RTC is active
- Otherwise 10.000 MHz assumed
@@ -3400,12 +3384,13 @@ to the user to ensure that no conflicting hardware is in use.
`\clearpage`{=latex}
### Tiny Z80 EIPC SBC
### Tiny Z80 SBC
| | |
|-------------------|----------------|
| ROM Image File | EZZ80_tz80.rom |
| ROM Image File | RCZ80_tiny.rom |
| Console Baud Rate | 115200 |
| Interrupt Mode | 2 |
- CPU speed is detected at startup if DS1302 RTC is active
- Otherwise 16.000 MHz assumed