From c0ca96cb9672e11570eddcd482aac51943ace91d Mon Sep 17 00:00:00 2001 From: Phillip Stevens Date: Fri, 15 Nov 2019 11:40:50 +1100 Subject: [PATCH 1/5] hbios - z180 CMR/CCR config --- Source/HBIOS/hbios.asm | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 3169899d..462ebd44 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1279,19 +1279,23 @@ HB_CPU1: ; REFLECT SPEED CHANGE LD C,CPUOSC / 1000000 LD DE,CPUOSC / 1000 -#ENDIF - +#ELSE +; #IF (Z180_CLKDIV >= 2) + LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 3 ; Z8S180 REV N OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! ; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED LD A,$80 - OUT0 (Z180_CMR),A + OUT0 (Z180_CMR),A ; MUST SET CMR BEFORE CCR + OUT0 (Z180_CCR),A ; REFLECT SPEED CHANGE LD C,(CPUOSC * 2) / 1000000 LD DE,(CPUOSC * 2) / 1000 #ENDIF ; +#ENDIF +; HB_CPU2: ; SAVE CPU SPEED IN CONFIG BLOCK LD A,C From fc760e90e07abd20e41b684fc6e7f75742c8c7e6 Mon Sep 17 00:00:00 2001 From: Phillip Stevens Date: Fri, 15 Nov 2019 11:46:20 +1100 Subject: [PATCH 2/5] hbios - z180 CMR/CCR order --- Source/HBIOS/hbios.asm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 462ebd44..a4b72085 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -776,8 +776,8 @@ HB_START: ; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2) XOR A - OUT0 (Z180_CCR),A OUT0 (Z180_CMR),A + OUT0 (Z180_CCR),A ; SET DEFAULT WAIT STATES LD A,$F0 From 326ee0ae67a10c6bfa00ca2f0cadf5e386291503 Mon Sep 17 00:00:00 2001 From: Phillip Stevens Date: Fri, 15 Nov 2019 11:56:24 +1100 Subject: [PATCH 3/5] hbios - z180 CMR/CCR testing --- Source/HBIOS/hbios.asm | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index a4b72085..4ca4b0cf 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1269,7 +1269,7 @@ HB_CPU1: LD C,(CPUOSC / 2) / 1000000 LD DE,(CPUOSC / 2) / 1000 ; -#IF (Z180_CLKDIV >= 1) +#IF (Z180_CLKDIV = 1) LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 2 ; Z8S180 REV K OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! @@ -1281,7 +1281,7 @@ HB_CPU1: LD DE,CPUOSC / 1000 #ELSE ; -#IF (Z180_CLKDIV >= 2) +#IF (Z180_CLKDIV = 2) LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 3 ; Z8S180 REV N OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! From 084df830efedc723f98579692dc55bb04d13f9a6 Mon Sep 17 00:00:00 2001 From: Phillip Stevens Date: Fri, 15 Nov 2019 19:14:43 +1100 Subject: [PATCH 4/5] hbios - z180 TASM equality check --- Source/HBIOS/hbios.asm | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 4ca4b0cf..f7b22071 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1269,7 +1269,7 @@ HB_CPU1: LD C,(CPUOSC / 2) / 1000000 LD DE,(CPUOSC / 2) / 1000 ; -#IF (Z180_CLKDIV = 1) +#IF (Z180_CLKDIV == 1) LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 2 ; Z8S180 REV K OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! @@ -1281,7 +1281,7 @@ HB_CPU1: LD DE,CPUOSC / 1000 #ELSE ; -#IF (Z180_CLKDIV = 2) +#IF (Z180_CLKDIV == 2) LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 3 ; Z8S180 REV N OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! From 659f60c23b56ea15b37d0a2a7df96954de33349a Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 15 Nov 2019 16:29:27 -0800 Subject: [PATCH 5/5] Cleanup Timer & Clock Multiplier Code --- Doc/ChangeLog.txt | 2 +- ReadMe.txt | 2 +- Source/CBIOS/ver.inc | 2 +- Source/HBIOS/hbios.asm | 138 ++++++++++++++++++----------------------- Source/HBIOS/ver.inc | 2 +- 5 files changed, 65 insertions(+), 81 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index c747390b..c1dd800e 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -28,7 +28,7 @@ Version 2.9.2 - WBW: Updated FAT to add MD and FORMAT commands - WBW: Add CP/M 3 (experimental) - M?T: Support Shift register SPI WIZNET for RC2014 -- P?S: Added seconds register in HBIOS +- PLS: Added seconds register in HBIOS Version 2.9.1 ------------- diff --git a/ReadMe.txt b/ReadMe.txt index abe6ea25..a56e3998 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.2-pre.20, 2019-11-11 +Version 2.9.2-pre.21, 2019-11-15 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index cc7a9eb0..53f408fa 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.20" +#DEFINE BIOSVER "2.9.2-pre.21" diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index f7b22071..b990716a 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -981,22 +981,69 @@ HB_CPU1: LD A,L LD (HB_CPUTYPE),A ; +#IF (DSRTCENABLE) + CALL DSRTC_PREINIT +#ENDIF +; +#IF (CPUFAM == CPU_Z180) +; + ; AT BOOT, Z180 PHI IS OSC / 2 + LD C,(CPUOSC / 2) / 1000000 + LD DE,(CPUOSC / 2) / 1000 +; +#IF (Z180_CLKDIV >= 1) + LD A,(HB_CPUTYPE) ; GET CPU TYPE + CP 2 ; Z8S180 REV K OR BETTER? + JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! + ; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED + LD A,$80 + OUT0 (Z180_CCR),A + ; REFLECT SPEED CHANGE + LD C,CPUOSC / 1000000 + LD DE,CPUOSC / 1000 +#ENDIF + +#IF (Z180_CLKDIV >= 2) + LD A,(HB_CPUTYPE) ; GET CPU TYPE + CP 3 ; Z8S180 REV N OR BETTER? + JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! + ; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED + LD A,$80 + OUT0 (Z180_CMR),A + ; REFLECT SPEED CHANGE + LD C,(CPUOSC * 2) / 1000000 + LD DE,(CPUOSC * 2) / 1000 +#ENDIF +; +HB_CPU2: + ; SAVE CPU SPEED IN CONFIG BLOCK + LD A,C + LD (CB_CPUMHZ),A + LD (CB_CPUKHZ),DE +; +#ENDIF +; + DIAG(%00011111) +; +; PERFORM DYNAMIC CPU SPEED DERIVATION +; + CALL HB_CPUSPD ; CPU SPEED DETECTION +; + CALL DELAY_INIT ; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS +; +#IF (CPUFAM == CPU_Z180) +; + ; SET FINAL DESIRED WAIT STATES + LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4) + OUT0 (Z180_DCNTL),A +; +#ENDIF +; #IF (KIOENABLE) LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN OUT (KIOBASE+$0E),A ; DO IT - ;CALL DLY64 ; WAIT A BIT FOR RESET TO COMPLETE #ENDIF ; -; SETUP INTERRUPT VECTORS, AS APPROPRIATE -; -;#IF (INTMODE == 1) -; ; OVERLAY $0038 WITH JP INT_IM1 -; LD A,$C3 ; JP INSTRUCTION -; LD ($0038),A ; INSTALL IT -; LD HL,INT_IM1 ; DESTINATION ADDRESS -; LD ($0039),HL ; INSTALL IT -;#ENDIF -; #IF (INTMODE == 2) ; SETUP Z80 IVT AND INT MODE 2 LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS @@ -1010,7 +1057,7 @@ HB_CPU1: IM 2 ; SWITCH TO INT MODE 2 #ENDIF - +; #IF (PLATFORM == PLT_SBC) ; #IF (HTIMENABLE) ; SIMH TIMER @@ -1142,7 +1189,6 @@ HB_CPU1: ; #ENDIF ; -; #IF (PLATFORM == PLT_RCZ80) ; ; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO @@ -1245,11 +1291,10 @@ HB_CPU1: LD (IVT(INT_TIM0)),HL ; Z180 TIMER 0 ; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0 -; LD HL,CPUOSC/TICKSPERSEC/20-1 ; 50HZ = 18432000 / 50 / 20 - LD HL,(CPUKHZ) ; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ - DEC HL ; RELOAD OCCURS *AFTER* ZERO + LD HL,(CB_CPUKHZ) ; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ OUT0 (Z180_TMDR0L),L ; INITIALIZE TIMER 0 DATA REGISTER OUT0 (Z180_TMDR0H),H + DEC HL ; RELOAD OCCURS *AFTER* ZERO OUT0 (Z180_RLDR0L),L ; INITIALIZE TIMER 0 RELOAD REGISTER OUT0 (Z180_RLDR0H),H LD A,%00010001 ; ENABLE TIMER0 INT AND DOWN COUNTING @@ -1259,67 +1304,6 @@ HB_CPU1: ; #ENDIF ; -#IF (DSRTCENABLE) - CALL DSRTC_PREINIT -#ENDIF -; -#IF (CPUFAM == CPU_Z180) -; - ; AT BOOT, Z180 PHI IS OSC / 2 - LD C,(CPUOSC / 2) / 1000000 - LD DE,(CPUOSC / 2) / 1000 -; -#IF (Z180_CLKDIV == 1) - LD A,(HB_CPUTYPE) ; GET CPU TYPE - CP 2 ; Z8S180 REV K OR BETTER? - JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! - ; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED - LD A,$80 - OUT0 (Z180_CCR),A - ; REFLECT SPEED CHANGE - LD C,CPUOSC / 1000000 - LD DE,CPUOSC / 1000 -#ELSE -; -#IF (Z180_CLKDIV == 2) - LD A,(HB_CPUTYPE) ; GET CPU TYPE - CP 3 ; Z8S180 REV N OR BETTER? - JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! - ; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED - LD A,$80 - OUT0 (Z180_CMR),A ; MUST SET CMR BEFORE CCR - OUT0 (Z180_CCR),A - ; REFLECT SPEED CHANGE - LD C,(CPUOSC * 2) / 1000000 - LD DE,(CPUOSC * 2) / 1000 -#ENDIF -; -#ENDIF -; -HB_CPU2: - ; SAVE CPU SPEED IN CONFIG BLOCK - LD A,C - LD (CB_CPUMHZ),A - LD (CB_CPUKHZ),DE -; -#ENDIF -; -; PERFORM DYNAMIC CPU SPEED DERIVATION -; - CALL HB_CPUSPD ; CPU SPEED DETECTION -; -#IF (CPUFAM == CPU_Z180) -; - ; SET DESIRED WAIT STATES - LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4) - OUT0 (Z180_DCNTL),A -; -#ENDIF -; - CALL DELAY_INIT ; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS -; - DIAG(%00011111) -; ; INITIALIZE HEAP STORAGE ; ; INITIALIZE POINTERS diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index cc7a9eb0..53f408fa 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.20" +#DEFINE BIOSVER "2.9.2-pre.21"