mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Reintegrate wbw -> trunk
This commit is contained in:
@@ -33,6 +33,7 @@ BIOSSIZE .EQU 0100H ; DEPRECATED!!!
|
||||
PLT_N8VEM .EQU 1 ; N8VEM ECB Z80 SBC
|
||||
PLT_ZETA .EQU 2 ; ZETA Z80 SBC
|
||||
PLT_N8 .EQU 3 ; N8 (HOME COMPUTER) Z180 SBC
|
||||
PLT_S2I .EQU 4 ; SCSI2IDE
|
||||
;
|
||||
; BOOT STYLE
|
||||
;
|
||||
@@ -199,14 +200,23 @@ RTC .EQU 70H ; ADDRESS OF RTC LATCH AND INPUT PORT
|
||||
;
|
||||
; PPI 82C55 I/O IS DECODED TO PORT 60-67
|
||||
;
|
||||
PPIA .EQU 60H ; PORT A
|
||||
PPIB .EQU 61H ; PORT B
|
||||
PPIC .EQU 62H ; PORT C
|
||||
PPIX .EQU 63H ; PPI CONTROL PORT
|
||||
#IF (PLATFORM == PLT_S2I)
|
||||
PPIBASE .EQU 80H
|
||||
#ELSE
|
||||
PPIBASE .EQU 60H
|
||||
#ENDIF
|
||||
PPIA .EQU PPIBASE + 0 ; PORT A
|
||||
PPIB .EQU PPIBASE + 1 ; PORT B
|
||||
PPIC .EQU PPIBASE + 2 ; PORT C
|
||||
PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
|
||||
;
|
||||
; 16C550 SERIAL LINE UART
|
||||
;
|
||||
#IF (PLATFORM == PLT_S2I)
|
||||
SIO_BASE .EQU 90H
|
||||
#ELSE
|
||||
SIO_BASE .EQU 68H
|
||||
#ENDIF
|
||||
SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
|
||||
SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
|
||||
SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG
|
||||
@@ -488,6 +498,9 @@ CCPSIZ: .EQU 00800H
|
||||
#IF (PLATFORM == PLT_N8)
|
||||
#DEFINE PLATFORM_NAME "N8 Z180 SBC"
|
||||
#ENDIF
|
||||
#IF (PLATFORM == PLT_S2I)
|
||||
#DEFINE PLATFORM_NAME "SCSI2IDE"
|
||||
#ENDIF
|
||||
;
|
||||
#IF (DSKYENABLE)
|
||||
#DEFINE DSKYLBL ", DSKY"
|
||||
|
||||
Reference in New Issue
Block a user