Merge pull request #9 from wwarthen/master

Resync
7 years ago · c969e46519
11 changed files with 16 additions and 17 deletions
--- a/ReadMe.txt
+++ b/ReadMe.txt
@ -7,7 +7,7 @@
 ***********************************************************************

 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre.5, 2019-08-15
+Version 2.9.2-pre.6, 2019-08-18
 https://www.retrobrewcomputers.org/

 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
--- a/Source/Apps/XM/xmhb.180
+++ b/Source/Apps/XM/xmhb.180
@ -128,10 +128,10 @@ HINIT:
 	CP	000H		; UART?
 	JP	Z,U_INIT	; If so, do UART init
 	CP	010H		; ASCI?
-	JP	HINIT1		; If so, handle it below
+	JP	Z,HINIT1	; If so, handle it below
 	CP	080H		; USB-FIFO?
-	JP	UF_INIT		; If so, do USB-FIFO init
-	JR	HWERR		; Unknown hardware error
+	JP	Z,UF_INIT	; If so, do USB-FIFO init
+	JP	H_INIT		; Otherwise, use HBIOS I/O
 ;
 HINIT1:
 	; Use platform to select ASCI driver
--- a/Source/CBIOS/ver.inc
+++ b/Source/CBIOS/ver.inc
@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.5"
+#DEFINE BIOSVER	"2.9.2-pre.6"
--- a/Source/HBIOS/Config/RCZ180_ext.asm
+++ b/Source/HBIOS/Config/RCZ180_ext.asm
@ -25,7 +25,6 @@
 #include "cfg_rcz180.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
-DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
--- a/Source/HBIOS/Config/RCZ180_nat.asm
+++ b/Source/HBIOS/Config/RCZ180_nat.asm
@ -24,8 +24,7 @@
 ;
 #include "cfg_rcz180.asm"
 ;
-CPUOSC		.SET	18432000	; CPU FAMILY: CPU_[Z80|Z180]
-DEFSERCFG	.SET	SER_38400_8N1	; HARDWARE BIOS: BIOS_[WBW|UNA]
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 ;
 MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
--- a/Source/HBIOS/Config/SC126_std.asm
+++ b/Source/HBIOS/Config/SC126_std.asm
@ -25,7 +25,6 @@
 #include "cfg_sc126.asm"
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
-DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
--- a/Source/HBIOS/Config/ZETA2_std.asm
+++ b/Source/HBIOS/Config/ZETA2_std.asm
@ -24,6 +24,8 @@
 ;
 #include "cfg_zeta2.asm"
 ;
+DEFSERCFG	.SET	DEFSERCFG | SER_RTS
+;
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@ -23,7 +23,7 @@ BOOT_DEFAULT	.EQU	'Z'		; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
 ;
 CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
-DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
@ -74,18 +74,18 @@ SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	DEFSERCFG	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	SER_115200_8N1	; AIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	DEFSERCFG	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	SER_115200_8N1	; AIO 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@ -23,7 +23,7 @@ BOOT_DEFAULT	.EQU	'Z'		; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
 ;
 CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
-DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@ -251,7 +251,7 @@ UART_INITDEV1:
 	JR	Z,UART_INITDEV2		; USE EFR REGISTER
 	CP	UART_16850		; 16850?
 	JR	Z,UART_INITDEV2		; USE EFR REGISTER
-	JR	UART_INITDEV4		; NO EFT, SKIP AHEAD
+	JR	UART_INITDEV4		; NO EFR, SKIP AHEAD
 ;
 UART_INITDEV2:
 	; WE HAVE AN EFR CAPABLE CHIP, SET EFR REGISTER
--- a/Source/HBIOS/ver.inc
+++ b/Source/HBIOS/ver.inc
@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.5"
+#DEFINE BIOSVER	"2.9.2-pre.6"