mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Merge pull request #655 from dinoboards/dean-dev-2026-01-24-vgmplay-cpu-benchmarking
vgmplay: added new timing type - measured fdelay based on hbios timer
This commit is contained in:
@@ -41,6 +41,28 @@ plt_type .equ sbcecb ; Select build configuration
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debug .equ 0 ; Display port, register, config info
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;
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;------------------------------------------------------------------------------
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; Configure timing loop
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;------------------------------------------------------------------------------
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;
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cpu_loop: .equ 0
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ctc_poll: .equ 1
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ctc_int: .equ 2 ; not implemented
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hbios_tmr: .equ 3 ; use hbios 50hz or 60hz timer to calculate a fdelay value (plt_romwbw must be set)
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;
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delay_type: .equ hbios_tmr ; cpu timed loop or utilize ctc
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delay_wait .equ 0 ; funny wait mode for ctc
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;
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D60 .equ 735 ; 735x60=44100 Frame delay values for ntsc
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D50 .equ 882 ; 882x50=44100 Frame delay values for pal
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#IF (delay_type==hbios_tmr)
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#IF (plt_romwbw!=1)
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## Assembly configuration Error
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## Must have plt_romwbw set, for delay_type==hbios_tmr
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#ENDIF
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#ENDIF
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;
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;------------------------------------------------------------------------------
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; Platform specific definitions. If building for ROMWBW, these may be overridden
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;------------------------------------------------------------------------------
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;
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@@ -183,20 +205,6 @@ YMSEL .equ VGMBASE+00H ; Primary YM2162 11000000 a1=0 a0=0
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#ENDIF
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;
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;------------------------------------------------------------------------------
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; Configure timing loop
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;------------------------------------------------------------------------------
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;
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cpu_loop: .equ 0
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ctc_poll: .equ 1
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ctc_int: .equ 2 ; not implemented
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;
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delay_type: .equ cpu_loop ; cpu timed loop or utilize ctc
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delay_wait .equ 0 ; funny wait mode for ctc
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;
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D60 .equ 735 ; 735x60=44100 Frame delay values for ntsc
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D50 .equ 882 ; 882x50=44100 Frame delay values for pal
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;
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;------------------------------------------------------------------------------
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; CTC Defaults
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;------------------------------------------------------------------------------
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;
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@@ -308,7 +316,11 @@ LF .equ 0AH ; line feed
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;
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CALL vgmsetup ; Device setup
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call welcome ; Welcome message and build debug info
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#IF (delay_type==hbios_tmr)
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call bcpu
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#ENDIF
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call vgmreadr ; read in the vgm file
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;
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;------------------------------------------------------------------------------
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; Play loop
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@@ -326,7 +338,7 @@ MAINLOOP CALL PLAY ; Play one frame
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OR A
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JR NZ,EXIT
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NO_CHK:
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#IF (delay_type==cpu_loop)
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#IF ((delay_type==cpu_loop) | (delay_type==hbios_tmr))
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vdelay: .equ $+1
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ld hl,vdelay
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fdelay: .equ $+1
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@@ -361,7 +373,7 @@ lp3: in a,(ctcch3) ; wait for counter to reach zero
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;
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#IF (delay_type==ctc_int)
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#ENDIF
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;
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JP MAINLOOP
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;
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;------------------------------------------------------------------------------
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@@ -431,7 +443,7 @@ HASEXT: LD C,OPENF ; Open File
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LD (FCBCR), A
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LD DE, VGMDATA
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LD (VGMPOS), DE
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RLOOP
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RLOOP
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; LD A,(TOPM) ; CBIOS start
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; SUB 10h ; Less BDOS = Top Memory Page
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LD A,$D6 ; Hardcoded top of memory
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@@ -1285,6 +1297,7 @@ MSG_TRACK .DB "Playing: ",0
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MSG_CPU .DB "[cpu]",0
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MSG_CTCPOLL .DB "[ctc polled]",0
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MSG_CTCINT .DB "[ctc interrupts]",0
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MSG_HBIOSTMR .DB "[hbios timer]",0
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MSG_ROMWBW .DB " [romwbw] ",0
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@@ -1312,7 +1325,7 @@ VGM_DEV .DB %00000000 ; IX+0 Flags for devices
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.DB %00000000 ; IX+1 Unimplemented device flags & future devices
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;
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OLDSTACK .DW 0 ; original stack pointer
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.FILL 40H ; space for stack
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.FILL 80H ; space for stack
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STACK .DW 0 ; top of stack
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;------------------------------------------------------------------------------
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@@ -1364,7 +1377,7 @@ welcome: LD DE,MSG_WELC ; Welcome Message
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CALL PRTSTR
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#ENDIF
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;
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LD A,delay_type ; display build type
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LD A,delay_type ; display delay type
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LD DE,MSG_CPU
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CALL PRTIDXDEA
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;
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@@ -1374,7 +1387,7 @@ welcome: LD DE,MSG_WELC ; Welcome Message
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call CRLF
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;
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#IF (debug)
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#IF (delay_type==cpu_loop)
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#IF ((delay_type==cpu_loop) | (delay_type==hbios_tmr))
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ld a,'f' ; Display frame rate delay
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call PRTCHR
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call PRTDOT
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@@ -1407,6 +1420,146 @@ welcome: LD DE,MSG_WELC ; Welcome Message
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#ENDIF
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CALL CRLF
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ret
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#IF (delay_type==hbios_tmr)
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bcpu:
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CALL hbios_tmr_enabled
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JP z, setfdelay
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LD DE, MSG_BENCHMARK
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CALL PRTSTR
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; get current timer tick value
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LD BC, $F8D0 ; GET TIMER TICKS
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RST 08 ; FROM HBIOS
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; hl is current timer tick value
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; c is freq
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LD A, L
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PUSH AF
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; sync to next timer tick
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; or timeout if there is no timer
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bc1:
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LD BC, $F8D0 ; GET TIMER TICKS
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RST 08 ; FROM HBIOS
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POP AF
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PUSH AF
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CP L
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JR Z, bc1
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POP AF
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LD H, L
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PUSH HL ; save current tick value
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LD B, 0
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LD HL, 2000
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bc2:
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DJNZ $
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DEC HL
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LD A, H
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OR L
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JR NZ, bc2
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LD BC, $F8D0 ; GET TIMER TICKS
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RST 08 ; FROM HBIOS
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LD A, L
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POP HL
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; h is starting timer tick
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; a is current timer tick
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; calculate a-l
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SUB L
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#IF (debug)
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CALL CRLF
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CALL PRTDOT
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CALL PRTDECB
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CALL PRTDOT
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#ENDIF
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; c is TICKFREQ
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; conversion rates are 50Hz -> 580, 60Hz -> 697
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LD HL, 580
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PUSH AF
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LD A, C
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CP 50
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JR Z, bc3
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LD HL, 697
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bc3:
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POP AF
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LD C, A
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CALL divide_16_by_8
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LD A, L
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#IF (debug)
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CALL PRTDECB
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#ENDIF
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CALL CRLF
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LD (fdelay), A
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RET
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; determine if hbios's timer is installed
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; returns:
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; A == 0 & Z if no timer
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; A != 0 & NZ if timer
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hbios_tmr_enabled:
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LD BC, $F8D0 ; GET TIMER TICKS
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RST 08 ; FROM HBIOS
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PUSH HL ; save current ticks
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; loop for a bit
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LD B, 0
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LD HL, 500
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tme1:
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DJNZ $
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DEC HL
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LD A, H
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OR L
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JR NZ, tme1
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LD BC, $F8D0 ; GET TIMER TICKS
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RST 08 ; FROM HBIOS
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LD A, L
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POP HL
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; if a == l then probably no timer
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SUB L
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RET
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; c = divisor
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; hl = dividend
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; a <- remainder
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; c <- divisor unchanged
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; hl <- quotient
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divide_16_by_8:
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XOR A
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LD B, 16
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div_loop:
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ADD HL, HL
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RLA
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JR C, div_overflow
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CP C
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JR C, div_zero
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div_overflow:
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INC L
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SUB C
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div_zero:
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DJNZ div_loop
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RET
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MSG_BENCHMARK:
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.DB "Benchmarking CPU ...", 0
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#ENDIF
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;
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;------------------------------------------------------------------------------
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; Probe HBIOS for devices and patch in I/O ports for devices
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@@ -1418,8 +1571,8 @@ cfgports: ret
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; Setup frame delay value - Loop count for DJNZ $ loop
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;------------------------------------------------------------------------------
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;
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#IF ((delay_type==cpu_loop) | (delay_type==hbios_tmr))
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setfdelay:
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#IF (delay_type==cpu_loop)
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#IF (plt_romwbw)
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LD BC,$F8F0 ; GET CPU SPEED
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RST 08 ; FROM HBIOS
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