From cb9ead08c7d4b55961814ae2b1f98fa818ec2cbe Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Wed, 6 Jun 2018 11:45:10 -0700 Subject: [PATCH] Finalize support for RC180 platform --- ReadMe.txt | 2 +- Source/Apps/XM/xmhb.180 | 127 ++++++++++++++++++++++++++++-- Source/CBIOS/cbios.asm | 9 +-- Source/CBIOS/ver.inc | 2 +- Source/HBIOS/Config/RC180_std.asm | 7 +- Source/HBIOS/cfg_rc180.asm | 2 +- Source/HBIOS/dbgmon.asm | 31 ++------ Source/HBIOS/hbios.asm | 19 +++-- Source/HBIOS/plt_rc.inc | 2 +- Source/HBIOS/plt_rc180.inc | 17 ++-- Source/HBIOS/ver.inc | 2 +- 11 files changed, 162 insertions(+), 58 deletions(-) diff --git a/ReadMe.txt b/ReadMe.txt index c5523808..4b41fbdf 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.1-pre.4, 2018-05-21 +Version 2.9.1-pre.5, 2018-06-06 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/Apps/XM/xmhb.180 b/Source/Apps/XM/xmhb.180 index ffc03b2b..f0c19936 100644 --- a/Source/Apps/XM/xmhb.180 +++ b/Source/Apps/XM/xmhb.180 @@ -3,7 +3,9 @@ ; XMHB.Z80 - XMODEMXX PATCH FILE FOR ROMWBW HBIOS ; ; Wayne Warthen - wwarthen@gmail.com -; Updated: 2017-11-08 +; Updated: 2018-06-06 +; +; 2018-06-06 WBW Added support for RC2014 w/ Z180 ; ;======================================================================= ; @@ -129,6 +131,8 @@ MINIT1: LD A,(PLTID) ; Get the platform id CP 7 ; Check for RC2014 JR Z,RCINIT ; Handle RC2014 special + CP 8 ; Check for RC2014 w/ Z180 + JR Z,ARCINIT ; Handle RC2014 w/ Z180 ; ; Check for Z180 which implies ASCI serial port LD DE,00202H ; D := 2, E := 2 @@ -153,6 +157,12 @@ RCINIT: LD DE,COMX ; HBIOS console notification string JR MINIT3 ; Complete the initialization ; +ARCINIT: + ; RC2014 running Z180 + LD HL,ARC_JPTBL ; ASCI RC2014 jump table address + LD DE,ASCIRC ; ASCI RC2014 console notification string + JR MINIT3 ; Complete the initialization +; MINIT3: PUSH HL ; Save HL @@ -220,10 +230,11 @@ PLTID DB 0 ; Platform ID CPUSPD DB 10 ; CPU speed in MHz RCVSCL DW 2800 ; RECV loop timeout scalar ; -RBC DB "RBC, 08-Nov-2017$" +RBC DB "RBC, 06-Jun-2018$" ; UART DB ", UART0$" ASCI DB ", ASCI0$" +ASCIRC DB ", ASCI0 (RC2014)$" COMX DB ", COM0$" ; UBTAG DB " [UNA]$" @@ -365,7 +376,7 @@ U_SNDRDY: ; ;----------------------------------------------------------------------- ; -; Report baud rate (index into SPTBL returned in regsiter A) +; Report baud rate (index into SPTBL returned in register A) ; U_SPEED: LD A,8 ; arbitrarily return 9600 baud @@ -387,6 +398,7 @@ A_DATP EQU 48H ;Z180 TSR - ASCI receive data port A_DATO EQU 46H ;Z180 TDR - ASCI transmit data port A_CTLP EQU 44H ;Z180 STAT - ASCI status port A_CTL2 EQU 40H ;Z180 CNTLA - ASCI control port +; A_SNDB EQU 02H ;Z180 STAT:TDRE - xmit data reg empty bit A_SNDR EQU 02H ;Z180 STAT:TDRE - xmit data reg empty value A_RCVB EQU 80H ;Z180 STAT:RDRF - rcv data reg full bit @@ -477,7 +489,7 @@ A_SNDRDY: ; ;----------------------------------------------------------------------- ; -; Report baud rate (index into SPTBL returned in regsiter A) +; Report baud rate (index into SPTBL returned in register A) ; A_SPEED: LD A,8 ; arbitrarily return 9600 baud @@ -486,6 +498,111 @@ A_SPEED: ;======================================================================= ;======================================================================= ; +; RC2014 Z180 primary ASCI port +; +; Will be used for all RC2014 Z180 systems. +; +;======================================================================= +;======================================================================= +; +; ASCI port constants for RC2014 +; +AR_DATP EQU 0C8H ;Z180 TSR - ASCI receive data port +AR_DATO EQU 0C6H ;Z180 TDR - ASCI transmit data port +AR_CTLP EQU 0C4H ;Z180 STAT - ASCI status port +AR_CTL2 EQU 0C0H ;Z180 CNTLA - ASCI control port +; +; Following jump table is dynamically patched over initial jump +; table at program startup. See MINIT above. Note that only a +; subset of the jump table is overlaid (SENDR to SPEED). +; +ARC_JPTBL: + JP AR_SENDR ;send character (via pop psw) + JP AR_CAROK ;test for carrier + JP AR_MDIN ;receive data byte + JP AR_GETCHR ;get character from modem + JP AR_RCVRDY ;check receive ready + JP AR_SNDRDY ;check send ready + JP AR_SPEED ;get speed value for file transfer time +; +;----------------------------------------------------------------------- +; +; Send character on top of stack +; +AR_SENDR: + POP AF ; get character to send from stack + OUT0 (AR_DATO),A ; send to port + RET +; +;----------------------------------------------------------------------- +; +; Test and rep;ort carrier status, Z set if carrier present +; +AR_CAROK: + XOR A ; not used, always indicate present + RET +; +;----------------------------------------------------------------------- +; +; Get a character (assume character ready has already been tested) +; +AR_MDIN: +AR_GETCHR: + IN0 A,(AR_DATP) ; read character from port + RET +; +;----------------------------------------------------------------------- +; +; Test for character ready to receive, Z = ready +; Error code returned in A register +; *** Error code does not seem to be used *** +; +AR_RCVRDY: + IN0 A,(AR_CTLP) ; get modem status + PUSH BC ; save scratch register + PUSH AF ; save full status on stack + AND A_FRME | A_OVRE | A_PARE ; isolate line err bits + LD B,A ; save err status in B + + ; Z180 ASCI ports will stall if there are errors. + ; Error bits are NOT cleared by merely reading + ; the status register. Below, bit 3 of ASCI + ; control register is written with a zero to + ; clear error(s) if needed. + JP Z,A_RCVRDY2 ; if no errs, continue + IN0 A,(AR_CTL2) ; get current control register + AND 0F7H ; force err reset bit to zero + OUT0 (AR_CTL2),A ; write control register + +AR_RCVRDY2: + POP AF ; get full status back + AND A_RCVB ; isolate ready bit + CP A_RCVR ; test it (set flags) + LD A,B ; get the error code back + POP BC ; restore scratch register + RET +; +;----------------------------------------------------------------------- +; +; Test for ready to send a character, Z = ready +; +AR_SNDRDY: + IN A,(AR_CTLP) ; get status + AND A_SNDB ; isolate transmit ready bit + CP A_SNDR ; test for ready value + RET +; +;----------------------------------------------------------------------- +; +; Report baud rate (index into SPTBL returned in register A) +; +AR_SPEED: + LD A,8 ; arbitrarily return 9600 baud + RET +; +;======================================================================= +;======================================================================= +; ; HBIOS CONSOLE (COM0:) ; ; Will be used for all RC2014 systems @@ -603,7 +720,7 @@ HB_SNDRDY: ; ;----------------------------------------------------------------------- ; -; Report baud rate (index into SPTBL returned in regsiter A) +; Report baud rate (index into SPTBL returned in register A) ; HB_SPEED: LD A,8 ; arbitrarily return 9600 baud diff --git a/Source/CBIOS/cbios.asm b/Source/CBIOS/cbios.asm index 232a7649..a134faab 100644 --- a/Source/CBIOS/cbios.asm +++ b/Source/CBIOS/cbios.asm @@ -222,7 +222,6 @@ DEVMAP: ; PUNCH (PUN:) .DB LD_TTY ; PUN:=TTY: (IOBYTE XX00XXXX) .DB LD_PTP ; PUN:=PTP: (IOBYTE XX01XXXX) - .DB LD_PTP ; PUN:=PTP: (IOBYTE XX01XXXX) .DB LD_UP1 ; PUN:=UP1: (IOBYTE XX10XXXX) .DB LD_UP2 ; PUN:=UP2: (IOBYTE XX11XXXX) ; LIST (LST:) @@ -2070,7 +2069,7 @@ DEV_INIT0: RET ; ALL DONE ; DEV_INIT1: - ; PATCH IN COM0: DEVICE ENTRIES + ; PATCH IN COM0: DEVICE ENTRIES, COM0: IS TTY: LD (DEVMAP + 0),A ; TTY: @ CON: LD (DEVMAP + 4),A ; TTY: @ RDR: LD (DEVMAP + 8),A ; TTY: @ PUN: @@ -2079,7 +2078,7 @@ DEV_INIT1: RET ; DEV_INIT2: - ; PATCH IN COM1: DEVICE ENTRIES + ; PATCH IN COM1: DEVICE ENTRIES, COM1: IS UC1:, PTR:, PTP:, LPT: LD (DEVMAP + 3),A ; UC1: @ CON: LD (DEVMAP + 5),A ; PTR: @ RDR: LD (DEVMAP + 9),A ; PTP: @ PUN: @@ -2088,7 +2087,7 @@ DEV_INIT2: RET ; DEV_INIT3: - ; PATCH IN COM2: DEVICE ENTRIES + ; PATCH IN COM2: DEVICE ENTRIES, COM2: IS UR1:, UP1:, UL1: LD (DEVMAP + 6),A ; UR1: @ RDR: LD (DEVMAP + 10),A ; UP1: @ PUN: LD (DEVMAP + 15),A ; UL1: @ LST: @@ -2096,7 +2095,7 @@ DEV_INIT3: RET ; DEV_INIT4: - ; PATCH IN COM3: DEVICE ENTRIES + ; PATCH IN COM3: DEVICE ENTRIES, COM3: IS UR2:, UP2: LD (DEVMAP + 7),A ; UR2: @ RDR: LD (DEVMAP + 11),A ; UP2: @ PUN: LD HL,DEV_INIT5 ; HL := CODE FOR NEXT DEVICE diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index bb4605bb..5554ec7e 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.1-pre.4" +#DEFINE BIOSVER "2.9.1-pre.5" diff --git a/Source/HBIOS/Config/RC180_std.asm b/Source/HBIOS/Config/RC180_std.asm index ab57ea1e..60095004 100644 --- a/Source/HBIOS/Config/RC180_std.asm +++ b/Source/HBIOS/Config/RC180_std.asm @@ -6,12 +6,13 @@ #include "cfg_rc180.asm" ; Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 3 ; MEMORY WAIT STATES TO INSERT (0-3) -Z180_IOWAIT .SET 3 ; IO WAIT STATES TO INSERT (0-3) +Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3) +Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3) ; CPUOSC .SET 18432000 ; CPU OSC FREQ -DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) +DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG ; +ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2 SIOMODE .SET SIOMODE_RC ; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA diff --git a/Source/HBIOS/cfg_rc180.asm b/Source/HBIOS/cfg_rc180.asm index 7b687313..e3b42043 100644 --- a/Source/HBIOS/cfg_rc180.asm +++ b/Source/HBIOS/cfg_rc180.asm @@ -7,7 +7,7 @@ ; CPUOSC .EQU 18432000 ; CPU OSC FREQ RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!! -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) +DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) INTMODE .EQU 2 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2 ; CRTACT .EQU FALSE ; CRT ACTIVATION AT STARTUP diff --git a/Source/HBIOS/dbgmon.asm b/Source/HBIOS/dbgmon.asm index 785cee3c..c653b026 100644 --- a/Source/HBIOS/dbgmon.asm +++ b/Source/HBIOS/dbgmon.asm @@ -559,10 +559,10 @@ UART_ENTRY: ; D XXXXH YYYYH DUMP MEMORY FROM XXXX TO YYYY ; F XXXXH YYYYH ZZH FILL MEMORY FROM XXXX TO YYYY WITH ZZ ; H LOAD INTEL HEX FORMAT DATA -; IXX INPUT FROM PORT XX AND SHOW HEX DATA +; I XX INPUT FROM PORT XX AND SHOW HEX DATA ; K ECHO KEYBOARD INPUT ; M XXXXH YYYYH ZZZZH MOVE MEMORY BLOCK XXXX TO YYYY TO ZZZZ -; OXX YY OUTPUT TO PORT XX HEX DATA YY +; O XX YY OUTPUT TO PORT XX HEX DATA YY ; P XXXXH YYH PROGRAM RAM FROM XXXXH WITH VALUE IN YYH, WILL PROMPT FOR NEXT LINES FOLLOWING UNTIL CR ; R RUN A PROGRAM FROM CURRENT LOCATION ; @@ -987,12 +987,13 @@ PHL: ; POUT: POUT1: -; INC HL ; + INC HL ; CALL HEXIN ; GET PORT LD C,A ; SAVE PORT POINTER INC HL ; CALL HEXIN ; GET DATA OUTIT: + LD B,0 ; MAKE SURE MSB IS ZERO OUT (C),A ; JP SERIALCMDLOOP ; @@ -1003,10 +1004,11 @@ OUTIT: ;_____________________________________________________________________________ ; PIN: -; INC HL ; + INC HL ; CALL HEXIN ; GET PORT LD C,A ; SAVE PORT POINTER CALL CRLF ; + LD B,0 ; MAKE SURE MSB IS ZERO IN A,(C) ; GET DATA CALL HXOUT ; SHOW IT JP SERIALCMDLOOP ; @@ -1651,27 +1653,6 @@ PROMPT: .DB CR,LF,'>',ENDT TXT_READY: - .DB CR,LF - .TEXT " NN NN 8888 VV VV EEEEEEEEEE MM MM" - .DB CR,LF - .TEXT " NNNN NN 88 88 VV VV EE MMMM MMMM" - .DB CR,LF - .TEXT " NN NN NN 88 88 VV VV EE MM MM MM MM" - .DB CR,LF - .TEXT " NN NNNN 88 88 VV VV EE MM MM MM" - .DB CR,LF - .TEXT " NN NN 8888 VV VV EEEEEEE MM MM" - .DB CR,LF - .TEXT " NN NN 88 88 VV VV EE MM MM" - .DB CR,LF - .TEXT " NN NN 88 88 VV VV EE MM MM" - .DB CR,LF - .TEXT " NN NN 88 88 VVV EE MM MM" - .DB CR,LF - .TEXT " NN NN 8888 V EEEEEEEEEE MM MM S B C" - .DB CR,LF - .DB CR,LF - .TEXT " ****************************************************************************" .DB CR,LF .TEXT "MONITOR READY " .DB CR,LF,ENDT diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 34f3704a..1a272628 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -67,7 +67,9 @@ MODCNT .SET MODCNT + 1 ; ; ; -; #DEFINE DIAGP $00 +#IF ((PLATFORM == PLT_RC) | (PLATFORM == PLT_RC180)) +#DEFINE DIAGP $00 +#ENDIF ; #IFDEF DIAGP #DEFINE DIAG(N) PUSH AF @@ -647,15 +649,21 @@ HB_STACK .EQU $ ; TOP OF HBIOS STACK HB_START: DI ; NO INTERRUPTS IM 1 ; INTERRUPT MODE 1 +; +#IFDEF DIAGP + LD A,%00000001 + OUT (DIAGP),A +#ENDIF +; LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY - - DIAG(%00000001) ; #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180)) ; SET BASE FOR CPU IO REGISTERS LD A,Z180_BASE OUT0 (Z180_ICR),A + DIAG(%00000010) + ; DISABLE REFRESH XOR A OUT0 (Z180_RCR),A @@ -908,11 +916,11 @@ PSCNX .EQU $ + 1 ; #IF (INTMODE == 2) ; SETUP Z80 IVT AND INT MODE 2 - ; SETUP Z180 IVT LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS LD I,A ; ... AND PLACE IT IN I REGISTER #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180)) + ; SETUP Z180 IVT XOR A ; SETUP LO BYTE OF IVT ADDRESS OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER #ENDIF @@ -943,7 +951,8 @@ PSCNX .EQU $ + 1 #IF (INTMODE == 2) ; ; MASK ALL EXTERNAL INTERRUPTS FOR NOW - XOR A ; INT0-2 DISABLED + ;XOR A ; INT0-2 DISABLED + LD A,$01 ; INT0 ENABLED, INT1-2 DISABLED OUT0 (Z180_ITC),A ; WRITE TO INT/TRAP CONTROL REGISTER ; ; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT diff --git a/Source/HBIOS/plt_rc.inc b/Source/HBIOS/plt_rc.inc index 78080c97..b9b1764e 100644 --- a/Source/HBIOS/plt_rc.inc +++ b/Source/HBIOS/plt_rc.inc @@ -6,5 +6,5 @@ MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY) MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY) MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY) MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) - +; RTC .EQU $C0 ; RTC PORT address diff --git a/Source/HBIOS/plt_rc180.inc b/Source/HBIOS/plt_rc180.inc index 950801b1..ee045790 100644 --- a/Source/HBIOS/plt_rc180.inc +++ b/Source/HBIOS/plt_rc180.inc @@ -1,16 +1,13 @@ ; ; RC2014 Z180 HARDWARE DEFINITIONS ; -SBC_BASE .EQU $60 ; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS -; -MPGSEL_0 .EQU SBC_BASE + $18 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY) -MPGSEL_1 .EQU SBC_BASE + $19 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY) -MPGSEL_2 .EQU SBC_BASE + $1A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY) -MPGSEL_3 .EQU SBC_BASE + $1B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY) -MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) -; -RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT -PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67 +MPGSEL_0 .EQU $78 ; BANK_0 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_1 .EQU $79 ; BANK_1 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_2 .EQU $7A ; BANK_2 PAGE SELECT REGISTER (WRITE ONLY) +MPGSEL_3 .EQU $7B ; BANK_3 PAGE SELECT REGISTER (WRITE ONLY) +MPGENA .EQU $7C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY) +; +RTC .EQU $0C ; ADDRESS OF RTC LATCH AND INPUT PORT ; Z180_BASE .EQU $C0 ; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS #INCLUDE "z180.inc" diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index bb4605bb..5554ec7e 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.1-pre.4" +#DEFINE BIOSVER "2.9.1-pre.5"