mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Support New Duodyne Boards
- Added support for Duodyne Multi-IO board - Added support for Duodyne Zilog-IO board - Added SUPCTS equate in hbios.asm to allow selectively adding code to suppress use of CTS during HBIOS boot - Added reference in User Guide to Bruce Hall's Assembly Language Programming document
This commit is contained in:
Wayne Warthen
@@ -46,15 +46,15 @@ RTCIO .EQU $94 ; RTC LATCH REGISTER ADR
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
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;
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
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CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
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CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
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CTCBASE .EQU $60 ; CTC BASE I/O ADDRESS
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CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
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CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
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CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
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CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
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CTCOSC .EQU (4915200/8) ; CTC CLOCK FREQUENCY
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CTCOSC .EQU (7372800/8) ; CTC CLOCK FREQUENCY
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;
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PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
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PCFBASE .EQU $56 ; PCF8584 BASE I/O ADDRESS
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@@ -132,7 +132,7 @@ UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
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UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
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UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
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UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
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UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
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;
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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;
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@@ -140,18 +140,18 @@ Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
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;
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ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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;
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SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
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SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
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SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BASE .EQU $60 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ACTCC .EQU 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCLK .EQU (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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SIO0BCTCC .EQU 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
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;
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
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;
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@@ -71,6 +71,8 @@
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;
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#DEFINE HBIOS
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;
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SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
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;
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; MAKE SURE EXACTLY ONE OF ROMBOOT, APPBOOT, IMGBOOT IS DEFINED.
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;
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MODCNT .EQU 0
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@@ -2300,8 +2302,36 @@ HB_BOOTDLY:
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JR C,HB_CONRDY ; IF TOO HIGH, JUST USE FAILSAFE
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LD A,BOOTCON ; GET REQUESTED CONSOLE DEV
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LD (CB_CONDEV),A ; SAVE IT
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;
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HB_CONRDY:
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;
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#IF (SUPCTS)
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;
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; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
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; IF THERE IS A PROBLEM WITH THE CTS SIGNAL, THEN OUTPUT TO THE CONSOLE
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; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
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; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR CTS TO BE ASSERTED. ALSO,
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; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
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; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT. SO, HERE
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; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
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; FLOW CONTROL. THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
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; PRIOR TO LAUNCING THE ROM LOADER.
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;
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; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
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LD B,BF_CIOQUERY ; HBIOS QUERY CIO CONFIG
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LD A,(CB_CONDEV) ; GET CONSOLE DEVICE
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LD (HB_BOOTCONSAV),A ; SAVE IT FOR LATER
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LD C,A ; BOOT CONSOLE TO C
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CALL HB_DISPATCH ; INTERNAL HBIOS CALL
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LD (HB_CONCFGSAV),DE ; SAVE CONFIG
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RES 5,D ; CLEAR RTS BIT
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LD B,BF_CIOINIT ; HBIOS CIO INIT
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LD A,(CB_CONDEV) ; GET CONSOLE DEVICE
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LD C,A ; BOOT CONSOLE TO C
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CALL HB_DISPATCH ; INTERNAL HBIOS CALL
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;
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#ENDIF
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;
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#IF (WBWDEBUG == USEMIO) ; OUTPUT ANY CACHED DEBUG TEXT
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LD HL,MIOOUTPTR
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LD E,(HL)
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@@ -2848,6 +2878,19 @@ HB_FPZ:
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;
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INITSYS3:
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;
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#IF (SUPCTS)
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;
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; RESTORE BOOT CONSOLE CONFIGURATION
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;
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CALL LDELAY ; ALLOW SERIAL PORT TO FLUSH
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LD B,BF_CIOINIT ; HBIOS CIO INIT
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LD A,(HB_BOOTCONSAV) ; ORIGINAL BOOT CONSOLE DEVICE
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LD C,A ; BOOT CONSOLE TO C
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LD DE,(HB_CONCFGSAV) ; SAVED ORIGINAL CONSOLE CFG
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CALL HB_DISPATCH ; INTERNAL HBIOS CALL
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;
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#ENDIF
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;
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; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE. A
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; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
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; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
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@@ -7721,6 +7764,11 @@ HB_BOOTCON .DB 0 ; INITIAL BOOT CONSOLE SAVE AREA
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HB_BOOTCFG .DW 0 ; CONSOLE CONFIG SAVE AREA
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HB_NEWCON .DB 0 ; NEW CONSOLE TO SWITCH TO
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;
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#IF (SUPCTS)
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HB_BOOTCONSAV .DB 0 ; INITIAL BOOT CONSOLE SAVE AREA
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HB_CONCFGSAV .DW 0 ; CONSOLE CONFIG SAVE AREA
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#ENDIF
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;
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HB_HASFP .DB 0 ; NON-ZERO MEANS FP EXISTS
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;
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HB_WRKBUF .FILL 512,0 ; INTERNAL DISK BUFFER
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@@ -837,7 +837,7 @@ INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
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INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
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INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
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INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
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;INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
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INT_SIO0 .EQU 6 ; ZILOG SIO 0, CHANNEL A & B
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INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
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INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
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INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
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@@ -63,7 +63,11 @@ UARTCBASE .EQU $80
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UARTMBASE .EQU $18
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UART4BASE .EQU $C0
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UARTRBASE .EQU $A0
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#IF (PLATFORM == PLT_DUO)
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UARTDBASE .EQU $70
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#ELSE
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UARTDBASE .EQU $80
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#ENDIF
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;
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#IF (UARTINTS)
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;
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