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Update vgmplay.asm 

YM2151 updates
pull/338/head
b1ackmai1er 3 years ago
parent
a646f49866
commit
cc9f5dd516
1 changed files with 366 additions and 288 deletions
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  1. 654
      Source/Apps/VGM/vgmplay.asm

654
Source/Apps/VGM/vgmplay.asm
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@ -12,14 +12,12 @@
; default file type, basic file size checking, polled CTC mode
; added by Phil Summers
;
; Bugs: YM2151 playback untested & no mute.
; CTC polled timing - predicted 44100 divider is too slow
; Bugs: CTC polled timing - predicted 44100 divider is too slow
;
; Assemble with:
;
; TASM -80 -b VGMPLAY.ASM VGMPLAY.COM
;
;
; A VGM file can play 44100 samples a second. This may be sound chip
; register commands or PCM data. This player does not support PCM playback
; due to the high processor speed and file size required. Typical VGM files
@ -31,60 +29,59 @@
; Device and system specific definitions
;------------------------------------------------------------------------------
;
custom .equ 0 ; System configurations
custom .equ 0 ; System configurations
P8X180 .equ 1
RCBUS .equ 2
sbcecb .equ 3
sbcecb .equ 3
MBC .equ 4
;
plt_romwbw .equ 1 ; Build for ROMWBW?
plt_type .equ sbcecb ; Select build configuration
debug .equ 0 ; Display port, register, config info
plt_romwbw .equ 1 ; Build for ROMWBW?
plt_type .equ sbcecb ; Select build configuration
debug .equ 0 ; Display port, register, config info
;
;------------------------------------------------------------------------------
; Platform specific definitions. If building for ROMWBW, these may be overridden
;------------------------------------------------------------------------------
#IF (plt_type=custom)
RSEL .equ 09AH ; Primary AY-3-8910 Register selection
RDAT .equ 09BH ; Primary AY-3-8910 Register data
RSEL2 .equ 88H ; Secondary AY-3-8910 Register selection
RDAT2 .equ 89H ; Secondary AY-3-8910 Register data
RSEL .equ 09AH ; Primary AY-3-8910 Register selection
RDAT .equ 09BH ; Primary AY-3-8910 Register data
RSEL2 .equ 88H ; Secondary AY-3-8910 Register selection
RDAT2 .equ 89H ; Secondary AY-3-8910 Register data
VGMBASE .equ $C0
YMSEL .equ VGMBASE+00H ; Primary YM2162 11000000 a1=0 a0=0
YMDAT .equ VGMBASE+01H ; Primary YM2162 11000001 a1=0 a0=1
YM2SEL .equ VGMBASE+02H ; Secondary YM2162 11000010 a1=1 a0=0
YM2DAT .equ VGMBASE+03H ; Secondary YM2162 11000011 a1=1 a0=1
PSG1REG .equ VGMBASE+08H ; Primary SN76489
PSG2REG .equ VGMBASE+09H ; Secondary SN76489
ctcbase .equ VGMBASE+0CH ; CTC base address
YM2151_SEL1 .equ 0FEH ; Primary YM2151 register selection
YM2151_DAT1 .equ 0FFH ; Primary YM2151 register data
YM2151_SEL2 .equ 0FEH ; Secondary YM2151 register selection
YM2151_DAT2 .equ 0FFH ; Secondary YM2151 register data
plt_cpuspd .equ 6;000000 ; Non ROMWBW cpu speed default
FRAME_DLY .equ 10 ; Frame delay (~ 1/44100)
YMSEL .equ VGMBASE+00H ; Primary YM2162 11000000 a1=0 a0=0
YMDAT .equ VGMBASE+01H ; Primary YM2162 11000001 a1=0 a0=1
YM2SEL .equ VGMBASE+02H ; Secondary YM2162 11000010 a1=1 a0=0
YM2DAT .equ VGMBASE+03H ; Secondary YM2162 11000011 a1=1 a0=1
PSG1REG .equ VGMBASE+04H ; Primary SN76489
PSG2REG .equ VGMBASE+05H ; Secondary SN76489
YM2151_SEL1 .equ VGMBASE+08H ; Primary YM2151 register selection
YM2151_DAT1 .equ VGMBASE+09H ; Primary YM2151 register data
YM2151_SEL2 .equ VGMBASE+0AH ; Secondary YM2151 register selection
YM2151_DAT2 .equ VGMBASE+0BH ; Secondary YM2151 register data
ctcbase .equ VGMBASE+0CH ; CTC base address
plt_cpuspd .equ 6;000000 ; Non ROMWBW cpu speed default
FRAME_DLY .equ 10 ; Frame delay (~ 1/44100)
#ENDIF
;
#IF (plt_type=P8X180)
RSEL .equ 82H ; Primary AY-3-8910 Register selection
RDAT .equ 83H ; Primary AY-3-8910 Register data
RSEL2 .equ 88H ; Secondary AY-3-8910 Register selection
RDAT2 .equ 89H ; Secondary AY-3-8910 Register data
PSG1REG .equ 84H ; Primary SN76489
PSG2REG .equ 8AH ; Secondary SN76489
YM2151_SEL1 .equ 0B0H ; Primary YM2151 register selection
YM2151_DAT1 .equ 0B1H ; Primary YM2151 register data
YM2151_SEL2 .equ 0B2H ; Secondary YM2151 register selection
YM2151_DAT2 .equ 0B3H ; Secondary YM2151 register data
ctcbase .equ 000H ; CTC base address
YMSEL .equ 000H ; Primary YM2162 11000000 a1=0 a0=0
YMDAT .equ 000H ; Primary YM2162 11000001 a1=0 a0=1
YM2SEL .equ 000H ; Secondary YM2162 11000010 a1=1 a0=0
YM2DAT .equ 000H ; Secondary YM2162 11000011 a1=1 a0=1
FRAME_DLY .equ 48 ; Frame delay (~ 1/44100)
plt_cpuspd .equ 20 ; Non ROMWBW cpu speed default
RSEL .equ 82H ; Primary AY-3-8910 Register selection
RDAT .equ 83H ; Primary AY-3-8910 Register data
RSEL2 .equ 88H ; Secondary AY-3-8910 Register selection
RDAT2 .equ 89H ; Secondary AY-3-8910 Register data
PSG1REG .equ 84H ; Primary SN76489
PSG2REG .equ 8AH ; Secondary SN76489
YM2151_SEL1 .equ 0B0H ; Primary YM2151 register selection
YM2151_DAT1 .equ 0B1H ; Primary YM2151 register data
YM2151_SEL2 .equ 0B2H ; Secondary YM2151 register selection
YM2151_DAT2 .equ 0B3H ; Secondary YM2151 register data
ctcbase .equ 000H ; CTC base address
YMSEL .equ 000H ; Primary YM2162 11000000 a1=0 a0=0
YMDAT .equ 000H ; Primary YM2162 11000001 a1=0 a0=1
YM2SEL .equ 000H ; Secondary YM2162 11000010 a1=1 a0=0
YM2DAT .equ 000H ; Secondary YM2162 11000011 a1=1 a0=1
FRAME_DLY .equ 48 ; Frame delay (~ 1/44100)
plt_cpuspd .equ 20 ; Non ROMWBW cpu speed default
#ENDIF
;
#IF (plt_type=RCBUS)
@ -103,7 +100,7 @@ YMSEL .equ 000H ; UNDEFINED ; Primary YM2162 11000000 a1=0 a0=0
YMDAT .equ 000H ; UNDEFINED ; Primary YM2162 11000001 a1=0 a0=1
YM2SEL .equ 000H ; UNDEFINED ; Secondary YM2162 11000010 a1=1 a0=0
YM2DAT .equ 000H ; UNDEFINED ; Secondary YM2162 11000011 a1=1 a0=1
plt_cpuspd .equ 7;372800 ; CPUOSC ; Non ROMWBW cpu speed default
plt_cpuspd .equ 7;372800 ; CPUOSC ; Non ROMWBW cpu speed default
FRAME_DLY .equ 12 ; Frame delay (~ 1/44100)
#ENDIF
;
@ -184,7 +181,7 @@ RTCIO .equ 070H
; YM2162 Register write macros - with wait and timeout
;------------------------------------------------------------------------------
;
#DEFINE setreg(reg,val) \
#DEFINE s2612reg(reg,val) \
#DEFCONT \ ld a,reg
#DEFCONT \ out (YMSEL),a
#DEFCONT \ ld a,val
@ -195,7 +192,7 @@ RTCIO .equ 070H
#DEFCONT \ jp nc,$+5
#DEFCONT \ djnz $-6
;
#DEFINE setreg2(reg,val) \
#DEFINE s2612reg2(reg,val) \
#DEFCONT \ ld a,reg
#DEFCONT \ out (YM2SEL),a
#DEFCONT \ ld a,val
@ -205,9 +202,30 @@ RTCIO .equ 070H
#DEFCONT \ rlca
#DEFCONT \ jp nc,$+5
#DEFCONT \ djnz $-6
;
;------------------------------------------------------------------------------
; VGM Codes - see vgmrips.net/wiki/VGM_specification
; YM2151 Register write macros - with wait and timeout
;------------------------------------------------------------------------------
;
; Status Byte: Bit
; 7 Busy Flag (1=Busy)
; 6-2 Not Used
; 1 Timer B Overflow (0=No Overflow, 1=Overflow)
; 0 Timer A Overflow (0=No Overflow, 1=Overflow)
;
#DEFINE s2151reg(reg,val) \
#DEFCONT \ ld a,reg
#DEFCONT \ out (YM2151_SEL1),a
#DEFCONT \ ld a,val
#DEFCONT \ out (YM2151_DAT1),a
#DEFCONT \ ld b,0
#DEFCONT \ in a,(YM2151_SEL1)
#DEFCONT \ rlca
#DEFCONT \ jp nc,$+5
#DEFCONT \ djnz $-6
;
;------------------------------------------------------------------------------
; VGM Codes - see vgmrips.net/wiki/VGM_Specification
;------------------------------------------------------------------------------
VGM_GG_W .equ 04FH ; GAME GEAR PSG STEREO. WRITE DD TO PORT 0X06
@ -219,8 +237,8 @@ VGM_WNS .equ 061H ; WAIT N SAMPLES
VGM_W735 .equ 062H ; WAIT 735 SAMPLES (1/60TH SECOND)
VGM_W882 .equ 063H ; WAIT 882 SAMPLES (1/50TH SECOND)
VGM_ESD .equ 066H ; END OF SOUND DATA
VGM_YM21511_W .equ 054H ; YM2612 #1 WRITE VALUE DD
VGM_YM21512_W .equ 0A4H ; YM2612 #2 WRITE VALUE DD
VGM_YM21511_W .equ 054H ; YM2151 #1 WRITE VALUE DD
VGM_YM21512_W .equ 0A4H ; YM2151 #2 WRITE VALUE DD
;------------------------------------------------------------------------------
; Generic CP/M definitions
@ -490,7 +508,7 @@ YM2162_2 CP VGM_YM26122_W
; YM2151 SECTION
;
YM2151_1 CP VGM_YM21511_W
JR NZ,YM2151_2
JR NZ,YM2151_2
LD A,(HL)
OUT (YM2151_SEL1),A
INC HL
@ -759,252 +777,254 @@ SKIP1: LD A,(IX+0)
XOR A
OUT (RDAT), A
OUT (RDAT2), A
#IFDEF SBCV2004
CALL FASTIO
#ENDIF
SKIP2: LD A,(IX+0) ; mute all channels on ym2612
AND %00110000
JP Z,SKIP3
setreg($22,$00) ; lfo off
setreg($27,$00) ; Disable independant Channel 3
setreg($28,$00) ; note off ch 1
setreg($28,$01) ; note off ch 2
setreg($28,$02) ; note off ch 3
setreg($28,$04) ; note off ch 4
setreg($28,$05) ; note off ch 5
setreg($28,$06) ; note off ch 6
setreg($2b,$00) ; dac off
setreg($b4,$00) ; sound off ch 1-3
setreg($b5,$00)
setreg($b6,$00)
setreg2($b4,$00) ; sound off ch 4-6
setreg2($b5,$00)
setreg2($b6,$00)
setreg($40,$7f) ; ch 1-3 total level minimum
setreg($41,$7f)
setreg($42,$7f)
setreg($44,$7f)
setreg($45,$7f)
setreg($46,$7f)
setreg($48,$7f)
setreg($49,$7f)
setreg($4a,$7f)
setreg($4c,$7f)
setreg($4d,$7f)
setreg($4e,$7f)
setreg2($40,$7f) ; ch 4-6 total level minimum
setreg2($41,$7f)
setreg2($42,$7f)
setreg2($44,$7f)
setreg2($45,$7f)
setreg2($46,$7f)
setreg2($48,$7f)
setreg2($49,$7f)
setreg2($4a,$7f)
setreg2($4c,$7f)
setreg2($4d,$7f)
setreg2($4e,$7f)
s2612reg($22,$00) ; lfo off
s2612reg($27,$00) ; Disable independant Channel 3
s2612reg($28,$00) ; note off ch 1
s2612reg($28,$01) ; note off ch 2
s2612reg($28,$02) ; note off ch 3
s2612reg($28,$04) ; note off ch 4
s2612reg($28,$05) ; note off ch 5
s2612reg($28,$06) ; note off ch 6
s2612reg($2b,$00) ; dac off
s2612reg($b4,$00) ; sound off ch 1-3
s2612reg($b5,$00)
s2612reg($b6,$00)
s2612reg2($b4,$00) ; sound off ch 4-6
s2612reg2($b5,$00)
s2612reg2($b6,$00)
s2612reg($40,$7f) ; ch 1-3 total level minimum
s2612reg($41,$7f)
s2612reg($42,$7f)
s2612reg($44,$7f)
s2612reg($45,$7f)
s2612reg($46,$7f)
s2612reg($48,$7f)
s2612reg($49,$7f)
s2612reg($4a,$7f)
s2612reg($4c,$7f)
s2612reg($4d,$7f)
s2612reg($4e,$7f)
s2612reg2($40,$7f) ; ch 4-6 total level minimum
s2612reg2($41,$7f)
s2612reg2($42,$7f)
s2612reg2($44,$7f)
s2612reg2($45,$7f)
s2612reg2($46,$7f)
s2612reg2($48,$7f)
s2612reg2($49,$7f)
s2612reg2($4a,$7f)
s2612reg2($4c,$7f)
s2612reg2($4d,$7f)
s2612reg2($4e,$7f)
#if (0)
setreg($2a,$00) ; dac value
setreg($24,$00) ; timer A frequency
setreg($25,$00) ; timer A frequency
setreg($26,$00) ; time B frequency
setreg($30,$00) ; ch 1-3 multiply & detune
setreg($31,$00)
setreg($32,$00)
setreg($34,$00)
setreg($35,$00)
setreg($36,$00)
setreg($38,$00)
setreg($39,$00)
setreg($3a,$00)
setreg($3c,$00)
setreg($3d,$00)
setreg($3e,$00)
setreg2($30,$00) ; ch 4-6 multiply & detune
setreg2($31,$00)
setreg2($32,$00)
setreg2($34,$00)
setreg2($35,$00)
setreg2($36,$00)
setreg2($38,$00)
setreg2($39,$00)
setreg2($3a,$00)
setreg2($3c,$00)
setreg2($3d,$00)
setreg2($3e,$00)
setreg($50,$00) ; ch 1-3 attack rate and scaling
setreg($51,$00)
setreg($52,$00)
setreg($54,$00)
setreg($55,$00)
setreg($56,$00)
setreg($58,$00)
setreg($59,$00)
setreg($5a,$00)
setreg($5c,$00)
setreg($5d,$00)
setreg($5e,$00)
setreg2($50,$00) ; ch 4-6 attack rate and scaling
setreg2($51,$00)
setreg2($52,$00)
setreg2($54,$00)
setreg2($55,$00)
setreg2($56,$00)
setreg2($58,$00)
setreg2($59,$00)
setreg2($5a,$00)
setreg2($5c,$00)
setreg2($5d,$00)
setreg2($5e,$00)
setreg($60,$00) ; ch 1-3 decay rate and am enable
setreg($61,$00)
setreg($62,$00)
setreg($64,$00)
setreg($65,$00)
setreg($66,$00)
setreg($68,$00)
setreg($69,$00)
setreg($6a,$00)
setreg($6c,$00)
setreg($6d,$00)
setreg($6e,$00)
setreg2($60,$00) ; ch 4-6 decay rate and am enable
setreg2($61,$00)
setreg2($62,$00)
setreg2($64,$00)
setreg2($65,$00)
setreg2($66,$00)
setreg2($68,$00)
setreg2($69,$00)
setreg2($6a,$00)
setreg2($6c,$00)
setreg2($6d,$00)
setreg2($6e,$00)
setreg($70,$00) ; ch 1-3 sustain rate
setreg($71,$00)
setreg($72,$00)
setreg($74,$00)
setreg($75,$00)
setreg($76,$00)
setreg($78,$00)
setreg($79,$00)
setreg($7a,$00)
setreg($7c,$00)
setreg($7d,$00)
setreg($7e,$00)
setreg2($70,$00) ; ch 4-6 sustain rate
setreg2($71,$00)
setreg2($72,$00)
setreg2($74,$00)
setreg2($75,$00)
setreg2($76,$00)
setreg2($78,$00)
setreg2($79,$00)
setreg2($7a,$00)
setreg2($7c,$00)
setreg2($7d,$00)
setreg2($7e,$00)
setreg($80,$00) ; ch 1-3 release rate and sustain level
setreg($81,$00)
setreg($82,$00)
setreg($84,$00)
setreg($85,$00)
setreg($86,$00)
setreg($88,$00)
setreg($89,$00)
setreg($8a,$00)
setreg($8c,$00)
setreg($8d,$00)
setreg($8e,$00)
setreg2($80,$00) ; ch 4-6 release rate and sustain level
setreg2($81,$00)
setreg2($82,$00)
setreg2($84,$00)
setreg2($85,$00)
setreg2($86,$00)
setreg2($88,$00)
setreg2($89,$00)
setreg2($8a,$00)
setreg2($8c,$00)
setreg2($8d,$00)
setreg2($8e,$00)
setreg($90,$00) ; ch 1-3 ssg-eg
setreg($91,$00)
setreg($92,$00)
setreg($94,$00)
setreg($95,$00)
setreg($96,$00)
setreg($98,$00)
setreg($99,$00)
setreg($9a,$00)
setreg($9c,$00)
setreg($9d,$00)
setreg($9e,$00)
setreg2($90,$00) ; ch 4-6 ssg-eg
setreg2($91,$00)
setreg2($92,$00)
setreg2($94,$00)
setreg2($95,$00)
setreg2($96,$00)
setreg2($98,$00)
setreg2($99,$00)
setreg2($9a,$00)
setreg2($9c,$00)
setreg2($9d,$00)
setreg2($9e,$00)
setreg($a0,$00) ; ch 1-3 frequency
setreg($a1,$00)
setreg($a2,$00)
setreg($a4,$00)
setreg($a5,$00)
setreg($a6,$00)
; setreg($a8,$00) ; ch 3 special mode
; setreg($a9,$00)
; setreg($aa,$00)
; setreg($ac,$00)
; setreg($ad,$00)
; setreg($ae,$00)
setreg2($a0,$00) ; ch 4-6 frequency
setreg2($a1,$00)
setreg2($a2,$00)
setreg2($a4,$00)
setreg2($a5,$00)
setreg2($a6,$00)
; setreg2($a8,$00) ; ch 3 special mode
; setreg2($a9,$00)
; setreg2($aa,$00)
; setreg2($ac,$00)
; setreg2($ad,$00)
; setreg2($ae,$00)
setreg($b0,$00) ; ch 1-3 algorith + feedback
setreg($b1,$00)
setreg($b2,$00)
setreg2($b0,$00) ; ch 4-6 algorith + feedback
setreg2($b1,$00)
setreg2($b2,$00)
s2612reg($2a,$00) ; dac value
s2612reg($24,$00) ; timer A frequency
s2612reg($25,$00) ; timer A frequency
s2612reg($26,$00) ; time B frequency
s2612reg($30,$00) ; ch 1-3 multiply & detune
s2612reg($31,$00)
s2612reg($32,$00)
s2612reg($34,$00)
s2612reg($35,$00)
s2612reg($36,$00)
s2612reg($38,$00)
s2612reg($39,$00)
s2612reg($3a,$00)
s2612reg($3c,$00)
s2612reg($3d,$00)
s2612reg($3e,$00)
s2612reg2($30,$00) ; ch 4-6 multiply & detune
s2612reg2($31,$00)
s2612reg2($32,$00)
s2612reg2($34,$00)
s2612reg2($35,$00)
s2612reg2($36,$00)
s2612reg2($38,$00)
s2612reg2($39,$00)
s2612reg2($3a,$00)
s2612reg2($3c,$00)
s2612reg2($3d,$00)
s2612reg2($3e,$00)
s2612reg($50,$00) ; ch 1-3 attack rate and scaling
s2612reg($51,$00)
s2612reg($52,$00)
s2612reg($54,$00)
s2612reg($55,$00)
s2612reg($56,$00)
s2612reg($58,$00)
s2612reg($59,$00)
s2612reg($5a,$00)
s2612reg($5c,$00)
s2612reg($5d,$00)
s2612reg($5e,$00)
s2612reg2($50,$00) ; ch 4-6 attack rate and scaling
s2612reg2($51,$00)
s2612reg2($52,$00)
s2612reg2($54,$00)
s2612reg2($55,$00)
s2612reg2($56,$00)
s2612reg2($58,$00)
s2612reg2($59,$00)
s2612reg2($5a,$00)
s2612reg2($5c,$00)
s2612reg2($5d,$00)
s2612reg2($5e,$00)
s2612reg($60,$00) ; ch 1-3 decay rate and am enable
s2612reg($61,$00)
s2612reg($62,$00)
s2612reg($64,$00)
s2612reg($65,$00)
s2612reg($66,$00)
s2612reg($68,$00)
s2612reg($69,$00)
s2612reg($6a,$00)
s2612reg($6c,$00)
s2612reg($6d,$00)
s2612reg($6e,$00)
s2612reg2($60,$00) ; ch 4-6 decay rate and am enable
s2612reg2($61,$00)
s2612reg2($62,$00)
s2612reg2($64,$00)
s2612reg2($65,$00)
s2612reg2($66,$00)
s2612reg2($68,$00)
s2612reg2($69,$00)
s2612reg2($6a,$00)
s2612reg2($6c,$00)
s2612reg2($6d,$00)
s2612reg2($6e,$00)
s2612reg($70,$00) ; ch 1-3 sustain rate
s2612reg($71,$00)
s2612reg($72,$00)
s2612reg($74,$00)
s2612reg($75,$00)
s2612reg($76,$00)
s2612reg($78,$00)
s2612reg($79,$00)
s2612reg($7a,$00)
s2612reg($7c,$00)
s2612reg($7d,$00)
s2612reg($7e,$00)
s2612reg2($70,$00) ; ch 4-6 sustain rate
s2612reg2($71,$00)
s2612reg2($72,$00)
s2612reg2($74,$00)
s2612reg2($75,$00)
s2612reg2($76,$00)
s2612reg2($78,$00)
s2612reg2($79,$00)
s2612reg2($7a,$00)
s2612reg2($7c,$00)
s2612reg2($7d,$00)
s2612reg2($7e,$00)
s2612reg($80,$00) ; ch 1-3 release rate and sustain level
s2612reg($81,$00)
s2612reg($82,$00)
s2612reg($84,$00)
s2612reg($85,$00)
s2612reg($86,$00)
s2612reg($88,$00)
s2612reg($89,$00)
s2612reg($8a,$00)
s2612reg($8c,$00)
s2612reg($8d,$00)
s2612reg($8e,$00)
s2612reg2($80,$00) ; ch 4-6 release rate and sustain level
s2612reg2($81,$00)
s2612reg2($82,$00)
s2612reg2($84,$00)
s2612reg2($85,$00)
s2612reg2($86,$00)
s2612reg2($88,$00)
s2612reg2($89,$00)
s2612reg2($8a,$00)
s2612reg2($8c,$00)
s2612reg2($8d,$00)
s2612reg2($8e,$00)
s2612reg($90,$00) ; ch 1-3 ssg-eg
s2612reg($91,$00)
s2612reg($92,$00)
s2612reg($94,$00)
s2612reg($95,$00)
s2612reg($96,$00)
s2612reg($98,$00)
s2612reg($99,$00)
s2612reg($9a,$00)
s2612reg($9c,$00)
s2612reg($9d,$00)
s2612reg($9e,$00)
s2612reg2($90,$00) ; ch 4-6 ssg-eg
s2612reg2($91,$00)
s2612reg2($92,$00)
s2612reg2($94,$00)
s2612reg2($95,$00)
s2612reg2($96,$00)
s2612reg2($98,$00)
s2612reg2($99,$00)
s2612reg2($9a,$00)
s2612reg2($9c,$00)
s2612reg2($9d,$00)
s2612reg2($9e,$00)
s2612reg($a0,$00) ; ch 1-3 frequency
s2612reg($a1,$00)
s2612reg($a2,$00)
s2612reg($a4,$00)
s2612reg($a5,$00)
s2612reg($a6,$00)
; s2612reg($a8,$00) ; ch 3 special mode
; s2612reg($a9,$00)
; s2612reg($aa,$00)
; s2612reg($ac,$00)
; s2612reg($ad,$00)
; s2612reg($ae,$00)
s2612reg2($a0,$00) ; ch 4-6 frequency
s2612reg2($a1,$00)
s2612reg2($a2,$00)
s2612reg2($a4,$00)
s2612reg2($a5,$00)
s2612reg2($a6,$00)
; s2612reg2($a8,$00) ; ch 3 special mode
; s2612reg2($a9,$00)
; s2612reg2($aa,$00)
; s2612reg2($ac,$00)
; s2612reg2($ad,$00)
; s2612reg2($ae,$00)
s2612reg($b0,$00) ; ch 1-3 algorith + feedback
s2612reg($b1,$00)
s2612reg($b2,$00)
s2612reg2($b0,$00) ; ch 4-6 algorith + feedback
s2612reg2($b1,$00)
s2612reg2($b2,$00)
#endif
@ -1014,6 +1034,64 @@ SKIP3: LD A,(IX+0) ; For YM2151 ... Unimplemented
; MUTE YM2151
s2151reg($14,$30) ; disable timer %00110000
s2151reg($0f,$00) ; disable noise
;
s2151reg($1b,$00) ; CTx output off, LFO waveform
s2151reg($08,$00) ; key off all channels
s2151reg($08,$01)
s2151reg($08,$02)
s2151reg($08,$03)
s2151reg($08,$04)
s2151reg($08,$05)
s2151reg($08,$06)
s2151reg($08,$07)
s2151reg($60,$7f) ; total level = silent
s2151reg($61,$7f)
s2151reg($62,$7f)
s2151reg($63,$7f)
s2151reg($64,$7f)
s2151reg($65,$7f)
s2151reg($66,$7f)
s2151reg($67,$7f)
s2151reg($68,$7f)
s2151reg($69,$7f)
s2151reg($6A,$7f)
s2151reg($6B,$7f)
s2151reg($6C,$7f)
s2151reg($6D,$7f)
s2151reg($6E,$7f)
s2151reg($6F,$7f)
s2151reg($70,$7f)
s2151reg($71,$7f)
s2151reg($72,$7f)
s2151reg($73,$7f)
s2151reg($74,$7f)
s2151reg($75,$7f)
s2151reg($76,$7f)
s2151reg($77,$7f)
s2151reg($78,$7f)
s2151reg($79,$7f)
s2151reg($7A,$7f)
s2151reg($7B,$7f)
s2151reg($7C,$7f)
s2151reg($7D,$7f)
s2151reg($7E,$7f)
s2151reg($7F,$7f)
s2151reg($20,$00) ; channel output off, no feedback
s2151reg($21,$00)
s2151reg($22,$00)
s2151reg($23,$00)
s2151reg($24,$00)
s2151reg($25,$00)
s2151reg($26,$00)
s2151reg($27,$00)
;
SKIP4 RET
;
;------------------------------------------------------------------------------

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