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Refactor UART Mode Settings 

- Replaced hard-coded mode settings with per-chip configuration settings.
pull/409/head
Wayne Warthen 2 years ago
parent
3999039102
commit
cd23863226
28 changed files with 517 additions and 403 deletions
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  1. 1
      Doc/ChangeLog.txt
  2. 2
      Source/HBIOS/Config/HEATH_std.asm
  3. 3
      Source/HBIOS/Config/MK4_std.asm
  4. 12
      Source/HBIOS/Config/SBC_simh.asm
  5. 5
      Source/HBIOS/Config/SBC_std.asm
  6. 31
      Source/HBIOS/cfg_duo.asm
  7. 28
      Source/HBIOS/cfg_dyno.asm
  8. 28
      Source/HBIOS/cfg_epitx.asm
  9. 28
      Source/HBIOS/cfg_fz80.asm
  10. 30
      Source/HBIOS/cfg_heath.asm
  11. 29
      Source/HBIOS/cfg_master.asm
  12. 29
      Source/HBIOS/cfg_mbc.asm
  13. 29
      Source/HBIOS/cfg_mk4.asm
  14. 29
      Source/HBIOS/cfg_n8.asm
  15. 28
      Source/HBIOS/cfg_nabu.asm
  16. 28
      Source/HBIOS/cfg_rcz180.asm
  17. 28
      Source/HBIOS/cfg_rcz280.asm
  18. 28
      Source/HBIOS/cfg_rcz80.asm
  19. 29
      Source/HBIOS/cfg_rph.asm
  20. 28
      Source/HBIOS/cfg_s100.asm
  21. 29
      Source/HBIOS/cfg_sbc.asm
  22. 28
      Source/HBIOS/cfg_scz180.asm
  23. 29
      Source/HBIOS/cfg_z80retro.asm
  24. 29
      Source/HBIOS/cfg_zeta.asm
  25. 29
      Source/HBIOS/cfg_zeta2.asm
  26. 319
      Source/HBIOS/uart.asm
  27. 2
      Source/ver.inc
  28. 2
      Source/ver.lib

1
Doc/ChangeLog.txt
View File

@ -27,6 +27,7 @@ Version 3.5
- WBW: Added support for DS1305 RTC on S100 FPGA Z80 - WBW: Added support for DS1305 RTC on S100 FPGA Z80
- WBW: Added support for Les Bird's RCBus Graphics/Sound/Joystick module - WBW: Added support for Les Bird's RCBus Graphics/Sound/Joystick module
- WBW: Added support for Les Bird's Dual 16C550 UART module - WBW: Added support for Les Bird's Dual 16C550 UART module
- WBW: Refactor UART driver for more flexible configuration
Version 3.4 Version 3.4
----------- -----------

2
Source/HBIOS/Config/HEATH_std.asm
View File

@ -24,7 +24,7 @@
; ;
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
; ;
#include "cfg_rcz80.asm"
#include "cfg_heath.asm"
; ;
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP

3
Source/HBIOS/Config/MK4_std.asm
View File

@ -35,9 +35,6 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
; ;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCAS .SET TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .SET TRUE ; UART: AUTO-DETECT MF/PIC UART
UART4 .SET TRUE ; UART: AUTO-DETECT 4UART UART
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)

12
Source/HBIOS/Config/SBC_simh.asm
View File

@ -33,7 +33,15 @@ HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
; ;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTSBCFORCE .SET TRUE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
SSERSTATUS .SET $6D ; SSER: STATUS PORT
SSERDATA .SET $68 ; SSER: DATA PORT
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
SSERORDY .SET %00100000 ; SSER: OUTPUT READY BIT MASK
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
; ;
HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)

5
Source/HBIOS/Config/SBC_std.asm
View File

@ -31,11 +31,6 @@ INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
; ;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .SET TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .SET TRUE ; UART: AUTO-DETECT MF/PIC UART
UART4 .SET TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .SET FALSE ; UART: AUTO-DETECT RC UART
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
; ;
TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)

31
Source/HBIOS/cfg_duo.asm
View File

@ -137,18 +137,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 7372800 ; UART: OSC FREQUENCY IN MHZ
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU TRUE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $58 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $A8 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $70 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $78 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

28
Source/HBIOS/cfg_dyno.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

28
Source/HBIOS/cfg_epitx.asm
View File

@ -148,17 +148,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $A0 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $A8 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

28
Source/HBIOS/cfg_fz80.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

30
Source/HBIOS/cfg_heath.asm
View File

@ -80,7 +80,7 @@ FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
; ;
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU]
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
; ;
@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $E8 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $E0 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

29
Source/HBIOS/cfg_master.asm
View File

@ -175,18 +175,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

29
Source/HBIOS/cfg_mbc.asm
View File

@ -134,18 +134,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $88 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

29
Source/HBIOS/cfg_mk4.asm
View File

@ -139,18 +139,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 6 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $18 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $C0 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $C8 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $D0 ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $D8 ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

29
Source/HBIOS/cfg_n8.asm
View File

@ -141,18 +141,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 5 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $C0 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $C8 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $D0 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $D8 ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

28
Source/HBIOS/cfg_nabu.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $48 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

28
Source/HBIOS/cfg_rcz180.asm
View File

@ -152,17 +152,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

28
Source/HBIOS/cfg_rcz280.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

28
Source/HBIOS/cfg_rcz80.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

29
Source/HBIOS/cfg_rph.asm
View File

@ -139,18 +139,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

28
Source/HBIOS/cfg_s100.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

29
Source/HBIOS/cfg_sbc.asm
View File

@ -134,18 +134,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 7 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU TRUE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $80 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $18 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $C0 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $C8 ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $D0 ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $D8 ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

28
Source/HBIOS/cfg_scz180.asm
View File

@ -146,17 +146,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $80 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $88 ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $A0 ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $A8 ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

29
Source/HBIOS/cfg_z80retro.asm
View File

@ -137,18 +137,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

29
Source/HBIOS/cfg_zeta.asm
View File

@ -126,18 +126,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

29
Source/HBIOS/cfg_zeta2.asm
View File

@ -137,18 +137,27 @@ SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $68 ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU SER_300_8N1 ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
; ;

319
Source/HBIOS/uart.asm
View File

@ -54,27 +54,6 @@ UART_FIFOACT .EQU 6 ; FIFO ACTIVE BIT
UART_AFCACT .EQU 5 ; AUTO FLOW CONTROL ACTIVE BIT UART_AFCACT .EQU 5 ; AUTO FLOW CONTROL ACTIVE BIT
UART_CTSBAD .EQU 4 ; CTS STALL DETECTED UART_CTSBAD .EQU 4 ; CTS STALL DETECTED
; ;
#IF (PLATFORM == PLT_DUO)
UARTSBASE .EQU $58
UARTDBASE .EQU $70
#ENDIF
;
#IF (PLATFORM == PLT_NABU)
UARTSBASE .EQU $48
UARTDBASE .EQU $80
#ENDIF
;
#IF ((PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU))
UARTSBASE .EQU $68
UARTDBASE .EQU $80
#ENDIF
;
UARTABASE .EQU $A8
UARTCBASE .EQU $80
UARTMBASE .EQU $18
UART4BASE .EQU $C0
UARTRBASE .EQU $A0
;
#IF (UARTINTS) #IF (UARTINTS)
; ;
#IF ((INTMODE == 2) | (INTMODE == 3)) #IF ((INTMODE == 2) | (INTMODE == 3))
@ -92,17 +71,17 @@ UART1_IVT .EQU IVT(INT_UART1)
; ;
; ;
UART_PREINIT: UART_PREINIT:
#IF (UART4)
#IF (UART4UART)
; ;
; INIT UART4 BOARD CONFIG REGISTER (NO HARM IF IT IS NOT THERE) ; INIT UART4 BOARD CONFIG REGISTER (NO HARM IF IT IS NOT THERE)
; ;
LD A,$80 ; SELECT 7.3728MHZ OSC & LOCK CONFIG REGISTER LD A,$80 ; SELECT 7.3728MHZ OSC & LOCK CONFIG REGISTER
OUT (UART4BASE+$0F),A ; DO IT
OUT (UART4UARTBASE+$0F),A ; DO IT
#ENDIF #ENDIF
; ;
; SETUP THE DISPATCH TABLE ENTRIES ; SETUP THE DISPATCH TABLE ENTRIES
; ;
LD B,UART_CNT ; LOOP CONTROL
LD B,UARTCNT ; LOOP CONTROL
LD C,0 ; PHYSICAL UNIT INDEX LD C,0 ; PHYSICAL UNIT INDEX
XOR A ; ZERO TO ACCUM XOR A ; ZERO TO ACCUM
LD (UART_DEV),A ; CURRENT DEVICE NUMBER LD (UART_DEV),A ; CURRENT DEVICE NUMBER
@ -203,7 +182,7 @@ UART_INITUNIT1:
; ;
; ;
UART_INIT: UART_INIT:
LD B,UART_CNT ; COUNT OF POSSIBLE UART UNITS
LD B,UARTCNT ; COUNT OF POSSIBLE UART UNITS
LD C,0 ; INDEX INTO UART CONFIG TABLE LD C,0 ; INDEX INTO UART CONFIG TABLE
UART_INIT1: UART_INIT1:
PUSH BC ; SAVE LOOP CONTROL PUSH BC ; SAVE LOOP CONTROL
@ -249,14 +228,14 @@ UART_INIT2:
UART_INT: UART_INT:
; ;
#IF (UARTSBC)
LD IY,UART_CFG_SBC
#IF (UARTCNT >= 1)
LD IY,UART0_CFG
CALL UART_INTRCV CALL UART_INTRCV
RET NZ RET NZ
#ENDIF #ENDIF
; ;
#IF (UARTCAS)
LD IY,UART_CFG_CAS
#IF (UARTCNT >= 2)
LD IY,UART1_CFG
CALL UART_INTRCV CALL UART_INTRCV
RET NZ RET NZ
#ENDIF #ENDIF
@ -265,15 +244,15 @@ UART_INT:
; ;
#IF ((INTMODE == 2) | (INTMODE == 3)) #IF ((INTMODE == 2) | (INTMODE == 3))
; ;
#IF (UARTSBC)
UART_INTSBC:
LD IY,UART_CFG_SBC
#IF (UARTCNT >= 1)
UART_INT0:
LD IY,UART0_CFG
JR UART_INTRCV JR UART_INTRCV
#ENDIF #ENDIF
; ;
#IF (UARTCAS)
UART_INTCAS:
LD IY,UART_CFG_CAS
#IF (UARTCNT >= 2)
UART_INT1:
LD IY,UART1_CFG
JR UART_INTRCV JR UART_INTRCV
#ENDIF #ENDIF
; ;
@ -837,16 +816,6 @@ UART_CHIP2: ; PICK BETWEEN 16550A/C
JR UART_CHIP_16550C ; IS SET, SO 16550C JR UART_CHIP_16550C ; IS SET, SO 16550C
; ;
UART_CHIP_NONE: UART_CHIP_NONE:
;
#IF (UARTSBCFORCE)
; SIMH DOES NOT EMULATE A UART WELL ENOUGH TO BE DETECTED, SO
; THIS BIT OF CODE CAN BE ENABLED TO FORCE THE PRIMARY SBC
; UART TO BE HANDLED AS AN 8250.
LD A,(IY+2) ; BASE IO PORT
CP UARTSBASE ; IS THIS PRIMARY SBC PORT?
JR Z,UART_CHIP_8250 ; SPECIAL CASE FOR PRIMARY UART!
#ENDIF
;
LD A,UART_NONE ; NO UART DETECTED AT THIS PORT LD A,UART_NONE ; NO UART DETECTED AT THIS PORT
RET RET
; ;
@ -1028,199 +997,153 @@ UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT
; UART PORT TABLE ; UART PORT TABLE
; ;
UART_CFG: UART_CFG:
#IF (UARTSBC)
UART_CFG_SBC:
; SBC/ZETA ONBOARD SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTSBASE ; IO PORT BASE (RBR, THR)
.DB UARTSBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW UARTSBC_RCVBUF ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: MODE=SBC, IO="
DEVECHO UARTSBASE
;
#IF (UARTCNT >= 1)
UART0_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART0BASE ; IO PORT BASE (RBR, THR)
.DB UART0BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART0CFG ; LINE CONFIGURATION
.DW UART0_RCVBUF ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART0BASE
#IF ((UARTINTS) & (INTMODE > 0)) #IF ((UARTINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF #ENDIF
DEVECHO "\n" DEVECHO "\n"
#ENDIF #ENDIF
#IF (UARTAUX)
UART_CFG_AUX:
; AUX SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTABASE ; IO PORT BASE (RBR, THR)
.DB UARTABASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; NO INT HANDLER
;
DEVECHO "UART: MODE=AUX, IO="
DEVECHO UARTABASE
DEVECHO "\n"
#ENDIF
#IF (UARTCAS)
UART_CFG_CAS:
; CASSETTE INTERFACE SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTCBASE ; IO PORT BASE (RBR, THR)
.DB UARTCBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCASSPD ; LINE CONFIGURATION
.DW UARTCAS_RCVBUF ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: MODE=CAS, IO="
DEVECHO UARTCBASE
;
#IF (UARTCNT >= 2)
UART1_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART1BASE ; IO PORT BASE (RBR, THR)
.DB UART1BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART1CFG ; LINE CONFIGURATION
.DW UART1_RCVBUF ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART1BASE
#IF ((UARTINTS) & (INTMODE > 0)) #IF ((UARTINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF #ENDIF
DEVECHO "\n" DEVECHO "\n"
#ENDIF #ENDIF
#IF (UARTMFP)
UART_CFG_MFP:
; MF/PIC SERIAL PORT
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTMBASE ; IO PORT BASE (RBR, THR)
.DB UARTMBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=MFP, IO="
DEVECHO UARTSBASE
;
#IF (UARTCNT >= 3)
UART2_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART2BASE ; IO PORT BASE (RBR, THR)
.DB UART2BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART2CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART2BASE
DEVECHO "\n" DEVECHO "\n"
#ENDIF #ENDIF
#IF (UART4)
; 4UART SERIAL PORT A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UART4BASE+0 ; IO PORT BASE (RBR, THR)
.DB UART4BASE+0 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=4UART, IO="
DEVECHO UART4BASE+0
DEVECHO "\n"
; ;
; 4UART SERIAL PORT B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UART4BASE+8 ; IO PORT BASE (RBR, THR)
.DB UART4BASE+8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=4UART, IO="
DEVECHO UART4BASE+8
#IF (UARTCNT >= 4)
UART3_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART3BASE ; IO PORT BASE (RBR, THR)
.DB UART3BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART3CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART3BASE
DEVECHO "\n" DEVECHO "\n"
#ENDIF
; ;
; 4UART SERIAL PORT C
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UART4BASE+16 ; IO PORT BASE (RBR, THR)
.DB UART4BASE+16 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=4UART, IO="
DEVECHO UART4BASE+16
#IF (UARTCNT >= 5)
UART4_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART4BASE ; IO PORT BASE (RBR, THR)
.DB UART4BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART4CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART4BASE
DEVECHO "\n" DEVECHO "\n"
#ENDIF
; ;
; 4UART SERIAL PORT D
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UART4BASE+24 ; IO PORT BASE (RBR, THR)
.DB UART4BASE+24 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=4UART, IO="
DEVECHO UART4BASE+24
#IF (UARTCNT >= 6)
UART5_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART5BASE ; IO PORT BASE (RBR, THR)
.DB UART5BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART5CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART5BASE
DEVECHO "\n" DEVECHO "\n"
#ENDIF #ENDIF
#IF (UARTRC)
; UARTRC SERIAL PORT A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTRBASE ; IO PORT BASE (RBR, THR)
.DB UARTRBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=RC, IO="
DEVECHO UARTRBASE+0
DEVECHO "\n"
; ;
; UARTRC SERIAL PORT B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTRBASE+8 ; IO PORT BASE (RBR, THR)
.DB UARTRBASE+8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=RC, IO="
DEVECHO UARTRBASE+8
#IF (UARTCNT >= 7)
UART6_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART6BASE ; IO PORT BASE (RBR, THR)
.DB UART6BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART6CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART6BASE
DEVECHO "\n" DEVECHO "\n"
;
#ENDIF #ENDIF
#IF (UARTDUAL)
; DUAL UART CHANNEL A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTDBASE ; IO PORT BASE (RBR, THR)
.DB UARTDBASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
; DUAL UART CHANNEL B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB UARTDBASE+8 ; IO PORT BASE (RBR, THR)
.DB UARTDBASE+8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.DW 0 ; SHOULD NEVER NEED INT HANDLER
;
DEVECHO "UART: MODE=DUAL, IO="
DEVECHO UARTDBASE+0
DEVECHO "\n"
; ;
DEVECHO "UART: MODE=DUAL, IO="
DEVECHO UARTDBASE+8
#IF (UARTCNT >= 8)
UART7_CFG:
.DB 0 ; DEVICE NUMBER (SET DURING INIT)
.DB 0 ; UART TYPE (SET DURING INIT)
.DB UART7BASE ; IO PORT BASE (RBR, THR)
.DB UART7BASE + UART_LSR ; LINE STATUS PORT (LSR)
.DW UART7CFG ; LINE CONFIGURATION
.DW 0 ; POINTER TO RCV BUFFER STRUCT
;
DEVECHO "UART: IO="
DEVECHO UART7BASE
DEVECHO "\n" DEVECHO "\n"
;
#ENDIF #ENDIF
; ;
UART_CNT .EQU ($ - UART_CFG) / 8
;
#IF ((!UARTINTS) | (INTMODE == 0)) #IF ((!UARTINTS) | (INTMODE == 0))
; ;
UARTSBC_RCVBUF .EQU 0
UARTCAS_RCVBUF .EQU 0
UART0_RCVBUF .EQU 0
UART1_RCVBUF .EQU 0
; ;
#ELSE #ELSE
; ;
; UART SBC RECEIVE BUFFER ; UART SBC RECEIVE BUFFER
; ;
#IF (UARTSBC)
#IF (UARTCNT >= 1)
; ;
UARTSBC_RCVBUF:
UARTSBC_CNT .DB 0 ; CHARACTERS IN RING BUFFER
UARTSBC_HD .DW UARTSBC_BUF ; BUFFER HEAD POINTER
UARTSBC_TL .DW UARTSBC_BUF ; BUFFER TAIL POINTER
UARTSBC_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER
UART0_RCVBUF:
UART0_CNT .DB 0 ; CHARACTERS IN RING BUFFER
UART0_HD .DW UART0_BUF ; BUFFER HEAD POINTER
UART0_TL .DW UART0_BUF ; BUFFER TAIL POINTER
UART0_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER
; ;
#ENDIF #ENDIF
; ;
; UART CASSETTE RECEIVE BUFFER ; UART CASSETTE RECEIVE BUFFER
; ;
#IF (UARTCAS)
#IF (UARTCNT >= 2)
; ;
UARTCAS_RCVBUF:
UARTCAS_CNT .DB 0 ; CHARACTERS IN RING BUFFER
UARTCAS_HD .DW UARTCAS_BUF ; BUFFER HEAD POINTER
UARTCAS_TL .DW UARTCAS_BUF ; BUFFER TAIL POINTER
UARTCAS_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER
UART1_RCVBUF:
UART1_CNT .DB 0 ; CHARACTERS IN RING BUFFER
UART1_HD .DW UART1_BUF ; BUFFER HEAD POINTER
UART1_TL .DW UART1_BUF ; BUFFER TAIL POINTER
UART1_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER
; ;
#ENDIF #ENDIF
; ;

2
Source/ver.inc
View File

@ -2,7 +2,7 @@
#DEFINE RMN 5 #DEFINE RMN 5
#DEFINE RUP 0 #DEFINE RUP 0
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "3.5.0-dev.58"
#DEFINE BIOSVER "3.5.0-dev.59"
#define rmj RMJ #define rmj RMJ
#define rmn RMN #define rmn RMN
#define rup RUP #define rup RUP

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 5
rup equ 0 rup equ 0
rtp equ 0 rtp equ 0
biosver macro biosver macro
db "3.5.0-dev.58"
db "3.5.0-dev.59"
endm endm

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