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Merge pull request #232 from wwarthen/dev

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BPBIOS Updates
This commit is contained in:
b1ackmai1er
2021-10-10 13:57:23 +08:00
committed by GitHub
parent 1db11ca924 32228eb89c
commit cea11393db
56 changed files with 337 additions and 11800 deletions
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11
Source/BPBIOS/@WBW Issues.txt
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@@ -15,17 +15,8 @@ as needed. The RomWBW ASSIGN command is not supported. BPBIOS
will boot from the first hard disk unit number you assign and
always from the first slice.
As documented in "@WBW Z3ENV.txt", there are two general
configurations of BPBIOS for RomWBW. I strongly recommend
using the T configurations (external HBIOS proxy). This is
the long term direction for BPBIOS on RomWBW. The N
configurations (internal HBIOS proxy) will not work with
interrrupts of any kind. This means that to use the N
configurations, you *must* use a RomWBW ROM built with
interrupts disabled or chaos will ensue.
BPBIOS does not yet understand the 1024 directory entry
hard disk format. You must use the 512 directory entry
format images.
--WBW 7:32 PM 10/3/2021
--WBW 1:25 PM 10/7/2021

161
Source/BPBIOS/@WBW Z3ENV.txt
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@@ -4,7 +4,7 @@ BPBIOS for RomWBW / HBIOS
The build process included in this directory constructs multiple BPBIOS OS images that
can be loaded dynamically on a running RomWBW CP/M-like system. Normally, you would
boot CP/M and then load the desired variant. On a running system, you would enter
something like "LDSYS BP34T". This document describes the specifics of the build
something like "LDSYS BP34". This document describes the specifics of the build
process and the image variations which are identified by naming convention.
Each image is composed of three basic components: Command Processor (CCP), Disk
@@ -36,62 +36,57 @@ ZCPR 4.X == ZSDOS 2.X
BPBIOS must be assembled for the target configuration. BPBIOS includes a DEF-WW-???????.LIB
file during assembly which sets various equates to contol the features and behavior of
BPBIOS. The most critical ones are:
BPBIOS. The relevant settings are:
BANKED: If YES, BPBIOS implements memory banking features
ZSDOS2: If YES, BPBIOS is built to utilize ZSDOS 2.X specifics features
INTPXY: If YES, BPBIOS implements HBIOS proxy code internally w/ stub at FFE0H-FFFFH
The table below illustrates the target build configurations along with the
.DAT and .LIB files which are utilized for the specific configuration. The "?"
is replaced with a letter that represents one of the ZCPR memory segment configurations
described later in this document.
BP33?.DAT DEF-WW-Z33?.LIB Non-Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
BP33?BNK.DAT DEF-WW-Z33?BNK.LIB Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
BP34?.DAT DEF-WW-Z34?.LIB Non-Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
BP34?BNK.DAT DEF-WW-Z34?BNK.LIB Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
BP41?BNK.DAT DEF-WW-Z41?BNK.LIB Banked BPBIOS w/ ZCPR 4.1 & ZSDOS 2.03
BP33.DAT DEF-WW-Z33.LIB Non-Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
BP33BNK.DAT DEF-WW-Z33BNK.LIB Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
BP34.DAT DEF-WW-Z34.LIB Non-Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
BP34BNK.DAT DEF-WW-Z34BNK.LIB Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
BP41BNK.DAT DEF-WW-Z41BNK.LIB Banked BPBIOS w/ ZCPR 4.1 & ZSDOS 2.X
The table below illustrates the BPBIOS equates used and the specific CCP/DOS/BIOS
components that are used to generate each configuration. As above, the "?" is
replaced with a letter that represents one of the ZCPR memory segment configurations
described later in this document.
BP33? BP33?BNK BP34? BP34?BNK BP41?BNK
BP33 BP33BNK BP34 BP34BNK BP41BNK
-------------- -------------- -------------- -------------- -------------- --------------
BANKED NO YES NO YES YES
ZSDOS2 NO NO NO NO YES
-------------- -------------- -------------- -------------- -------------- --------------
CCP ZCPR33?.REL ZCPR33?.REL Z34.REL Z34.REL Z41.ZRL
DOS ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZS203.ZRL
BIOS BP33?.REL BP33?BNK.REL BP34?.REL BP34?BNK.REL BP41?BNK.REL
CCP ZCPR33.REL ZCPR33.REL Z34.REL Z34.REL Z41.ZRL
DOS ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZS227G.ZRL
BIOS BP33.REL BP33BNK.REL BP34.REL BP34BNK.REL BP41BNK.REL
-------------- -------------- -------------- -------------- -------------- --------------
In addition to the configuration options above, ZCPR also utilizes a
defined set of memory segments in upper memory. The location and size of these
segments have many ramifications and general ZCPR / BPBIOS documents
should be consulted to understand these. The build process used here
produces several different configurations which can be loaded at runtime.
The original distributed memory segment configuration occupies the top
of memory which, unfortunately, conflicts with the RomWBW HBIOS need to
occupy this space.
In addition to the configuration options above, ZCPR also utilizes a
defined set of memory segments in upper memory. The location and
size of these segments have many ramifications and general ZCPR /
BPBIOS documents should be consulted to understand these. The build
process used here produces a custom configuration appropriate for
RomWBW. The original distributed memory segment configuration occupies
the top of memory which, unfortunately, conflicts with the RomWBW
HBIOS need to occupy this space.
Although RomWBW HBIOS is implemented in it's own dedicated memory bank, it
requires a small proxy at the top of memory which acts as a mechansim to
route calls to HBIOS. There are two ways to implement this upper memory
proxy. The full proxy occupies FE00H-FFFFH and implements all of the
HBIOS routing code. Alternatively, a mini proxy can be utilized to
minimize the dedicated proxy space in upper memory. The mini proxy
requires just 20H bytes at the top of memory (FFE0H-FFFFH), but requires
that the remainder of the proxy code be implemented internally in BPBIOS.
Although RomWBW HBIOS is implemented in it's own dedicated memory
bank, it requires a small proxy at the top of memory which acts as a
mechansim to route calls to HBIOS. The proxy occupies FE00H-FFFFH and
implements all of the HBIOS routing code.
Taking the above into account, the build process implements a couple of
memory segment configurations that are compatible with RomWBW HBIOS.
Essentially, these configurations rearrange the ZCPR memory segments
to free up the area required by the HBIOS full or mini proxy. Note
that this is a bit complicated because there are some constraints on
the locations of certain segments.
Taking the above into account, the build process implements a memory
segment configuration that is compatible with RomWBW HBIOS.
Essentially, this configuration rearranges the ZCPR memory segments to
free up the area required by the HBIOS proxy. Note that this is a bit
complicated because there are some constraints on the locations of
certain segments.
BPBIOS is assembled as relocatable code. Subsequently, the BPBUILD tool
is used to link BPBIOS with the CCP and DOS relocatable code to produce
@@ -101,38 +96,38 @@ segment to customize the final image for the desired location and size
of Z-System segments.
The following table summarizes the original memory segment configuration and the
two new configurations utilized by this build process. As indicated above, the
new configuration utilized by this build process. As indicated above, the
original configuration is incompatible with RomWBW HBIOS because it occupies the
very top of memory. The original configuration is shown below purely to
document the original distributed configuration.
SEGMENT Original T Config N Config
-------------- -------------- -------------- --------------
Environment FE00 FC00 FC00
# Recs 2 2 2
Flow Ctl Pkg FA00 F700 F900
# Recs 4 4 4
I/O Pkg EC00 EF00 F100
# Recs 12 0 0
Res Cmd Pkg F200 EF00 F100
# Recs 16 16 16
Cmd Line FF00 FD00* FD00
# Bytes 203 251 251
Named Dirs FC00 F900 FE00
# Ents 14 25 25
Ext Path FDF4 FBF4 FBF4
# Ents 5 5 5
Shell Stack FD00 FB00 FB00
# Ents 4 4 4
Ent Size 32 32 32
Msg Buffer FD80 FB80 FB80
Ext FCB FDD0 FBD0 FBD0
Ext Stack FFD0 FAD0 FFB0
SEGMENT Original RomWBW Config
-------------- -------------- --------------
Environment FE00 FC00
# Recs 2 2
Flow Ctl Pkg FA00 F700
# Recs 4 4
I/O Pkg EC00 EF00
# Recs 12 0
Res Cmd Pkg F200 EF00
# Recs 16 16
Cmd Line FF00 FD00
# Bytes 203 251
Named Dirs FC00 F900
# Ents 14 25
Ext Path FDF4 FBF4
# Ents 5 5
Shell Stack FD00 FB00
# Ents 4 4
Ent Size 32 32
Msg Buffer FD80 FB80
Ext FCB FDD0 FBD0
Ext Stack FFD0 FAD0
User Space E900 EC00* EE00
Size 300 300 300
User Space E900 EC00
Size 300 300
Wheel Byte FDFF FBFF FDFF
Wheel Byte FDFF FBFF
The sections below provide a more detailed description of the memory
segment configurations.
@@ -158,7 +153,7 @@ ORIGINAL DISTRIBUTION CONFIGURATION (NO HBIOS):
=============================================================================
=============================================================================
T CONFIGURATION (HBIOS FULL PROXY @ FC00-FFFF):
ROMWBW CONFIGURATION (HBIOS PROXY @ FE00-FFFF):
-----------------------------------------------------------------------------
A - Environment - FC00H F - Named Dirs - F900H
Size (# recs)- 2 # of Entries - 25
@@ -172,21 +167,6 @@ T CONFIGURATION (HBIOS FULL PROXY @ FC00-FFFF):
Size (bytes) - 251 K - Ext. Stack - FAD0H
=============================================================================
=============================================================================
N CONFIGURATION (HBIOS MINI PROXY @ FFE0-FFFF):
-----------------------------------------------------------------------------
A - Environment - FC00H F - Named Dirs - FE00H
Size (# recs)- 2 # of Entries - 24
B - Flow Ctrl Pkg - F900H G - External Path - FBF4H
Size (# recs)- 4 # of Entries - 5
C - I/O Package - F100H H - Shell Stack - FB00H
Size (# recs)- 0 # of Entries - 4
D - Res Cmd Proc - F100H Entry Size - 32
Size (# recs)- 16 I - Msg Buffer - FB80H
E - Command Line - FD00H J - Ext. FCB - FBD0H
Size (bytes) - 251 K - Ext. Stack - FFB0H
=============================================================================
BPBIOS is designed to invoke a command at startup (autostart command). There
are 3 ZEX command files customized for this build. They are ZSTT.ZEX, ZSTN.ZEX,
and ZSTF.ZEX. BPBIOS is customized to launch the ZEX command file corresponding
@@ -197,27 +177,10 @@ process:
ZCPR ZSDOS BPBIOS STARTUP HBIOS PROXY IMAGE
------ ------ -------------- -------------- -------------- --------------
v3.3 v1.1 NON-BANKED ZSTT.ZEX EXTERNAL BP33T.IMG
v3.3 v1.1 BANKED ZSTT.ZEX EXTERNAL BP33TBNK.IMG
v3.3 v1.1 NON-BANKED ZSTN.ZEX INTERNAL BP33N.IMG
v3.3 v1.1 BANKED ZSTN.ZEX INTERNAL BP33NBNK.IMG
v3.4 v1.1 NON-BANKED ZSTT.ZEX EXTERNAL BP34T.IMG
v3.4 v1.1 BANKED ZSTT.ZEX EXTERNAL BP34TBNK.IMG
v3.4 v1.1 NON-BANKED ZSTN.ZEX INTERNAL BP34N.IMG
v3.4 v1.1 BANKED ZSTN.ZEX INTERNAL BP34NBNK.IMG
v4.1 v2.03 BANKED ZSTF.ZEX EXTERNAL BP41TBNK.IMG
v4.1 v2.03 BANKED ZSTF.ZEX INTERNAL BP41NBNK.IMG
v3.3 v1.1 NON-BANKED ZST.ZEX EXTERNAL BP33.IMG
v3.3 v1.1 BANKED ZST.ZEX EXTERNAL BP33BNK.IMG
v3.4 v1.1 NON-BANKED ZST.ZEX EXTERNAL BP34.IMG
v3.4 v1.1 BANKED ZST.ZEX EXTERNAL BP34BNK.IMG
v4.1 v2.03 BANKED ZSTF.ZEX EXTERNAL BP41BNK.IMG
WARNING: Once an N configuration image has been loaded, it is no longer
possible to load a T configuration without rebooting. This constraint
exists because the N configurations wipes out all but the top 20H bytes
of memory. The T configurations rely on the full 200H byte HBIOS
proxy.
WARNING: The N configurations *cannot* handle interrupts because the
RomWBW interrupt procesing framework exists in the RAM area FE00-FFFF
which is mostly overlaid by the N configurations. Use of the T
configuration is strongly recommended even though it leaves slightly
less TPA available for applications.
--WBW 7:32 PM 10/3/2021
--WBW 1:34 PM 10/7/2021

18
Source/BPBIOS/Build.cmd
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@@ -9,19 +9,11 @@ set ZXBINDIR=../../tools/cpm/bin/
set ZXLIBDIR=../../tools/cpm/lib/
set ZXINCDIR=../../tools/cpm/include/
call :makebp 33t
call :makebp 33tbnk
call :makebp 33n
call :makebp 33nbnk
call :makebp 34t
call :makebp 34tbnk
call :makebp 34n
call :makebp 34nbnk
call :makebp 41tbnk
call :makebp 41nbnk
call :makebp 33
call :makebp 33bnk
call :makebp 34
call :makebp 34bnk
call :makebp 41bnk
rem pause

2
Source/BPBIOS/ZCPR33/@WBW.txt
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@@ -2,7 +2,5 @@ This directory contains the official ZCPR 3.3 source with minor customizations
to support the BPBIOS build in the parent directory:
- Modified to produce a relocatable image compatibile with BPBUILD
- Build process (Build.cmd) creates ZCPR33T.REL and ZCPR33N.REL based
on Z3BASET.LIB and B3BASEN.LIB from parent directory.
See "@WBW Z3ENV.txt" file in parent directory for more information.

13
Source/BPBIOS/ZCPR33/Build.cmd
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@@ -7,12 +7,7 @@ set ZXBINDIR=../../../tools/cpm/bin/
set ZXLIBDIR=../../../tools/cpm/lib/
set ZXINCDIR=../../../tools/cpm/include/
copy ..\z3baset.lib . || exit /b
zx ZMAC -zcpr33t.z80 -/P || exit /b
del z3baset.lib || exit /b
move zcpr33t.rel .. || exit /b
copy ..\z3basen.lib . || exit /b
zx ZMAC -zcpr33n.z80 -/P || exit /b
del z3basen.lib || exit /b
move zcpr33n.rel .. || exit /b
copy ..\z3base.lib . || exit /b
zx ZMAC -zcpr33.z80 -/P || exit /b
del z3base.lib || exit /b
move zcpr33.rel .. || exit /b

226
Source/BPBIOS/ZCPR33/z3base.lib
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@@ -1,226 +0,0 @@
; Z3BASE - Dynamic Configuration
;
; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user
; distribution and duplication permitted for non-commercial purposes only.
; Any commercial use of ZCPR33, defined as any situation where the duplicator
; recieves revenue by duplicating or distributing ZCPR33 by itself or in
; conjunction with any hardware or software product, is expressly prohibited
; unless authorized in writing by Echelon.
;
; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE
; for Z-Com. All segment addresses are automatically derived when the
; CCP equate is set. The benefit of this is that reconfiguration of the
; system after initial installation is greatly eased.
;
; Although this version of Z3BASE is being distributed with ZCPR 3.3, any
; previous version of Z3BASE can be used to assemble the Z33 Command
; Processor. No new symbols are needed. So, if you have an existing
; Z3BASE, go ahead and use it.
;
; Instructions:
;
; The user should first design the ZCPR3 memory usage using the chart
; below. (Echelon recommends the chart be filled out, even though it is
; not read by the assembler, so that your system will be self-documenting.)
; Then set the CCP equate for the beginning address of ZCPR3. Next, examine
; and change the SEGn equates which follow in the file to ensure that the
; system segments and buffers are placed at the proper addresses.
;
; This file has been customized for use with AMPRO hard disk systems. The
; target configuration has support for hard disks up to 49 Meg, extended
; IOP support, and 28-entry NDR.
;
;****************************************************************
;* *
;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System *
;* *
;* Segments: *
;* *
;* Segment Function *
;* ------- -------- *
;* ZRDOS Echelon Z80 Replacement Disk Operating *
;* System, Version 1.7 (Public ZRDOS Plus) *
;* CBIOSZ Ampro-compatible BIOS with additional *
;* ZCPR3 initialization routines *
;* ZCPR3 Echelon Z80 Command Processor *
;* Replacement, Version 3.3 (ZCPR3) *
;* *.ENV All Environment Descriptors *
;* *.FCP All Flow Command Packages *
;* *.NDR All Named Directory Definition Files *
;* *.RCP All Resident Command Packages *
;* *.IOP All Input/Output Packages *
;* *
;* *
;* Memory Map of System (for CCP EQU 0BC00H): *
;* *
;* Address Range Size Function *
;* ------------- ------- -------- *
;* 0 - FF 256 b Standard CP/M Buffers except *
;* 100 - C3FF ~49 K Transient Program Area *
;* BC00 - C3FF 2K ZCPR 3.3 Command Processor *
;* C400 - D1FF 3.5 K ZRDOS *
;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers *
;* EB00 - F2FF 2 K Resident Command Package *
;* F300 - F8FF 1.5 K Input/Output Package *
;* F900 - FAFF .5 K Flow Command Package *
;* FB00 - FB7F 128 b ZCPR3 Shell Stack *
;* FB80 - FBCF 80 b ZCPR3 Message Buffers *
;* FBD0 - FBF3 36 b ZCPR3 External FCB *
;* FBF4 - FBFE 11 b ZCPR3 External Path *
;* FBFF 1 b Wheel Byte *
;* FC00 - FDFF .5 K Memory-Based Named Directory *
;* FE00 - FEFF 256 b Environment Descriptor *
;* Bytes 00H-7FH: Z3 Parameters *
;* Bytes 80H-FFH: Z3 TCAP *
;* FF00 - FFCF 208 B Multiple Command Line Buffer *
;* FD00 - FFFF 48 b ZCPR3 External Stack *
;****************************************************************
FALSE equ 0
TRUE equ NOT FALSE
Z3REV EQU 33 ; ZCPR3 REV NUMBER
MSIZE EQU 54 ; SIZE OF CPM SYSTEM
BASE EQU 0
CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR
seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR,
; 3.5k DOS, and 6.25k BIOS).
;
; RCP definition. Set RCPS to 0 to eliminate RCP
;
RCPS EQU 16 ; 16 128-byte Blocks (2K bytes)
IF RCPS NE 0
RCP EQU seg1 ; RESIDENT COMMAND PACKAGE
ELSE
RCP EQU 0
ENDIF
seg2 equ seg1+[rcps*128]
;
; IOP definition. Set IOPS to 0 to eliminate IOP
;
IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes)
IF IOPS NE 0
IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE
ELSE
IOP EQU 0
ENDIF
seg3 equ seg2+[iops*128]
;
; FCP definition. Set FCPS to 0 to eliminate FCP
;
FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes)
IF FCPS NE 0
fcp equ seg3
ELSE
fcp equ 0
ENDIF
seg4 equ seg3+[fcps*128]
;
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
;
SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES
SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY
; (STACK SIZE = SHSTKS * SHSIZE)
IF SHSTKS NE 0
SHSTK EQU seg4
ELSE
SHSTK EQU 0
ENDIF
seg5 equ seg4+[shstks*shsize]
;
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
;
Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER
seg6 equ seg5+80
;
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
;
EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB
seg7 equ seg6+36
;
; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be
; used with this Z3BASE.LIB file.
;
EXPATH EQU seg7 ; EXTERNAL PATH
EXPATHS EQU 5 ; 5 2-byte Path Elements
; (PATH SIZE = EXPATHS*2 + 1)
seg8 equ seg7+[expaths*2]+1
;
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
;
Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS
seg9 equ seg8+1
;
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
; the named directory buffer. If Z3NDIRS is changed, also change the seg10
; equate below.
;
Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted
; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0)
IF Z3NDIRS NE 0
Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA
ELSE
Z3NDIR EQU 0
ENDIF
seg10 equ seg9+512 ; add 512 for 28-entry NDR
; add 256 for 14-entry NDR ("standard")
; add 0 if Z3NDIRS is set to 0
;
; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3.
; Echelon recommends you work this out so that your ENV begins at address
; FE00h, but this is only a recommendation and not mandatory.
;
Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS
Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS
seg11 equ seg10+[z3envs*128]
;
; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3.
;
Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER
Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER
seg12 equ seg11+z3cls
;
; The ZCPR3 External Stack is mandatory for ZCPR 3.3.
;
EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK
; end of Z3BASE.LIB


9
Source/BPBIOS/ZCPR33/zcpr33.z80
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@@ -78,6 +78,9 @@
; which are used to customize ZCPR33 for the user's working environment.
; NOTE -- TRUE & FALSE are defined in Z3BASE.
memtop equ 0FE00H - 1 ; Reserve memory above this for HBIOS
base equ 0
maclib z3base.lib
maclib z33hdr.lib
@@ -137,7 +140,7 @@ tfcb equ base+005ch ; Default FCB buffer
tfcb2 equ tfcb+16 ; 2nd FCB
tbuff equ base+0080h ; Default disk I/O buffer
tpa equ base+0100h ; Base of TPA
bios equ ccp+0800h+0e00h ; BIOS location
;bios equ ccp+0800h+0e00h ; BIOS location
; ---------- Error codes
@@ -262,6 +265,10 @@ curdr equ z3msg+2fh ; Currently logged drive
if not rel ; If generating absolute code
org ccp
else
common /_BIOS_/
bios equ $
cseg
endif ;not rel

4045
Source/BPBIOS/ZCPR33/zcpr33n.z80
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4045
Source/BPBIOS/ZCPR33/zcpr33t.z80
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Source/BPBIOS/bp34t.dat → Source/BPBIOS/bp34.dat
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21
Source/BPBIOS/bpbio-ww.z80
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@@ -80,14 +80,15 @@ FALSE EQU 0
TRUE EQU NOT FALSE
NO EQU FALSE
YES EQU TRUE
; << ****** SYSTEM SPECIFIC ****** >>
; << Insert DEF-xxxx.LIB definition >>
INCLUDE DEF-WW.LIB ; << file for your configuration. >>
; << ****** SYSTEM SPECIFIC ****** >>
; << Insert ROMWBW definitions here >>
INCLUDE ROMWBW.LIB ; << for version # in ROM >>
; << ****** SYSTEM SPECIFIC ****** >>
; << Insert DEF-xxxx.LIB definition >>
INCLUDE DEF-WW.LIB ; << file for your configuration. >>
CSEG
;.....
; Ascii Character Equates
@@ -109,18 +110,10 @@ LOCKF EQU LOW [NOT AUTOSL] ;Lock flag for format default
ALONE EQU FALSE ; Boot code equate
; Include ENV definitions
IF Z3
IF INTPXY
IF ZSDOS2
MACLIB Z3BASEFN.LIB
ELSE
MACLIB Z3BASEN.LIB
ENDIF
IF ZSDOS2
MACLIB Z3BASEF.LIB
ELSE
IF ZSDOS2
MACLIB Z3BASEFT.LIB
ELSE
MACLIB Z3BASET.LIB
ENDIF
MACLIB Z3BASE.LIB
ENDIF
ENDIF
PAGE

34
Source/BPBIOS/cboot-ww.z80
View File

@@ -28,11 +28,13 @@
CBOOT:
DI ; Disable interrupt system
IF BANKED
LD SP,USP ; Set to User Stack in High memory
ELSE
LD SP,80H ; Set stack in Low memory
ENDIF ; BANKED
CALL HBX_INIT
LD HL,(IOBYT) ; Get IOBYTE, Default Drive & User
@@ -275,7 +277,7 @@ BLKMV: POP BC ; And number of bytes to move
; Allocate disk buffer in HBIOS bank and
; save it for use later in disk access.
LD B,H_ALLOC ; HBIOS Func: ALLOCATE Heap Memory
LD B,HBF_ALLOC ; HBIOS Func: ALLOCATE Heap Memory
LD HL,512 ; 1 Sector, 512 Bytes
CALL HBX_INVOKE ; Do it
CALL NZ,PANIC ; Handle error
@@ -313,21 +315,21 @@ MEMOK:
DEFB CR,LF,'RetroB' ; Save all bytes possible
ELSE ; Otherwise sign on with complete name
DEFB CR,LF,'Retro-Brew '
IF SBC
DEFB ' SBC V1/2 '
ENDIF ;SBC
IF SIMH
DEFB 'ON SimH '
ENDIF ;SIMH
IF ZETA
DEFB ' ZETA '
ENDIF ;ZETA
IF N8
DEFB ' N8 '
ENDIF ;N8
IF MK4
DEFB ' Mark IV '
ENDIF ;MK4
; IF SBC
; DEFB ' SBC V1/2 '
; ENDIF ;SBC
; IF SIMH
; DEFB 'ON SimH '
; ENDIF ;SIMH
; IF ZETA
; DEFB ' ZETA '
; ENDIF ;ZETA
; IF N8
; DEFB ' N8 '
; ENDIF ;N8
; IF MK4
; DEFB ' Mark IV '
; ENDIF ;MK4
ENDIF ; MOVCPM
DEFB 'B/P 50.00k Bios' ;**** Do NOT alter this string ****

3
Source/BPBIOS/deblock.z80
View File

@@ -268,7 +268,8 @@ MATCH: LD A,(SECMSK) ; Get the sector mask
;
; Modified to use HBIOS host buffer
;
LD A,BID_HB ; HSTBUF is in HBIOS
;LD A,BID_HB ; HSTBUF is in HBIOS
LD A,(HBX_BNKBIOS) ; HSTBUF is in HBIOS
LD C,A
IF BANKED
LD A,(DMABNK) ; Set Read Destination Bank

33
Source/BPBIOS/def-ww-z33t.lib → Source/BPBIOS/def-ww-z33.lib
View File

@@ -16,15 +16,15 @@
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
DEFB '07 Oct 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTT',0 ; Autostart command line
DEFB 8,'ZEX ZST ',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
@@ -38,20 +38,6 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU NO ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
@@ -139,21 +125,16 @@ NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
;
; RomWBW HBIOS sets these values at runtime during startup.
;
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK1 EQU BID_COM ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general

33
Source/BPBIOS/def-ww-z33tbnk.lib → Source/BPBIOS/def-ww-z33bnk.lib
View File

@@ -16,15 +16,15 @@
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 AUG 21' ; Date of this version
DEFB '07 Oct 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTT',0 ; Autostart command line
DEFB 8,'ZEX ZST ',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
@@ -38,20 +38,6 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU NO ; YES to use internal HBIOS Mini proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; Use internal Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; mini-proxy (32 bytes)
ELSE
; Use external HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
@@ -139,21 +125,16 @@ NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
;
; RomWBW HBIOS sets these values at runtime during startup.
;
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK1 EQU BID_COM ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general

384
Source/BPBIOS/def-ww-z33n.lib
View File

@@ -1,384 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew boards /w RomWBW HBIOS - **********************
; Setup for a Non-banked, internal HBIOS proxy System
; Custom tailor your system here.
;
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN
; 17 Jan 14 - Initial N8VEM release WW+LN
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTN',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU NO ; Is this a banked BIOS?
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
CLKSET EQU YES ; Allow Clock Sets? (Error if No)
;--- Floppy Diskette Section ---
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;;--- RAM Disk Section ---
;
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
;
; Set each of these equates for the drive and partition complement of
; your system. Set equates to no if drive exists or is wanted.
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0.
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1.
DRV_C EQU yes
DRV_D EQU yes
DRV_E EQU yes ; Default is C-J are Hard Disk Slices
DRV_F EQU yes ; on the first hard drive (room for
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card.
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes ; Default is K-N are Hard Disk Slices
DRV_L EQU yes ; on a second hard drive (room for up to
DRV_M EQU yes ; 4 Slices provided) e.g. SD card
DRV_N EQU yes
if FLPYDSK
DRV_O EQU yes ; O & P are floppies
DRV_P EQU yes
else
DRV_O EQU no ; O & P are floppies
DRV_P EQU no
endif
;========== Configuration Unique Equates ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================
ENDIF ; REMOVE CODE

383
Source/BPBIOS/def-ww-z33nbnk.lib
View File

@@ -1,383 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew boards /w RomWBW HBIOS - **********************
; Setup for banked bios & internal HBIOS proxy System
; Custom tailor your system here.
;
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN
; 17 Jan 14 - Initial N8VEM release WW+LN
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTN',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU YES ; Is this a banked BIOS?
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; YES to use internal HBIOS Mini proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
CLKSET EQU YES ; Allow Clock Sets? (Error if No)
;--- Floppy Diskette Section ---
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;;--- RAM Disk Section ---
;
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
;
; Set each of these equates for the drive and partition complement of
; your system. Set equates to no if drive exists or is wanted.
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0.
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1.
DRV_C EQU yes
DRV_D EQU yes
DRV_E EQU yes ; Default is C-J are Hard Disk Slices
DRV_F EQU yes ; on the first hard drive (room for
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card.
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes ; Default is K-N are Hard Disk Slices
DRV_L EQU yes ; on a second hard drive (room for up to
DRV_M EQU yes ; 4 Slices provided) e.g. SD card
DRV_N EQU yes
if FLPYDSK
DRV_O EQU yes ; O & P are floppies
DRV_P EQU yes
else
DRV_O EQU no ; O & P are floppies
DRV_P EQU no
endif
;========== Configuration Unique Equates ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================
ENDIF ; REMOVE CODE

33
Source/BPBIOS/def-ww-z34t.lib → Source/BPBIOS/def-ww-z34.lib
View File

@@ -16,15 +16,15 @@
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
DEFB '07 Oct 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTT',0 ; Autostart command line
DEFB 8,'ZEX ZST ',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
@@ -38,20 +38,6 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU NO ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
@@ -139,21 +125,16 @@ NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
;
; RomWBW HBIOS sets these values at runtime during startup.
;
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK1 EQU BID_COM ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general

33
Source/BPBIOS/def-ww-z34tbnk.lib → Source/BPBIOS/def-ww-z34bnk.lib
View File

@@ -16,15 +16,15 @@
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 AUG 21' ; Date of this version
DEFB '07 Oct 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTT',0 ; Autostart command line
DEFB 8,'ZEX ZST ',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
@@ -38,20 +38,6 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU NO ; YES to use internal HBIOS Mini proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; Use internal Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; mini-proxy (32 bytes)
ELSE
; Use external HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
@@ -139,21 +125,16 @@ NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
;
; RomWBW HBIOS sets these values at runtime during startup.
;
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK1 EQU BID_COM ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general

384
Source/BPBIOS/def-ww-z34n.lib
View File

@@ -1,384 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew boards /w RomWBW HBIOS - **********************
; Setup for a Non-banked, internal HBIOS proxy System
; Custom tailor your system here.
;
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN
; 17 Jan 14 - Initial N8VEM release WW+LN
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTN',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU NO ; Is this a banked BIOS?
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
CLKSET EQU YES ; Allow Clock Sets? (Error if No)
;--- Floppy Diskette Section ---
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;;--- RAM Disk Section ---
;
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
;
; Set each of these equates for the drive and partition complement of
; your system. Set equates to no if drive exists or is wanted.
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0.
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1.
DRV_C EQU yes
DRV_D EQU yes
DRV_E EQU yes ; Default is C-J are Hard Disk Slices
DRV_F EQU yes ; on the first hard drive (room for
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card.
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes ; Default is K-N are Hard Disk Slices
DRV_L EQU yes ; on a second hard drive (room for up to
DRV_M EQU yes ; 4 Slices provided) e.g. SD card
DRV_N EQU yes
if FLPYDSK
DRV_O EQU yes ; O & P are floppies
DRV_P EQU yes
else
DRV_O EQU no ; O & P are floppies
DRV_P EQU no
endif
;========== Configuration Unique Equates ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================
ENDIF ; REMOVE CODE

383
Source/BPBIOS/def-ww-z34nbnk.lib
View File

@@ -1,383 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew boards /w RomWBW HBIOS - **********************
; Setup for banked bios & internal HBIOS proxy System
; Custom tailor your system here.
;
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN
; 17 Jan 14 - Initial N8VEM release WW+LN
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTN',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU YES ; Is this a banked BIOS?
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; YES to use internal HBIOS Mini proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
CLKSET EQU YES ; Allow Clock Sets? (Error if No)
;--- Floppy Diskette Section ---
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;;--- RAM Disk Section ---
;
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
;
; Set each of these equates for the drive and partition complement of
; your system. Set equates to no if drive exists or is wanted.
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0.
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1.
DRV_C EQU yes
DRV_D EQU yes
DRV_E EQU yes ; Default is C-J are Hard Disk Slices
DRV_F EQU yes ; on the first hard drive (room for
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card.
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes ; Default is K-N are Hard Disk Slices
DRV_L EQU yes ; on a second hard drive (room for up to
DRV_M EQU yes ; 4 Slices provided) e.g. SD card
DRV_N EQU yes
if FLPYDSK
DRV_O EQU yes ; O & P are floppies
DRV_P EQU yes
else
DRV_O EQU no ; O & P are floppies
DRV_P EQU no
endif
;========== Configuration Unique Equates ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================
ENDIF ; REMOVE CODE

31
Source/BPBIOS/def-ww-z41tbnk.lib → Source/BPBIOS/def-ww-z41bnk.lib
View File

@@ -16,7 +16,7 @@
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
DEFB '07 Oct 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTF',0 ; Autostart command line
@@ -24,7 +24,7 @@ AUTOCL MACRO
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
MOVCPM EQU NO ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
@@ -38,20 +38,6 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU NO ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
@@ -139,21 +125,16 @@ NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
;
; RomWBW HBIOS sets these values at runtime during startup.
;
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK1 EQU BID_COM ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general

385
Source/BPBIOS/def-ww-z41nbnk.lib
View File

@@ -1,385 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew boards /w RomWBW HBIOS - **********************
; Tailored for a Fully-banked, internal HBIOS proxy System
; Custom tailor your system here.
;
; 02 May 18 - changes made to conform with HBIOS v 2.9.1p2 WW+LN
; 04 Sep 16 - Mods for RomWBW V 2.8 WW+LN
; 30 Apr 15 - changes made to conform with v 2.7.2 of RomWBW WW+LN
; 17 Jan 14 - Initial N8VEM release WW+LN
; 30 Aug 01 - Cleaned up for GPL release. HFB
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
; 5 Jan 97 - Reformatted to Standard. HFB
; 10 Jun 96 - Initial Test Release. HFB
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
DATE MACRO
DEFB '02 Aug 21' ; Date of this version
ENDM
AUTOCL MACRO
DEFB 8,'ZEX ZSTF',0 ; Autostart command line
ENDM
;--- Basic System and Z-System Section ---
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
IF MOVCPM
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
ELSE
VERS EQU 21H ; Version number w/Device Swapping permitted
ENDIF
BANKED EQU YES ; Is this a banked BIOS?
ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible
INROM EQU NO ; Alternate bank in ROM?
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
; ..No if restoring from Drive A
Z3 EQU YES ; Include ZCPR init code?
HAVIOP EQU NO ; Include IOP code into Jump table?
INTPXY EQU YES ; YES to use internal HBIOS proxy
; and load Proxy as part of BPBIOS.
; NO to use HBIOS Proxy in high RAM
; (already loaded)
IF INTPXY
; YES load Proxy as part of BPBIOS.
MEMTOP EQU 0FFE0H - 1 ; Reserve memory above this for HBIOS
; interface (32 bytes)
ELSE
; NO use HBIOS Proxy in high RAM
; (already loaded)
HBLOC EQU 0FE00H ; Location of HBIOS proxy (if used)
MEMTOP EQU HBLOC - 1 ; Reserve memory above this for HBIOS
ENDIF
;--- Memory configuration Section --- (Expansion Memory configured here)
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
; No = Include Common RAM transfer buffer
;--- Character Device Section ---
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
; NO = Only use the 4 defined Char Devices
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
; ..must be 2^n with n<8
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
;--- Clock and Time Section ---
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
CLKSET EQU YES ; Allow Clock Sets? (Error if No)
;--- Floppy Diskette Section ---
FLPYDSK EQU NO ; YES = Make Floppy-Disk Code, NO = No code made
BIOERM EQU yes ; Print BIOS error messages?
CALCSK EQU YES ; Calculate skew table?
AUTOSL EQU YES ; Auto select floppy formats?
; If AUTOSL=True, the next two are active...
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
FLOPY8 EQU no ; Include 8" Floppy Formats?
MORDPB EQU NO ; Include additional Floppy DPB Formats?
;;--- RAM Disk Section ---
;
;RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
;
;--- Hard Disk Section ---
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
; (Pick 1 of 3 options below)
HBDSK EQU YES ; YES = Use HBIOS Disk Driver
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
; (DMA not implemented for GIDE)
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
;--- Logical Drive Section ---
;
; Set each of these equates for the drive and partition complement of
; your system. Set equates to no if drive exists or is wanted.
DRV_A EQU yes ; A is always RAMDSK on HBIOS Device 0.
DRV_B EQU yes ; B is always ROMDSK on HBIOS Device 1.
DRV_C EQU yes
DRV_D EQU yes
DRV_E EQU yes ; Default is C-J are Hard Disk Slices
DRV_F EQU yes ; on the first hard drive (room for
DRV_G EQU yes ; up to 8 Slices provided) e.g. CF card.
DRV_H EQU yes
DRV_I EQU yes
DRV_J EQU yes
DRV_K EQU yes ; Default is K-N are Hard Disk Slices
DRV_L EQU yes ; on a second hard drive (room for up to
DRV_M EQU yes ; 4 Slices provided) e.g. SD card
DRV_N EQU yes
if FLPYDSK
DRV_O EQU yes ; O & P are floppies
DRV_P EQU yes
else
DRV_O EQU no ; O & P are floppies
DRV_P EQU no
endif
;========== Configuration Unique Equates ===========
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
; systems with dynamic RAMs.
NOWAIT EQU NO ; Set to NO to use configured Wait States in
; Hard Disk Driver. Yes to eliminate Waits.
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
; memory in 32k increments. In SBC V1&2, Zeta and Simh, RAM occupies the
; first 512k (16 32k banks). The upper 32k bank is fixed as the last 32k
; of 512k. HBIOS occupies bank 1. The upper
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
BNKU EQU 00H ; User Area Bank 58000H
; (set to 0 to disable)
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
; With both on-board RAMs only (MEM1 or MEM2),
; the maximum Bank number is 11 (0BH).
IF NO ; REMOVE CODE - NOT NEEDED WITH HBIOS makes a
; nice resource for Z180 programing in general
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
CNTLA0 EQU 00H ; Control Port ASCI 0
CNTLA1 EQU 01H ; Control Port ASCI 1
STAT0 EQU 04H ; Serial port 0 Status
STAT1 EQU 05H ; Serial port 1 Status
TDR0 EQU 06H ; Serial port 0 Output Data
TDR1 EQU 07H ; Serial port 1 Output Data
RDR0 EQU 08H ; Serial port 0 Input Data
RDR1 EQU 09H ; Serial Port 1 Input Data
CNTR EQU 0AH ; HD64180 Counter port
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
RLDR0H EQU 0FH ; CTC0 Reload Count, High
TCR EQU 10H ; Interrupt Control Register
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
FRC EQU 18H ; Free-Running Counter
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
DSTAT EQU 30H ; DMA Status/Control port
DMODE EQU 31H ; DMA Mode Control port
DCNTL EQU 32H ; DMA/WAIT Control Register
IL EQU 33H ; Interrupt Segment Register
ITC EQU 34H ; Interrupt/Trap Control Register
RCR EQU 36H ; HD64180 Refresh Control register
CBR EQU 38H ; MMU Common Base Register
BBR EQU 39H ; MMU Bank Base Register
CBAR EQU 3AH ; MMU Common/Bank Area Register
OMCR EQU 3EH ; Operation Mode Control Reg
ICR EQU 3FH ; I/O Control Register
; Some bit definitions used with the Z-180 on-chip peripherals:
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
RDRF EQU 80H ; ACSI Received Character available
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Extended Features of Z80182 for P112
WSGCS EQU 0D8H ; Wait-State Generator CS
ENH182 EQU 0D9H ; Z80182 Enhancements Register
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
RAMUBR EQU 0E6H ; RAM End Boundary
RAMLBR EQU 0E7H ; RAM Start Boundary
ROMBR EQU 0E8H ; ROM Boundary
FIFOCTL EQU 0E9H ; FIFO Control Register
RTOTC EQU 0EAH ; RX Time-Out Time Constant
TTOTC EQU 0EBH ; TX Time-Out Time Constant
FCR EQU 0ECH ; FIFO Register
SCR EQU 0EFH ; System Pin Control
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
THR EQU 0F0H ; MIMIN TX Holding Register (W)
IER EQU 0F1H ; Interrupt Enable Register
LCR EQU 0F3H ; Line Control Register
MCR EQU 0F4H ; Modem Control Register
LSR EQU 0F5H ; Line Status Register
MDMSR EQU 0F6H ; Modem Status Register
MSCR EQU 0F7H ; MIMIC Scratch Register
DLATL EQU 0F8H ; Divisor Latch (Low)
DLATM EQU 0F9H ; Divisor Latch (High)
TTCR EQU 0FAH ; TX Time Constant
RTCR EQU 0FBH ; RX Time Constant
IVEC EQU 0FCH ; MIMIC Interrupt Vector
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
MMCR EQU 0FFH ; MIMIC Master Control Register
; Z80182 PIO Registers
DDRA EQU 0EDH ; Data Direction Register A
DRA EQU 0EEH ; Port A Data
DDRB EQU 0E4H ; Data Direction Register B
DRB EQU 0E5H ; Data B Data
DDRC EQU 0DDH ; Data Direction Register C
DRC EQU 0DEH ; Data C Data
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; ESCC Registers on Z80182
SCCACNT EQU 0E0H ; ESCC Control Channel A
SCCAD EQU 0E1H ; ESCC Data Channel A
SCCBCNT EQU 0E2H ; ESCC Control Channel B
SCCBD EQU 0E3H ; ESCC Data Channel B
; [E]SCC Internal Register Definitions
RR0 EQU 00H
RR1 EQU 01H
RR2 EQU 02H
RR3 EQU 03H
RR6 EQU 06H
RR7 EQU 07H
RR10 EQU 0AH
RR12 EQU 0CH
RR13 EQU 0DH
RR15 EQU 0FH
WR0 EQU 00H
WR1 EQU 01H
WR2 EQU 02H
WR3 EQU 03H
WR4 EQU 04H
WR5 EQU 05H
WR6 EQU 06H
WR7 EQU 07H
WR9 EQU 09H
WR10 EQU 0AH
WR11 EQU 0BH
WR12 EQU 0CH
WR13 EQU 0DH
WR14 EQU 0EH
WR15 EQU 0FH
; FDC37C665/6 Parallel Port in Standard AT Mode
DPORT EQU 8CH ; Data Port
SPORT EQU 8DH ; Status Port
CPORT EQU 8EH ; Control Port
; FDC37C665/6 Configuration Control (access internal registers)
CFCNTL EQU 90H ; Configuration control port
CFDATA EQU 91H ; Configuration data port
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
DCR EQU 92H ; Drive Control Register (Digital Output)
MSR EQU 94H ; Main Status Register
DR EQU 95H ; Data/Command Register
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
_DMA EQU 0A0H ; Diskette DMA Address
; FDC37C665/6 Serial Port (National 16550 compatible)
_RBR EQU 68H ;R Receiver Buffer
_THR EQU 68H ;W Transmit Holding Reg
_IER EQU 69H ;RW Interrupt-Enable Reg
_IIR EQU 6AH ;R Interrupt Ident. Reg
_FCR EQU 6AH ;W FIFO Control Reg
_LCR EQU 6BH ;RW Line Control Reg
_MCR EQU 6CH ;RW Modem Control Reg
_LSR EQU 6DH ;RW Line Status Reg
_MMSR EQU 6EH ;RW Modem Status Reg
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
_DLM EQU 69H ;RW Divisor MSB | set High
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
IF HARDDSK
NCR EQU 40H ; Base of NCR 5380
; 5380 Chip Registers
NCRDAT EQU NCR ; Current SCSI Data (Read)
; Output Data Register (Write)
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
NCRST EQU NCR+5 ; Bus & Status Register (Read)
; Start DMA Send (Write)
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
; Start DMA Initiator Receive (Write)
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
; Bit Assignments for NCR 5380 Ports as indicated
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
B_BSY EQU 01000000B ; *Busy (NCRBUS)
B_REQ EQU 00100000B ; *Request (NCRBUS)
B_MSG EQU 00010000B ; *Message (NCRBUS)
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
B_IO EQU 00000100B ; *I/O (NCRBUS)
B_SEL EQU 00000010B ; *Select (NCRBUS)
B_PHAS EQU 00001000B ; Phase Match (NCRST)
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
ENDIF ;harddsk
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
; Set the base GIDE equate to the jumper setting on the GIDE board.
IF IDE
GIDE EQU 50H ; Set base of 16 byte address range
IDEDOR EQU GIDE+6 ; Digital Output Register
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
IDEErr EQU GIDE+9 ; IDE Error Register
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
CMDHOM EQU 10H ; Home Drive Heads
CMDRD EQU 20H ; Read Sector Command (w/retry)
CMDWR EQU 30H ; Write Sector Command (w/retry)
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
CMDFMT EQU 50H ; Format Track Command
CMDDIAG EQU 90H ; Execute Diagnostics Command
CMDINIT EQU 91H ; Initialize Drive Params Command
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
CMDPWQ EQU 0E5H ; Power Status Query Command
CMDID EQU 0ECH ; Read Drive Ident Data Command
ENDIF ;ide
;=================== End Unique Equates =======================
ENDIF ; REMOVE CODE

21
Source/BPBIOS/dpbhd-ww.lib
View File

@@ -164,18 +164,8 @@ DPBRAM: DEFW 64 ; Records/Track (16 sectors*4 records/sector)
DEFW MSIZR-1 ; Disk Size-1 128 kB 256 kB 512 kB
; Dir Max -or- 64 128 256
; Alloc 0, 1 80H,0 0C0H,0 0F0H,0
IF MSIZR<65
DEFW 63 ; Dir Max-1 1 block
DEFB 80H,0 ; Alloc 0,1
ELSE
IF MSIZR<129
DEFW 128 - 1 ; Dir Max-1 2 blocks
DEFB 0C0H, 00 ; Alloc 0,1
ELSE
DEFW 255 ; Dir Max-1 4 blocks
DEFB 0F0H,0 ; Alloc 0,1
ENDIF
ENDIF
DEFW 0000 ; Check Size
DEFW 0000 ; Trk Offset from beginning of Ram Bank base
;
@@ -200,7 +190,6 @@ MSIZO EQU HB_ROMBLKS ; # of blocks in Drive (by Memory/Block size)
; 1x512k = 192 (384k) - 176 (352k) w/User Bank
; 2x512k = 448 (896k) - 432 (864k) w/User Bank
;DPBROM: DEFW 32 ; Sectors/Track
DPBROM: DEFW 64 ; Sectors/Track
DEFB 4 ; Block Shift Factor (2k per block)
DEFB 0FH ; Block Mask
@@ -212,18 +201,8 @@ DPBROM: DEFW 64 ; Sectors/Track
DEFW MSIZO-1 ; Disk Size-1 128 kB 256 kB 512 kB
; Dir Max -or- 64 128 256
; Alloc 0, 1 80H,0 0C0H,0 0F0H,0
IF MSIZO<65
DEFW 63 ; Dir Max-1 1 block
DEFB 80H,0 ; Alloc 0,1
ELSE
IF MSIZO<129
DEFW 128 - 1 ; Dir Max-1 2 blocks
DEFB 0C0H, 00 ; Alloc 0,1
ELSE
DEFW 255 ; Dir Max-1 4 blocks
DEFB 0F0H,0 ; Alloc 0,1
ENDIF
ENDIF
DEFW 0000 ; Check Size
DEFW 0000 ; Trk Offset from beginning of Ram Bank base
;

44
Source/BPBIOS/dphhd.lib
View File

@@ -22,7 +22,7 @@
XDPH90: DEFB TRUE ; Format lock flag (Lock RAM Drive)
DEFB FIXDSK ; Disk Drive Type
DEFB 2 ; Driver ID = Treat as Hard Drive
DEFB HB_MDDEV ; Physical Drive Number
DEFB HB_MDRAM ; Physical Drive Number
DPH$90: DEFW 0 ; Skew Table pointer
DEFW 0,0,0 ; Scratch area
DEFW DIRBUF ; Directory buffer pointer
@@ -35,7 +35,7 @@ DPH$90: DEFW 0 ; Skew Table pointer
XDPH91: DEFB TRUE ; Format lock flag (Lock ROM Drive)
DEFB FIXDSK ; Disk Drive Type
DEFB 2 ; Driver ID = Treat as Hard Drive
DEFB HB_MDDEV + 1 ; Physical Drive Number
DEFB HB_MDROM ; Physical Drive Number
DPH$91: DEFW 0 ; Skew Table pointer
DEFW 0,0,0 ; Scratch area
DEFW DIRBUF ; Directory buffer pointer
@@ -48,7 +48,7 @@ DPH$91: DEFW 0 ; Skew Table pointer
XDPH50: DEFB TRUE ; Format lock flag (Lock First Hard Drive)
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$50: DEFW 0 ; Skew table pointer
DEFW 0,0,0 ; Scratch area
DEFW DIRBUF ; Directory buffer pointer
@@ -61,7 +61,7 @@ DPH$50: DEFW 0 ; Skew table pointer
XDPH51: DEFB TRUE ; --- Second Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$51: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -74,7 +74,7 @@ DPH$51: DEFW 0
XDPH52: DEFB TRUE ; --- Third Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..2] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..2] for this Partition
DPH$52: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -87,7 +87,7 @@ DPH$52: DEFW 0
XDPH53: DEFB TRUE ; --- Fourth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$53: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -100,7 +100,7 @@ DPH$53: DEFW 0
XDPH54: DEFB TRUE ; --- Fifth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$54: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -113,7 +113,7 @@ DPH$54: DEFW 0
XDPH55: DEFB TRUE ; --- Sixth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$55: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -126,7 +126,7 @@ DPH$55: DEFW 0
XDPH56: DEFB TRUE ; --- Seventh Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$56: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -139,7 +139,7 @@ DPH$56: DEFW 0
XDPH57: DEFB TRUE ; --- Eighth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
DEFB HB_HDDEV + 0 ; Physical drive [0..6] for this Partition
DEFB HB_HDDEV0 ; Physical drive [0..6] for this Partition
DPH$57: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -152,11 +152,7 @@ DPH$57: DEFW 0
XDPH58: DEFB TRUE ; --- Ninth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
IF MK4
DEFB HB_HDDEV + 2 ; SD card on MK4
ELSE
DEFB HB_HDDEV + 1 ; SLAVE IDE or 2nd simh HDSK
ENDIF
DEFB HB_HDDEV1 ; Physical drive [0..6] for this Partition
DPH$58: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -169,11 +165,7 @@ DPH$58: DEFW 0
XDPH59: DEFB TRUE ; --- Tenth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
IF MK4
DEFB HB_HDDEV + 2 ; SD card on MK4
ELSE
DEFB HB_HDDEV + 1 ; SLAVE IDE or 2nd simh HDSK
ENDIF
DEFB HB_HDDEV1 ; Physical drive [0..6] for this Partition
DPH$59: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -186,11 +178,7 @@ DPH$59: DEFW 0
XDPH60: DEFB TRUE ; --- Eleventh Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
IF MK4
DEFB HB_HDDEV + 2 ; SD card on MK4
ELSE
DEFB HB_HDDEV + 1 ; SLAVE IDE or 2nd simh HDSK
ENDIF
DEFB HB_HDDEV1 ; Physical drive [0..6] for this Partition
DPH$60: DEFW 0
DEFW 0,0,0
DEFW DIRBUF
@@ -203,11 +191,7 @@ DPH$60: DEFW 0
XDPH61: DEFB TRUE ; --- Twelveth Hard Drive/Partition
DEFB FIXDSK ; Disk drive type
DEFB 2 ; Driver ID - 2=hard drive
IF MK4
DEFB HB_HDDEV + 2 ; SD card on MK4
ELSE
DEFB HB_HDDEV + 1 ; SLAVE IDE or 2nd simh HDSK
ENDIF
DEFB HB_HDDEV1 ; Physical drive [0..6] for this Partition
DPH$61: DEFW 0
DEFW 0,0,0
DEFW DIRBUF

4
Source/BPBIOS/hard-ww.z80
View File

@@ -197,7 +197,9 @@ HDSK_RW1:
POP BC ; RESTORE INCOMING FUNCTION, DEVICE/UNIT
RET NZ ; ABORT IF SEEK RETURNED AN ERROR W/ ERROR IN A
LD HL,(HB_DSKBUF) ; GET BUFFER ADDRESS
LD D,BID_HB ; BUFFER IN HBIOS BANK
;LD D,BID_HB ; BUFFER IN HBIOS BANK
LD A,(HBX_BNKBIOS) ; BUFFER IN HBIOS BANK
LD D,A ; PUT IN D
LD E,1 ; ONE SECTOR
CALL HBX_INVOKE ; DO IT
OR A ; SET FLAGS

306
Source/BPBIOS/hbios.z80
View File

@@ -4,77 +4,13 @@
; - Retro Brew -
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
;
HB_DEFBNK EQU BID_USR ; Default bank number
;
; LOCATION OF DISPATCH ENTRY IN HBIOS BANK
;
HB_DISPATCH EQU 403H
HB_STACK EQU 500H
;
; HBIOS Functions
;
H_ALLOC EQU 0F6H ; HBIOS Func: ALLOCATE Heap Memory
HBF_ALLOC EQU 0F6H ; HBIOS Func: ALLOCATE Heap Memory
HBF_BNKINFO EQU 0F8F2H ; HBIOS Func: Get Bank Info
;
; PLATFORM SPECIFIC CONSTANTS
; HBIOS Proxy Addresses
;
IF SBC OR ZETA OR ZETA2
SBC_BASE EQU 60H
ENDIF ;SBC OR ZETA OR ZETA2
IF SBC OR ZETA
MPCL_RAM EQU SBC_BASE + 18H ; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
MPCL_ROM EQU SBC_BASE + 1CH ; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
ENDIF ;SBC OR ZETA
IF ZETA2
MPGSEL_0 EQU SBC_BASE + 18H
MPGSEL_1 EQU SBC_BASE + 19H
MPGSEL_2 EQU SBC_BASE + 1AH
MPGSEL_3 EQU SBC_BASE + 1BH
MPGENA EQU SBC_BASE + 1CH
ENDIF ;ZETA2
IF N8
N8_BASE EQU 80H ; BASE I/O ADDRESS BOARD PERIPHERALS (NON-CPU)
ACR EQU N8_BASE + 14H ; AUXILLARY CONTROL REGISTER
DEFACR EQU 1BH ; DEFAULT VALUE FOR ACR
CPU_BBR EQU 40H + 39H
ENDIF ;N8
IF MK4
CPU_BBR EQU 40H + 39H
ENDIF ;MK4
CSEG
IF INTPXY
DB 0 ; Prevents link error in BPBUILD
HB_XFC EQU 0FFE0H
HB_XFCIMG EQU $
.PHASE HB_XFC
HB_CURBNK: DB 0
HB_INVBNK: DB 0
HB_SRCADR: DW 0
HB_SRCBNK: DB 0
HB_DSTADR: DW 0
HB_DSTBNK: DB 0
HB_CPYLEN: DW 0
DB 0,0,0,0,0,0
HB_INVOKE: JP HBX_INVOKE
HB_BNKSEL: JP HBX_BNKSEL
HB_BNKCPY: JP HBX_BNKCPY
HB_BNKCALL: JP 0 ; HBX_BNKCALL (NOT IMPLEMENTED)
DB 0,0 ; RESERVED
HB_IDENT: DW 0 ; HBX_IDENT
.DEPHASE
HB_XFCSIZ EQU $ - HB_XFCIMG
ELSE
HBX_INVOKE EQU 0FFF0H
HBX_BNKSEL EQU 0FFF3H
HBX_BNKCPY EQU 0FFF6H
@@ -88,36 +24,49 @@ HB_DSTADR EQU 0FFE5H
HB_DSTBNK EQU 0FFE7H
HB_CPYLEN EQU 0FFE8H
ENDIF ;INTPXY
CSEG
;
;==================================================================================================
; HBIOS INTERFACE
; HBIOS INITIALIZATION
;==================================================================================================
;
; This code should be moved to follow CBOOT so that it will be reused
; by RAM data.
;
HBX_INIT:
IF INTPXY
; Copy HB_XFCIMG to target location
LD HL,HB_XFCIMG
LD DE,HB_XFC ; point to HBIOS comm block
LD BC,HB_XFCSIZ
LDIR
; Setup RST 08 vector
LD A,0C3H ; $C3 = JP
LD (08H),A
LD HL,HBX_INVOKE
LD (09H),HL
ENDIF ;INTPXY
; Init HB data fields
LD A,BID_USR
LD (HB_CURBNK),A
LD (HB_SRCBNK),A
LD (HB_DSTBNK),A
;; Init HB data fields
;LD A,BID_USR
;LD (HB_CURBNK),A
;LD (HB_SRCBNK),A
;LD (HB_DSTBNK),A
; Initialize BPBIOS bank numbers from HBIOS
; BNKU (UABNK) --> 0 (DISABLED)
; BNK0 (TPABNK) --> BID_USR
; BNK1 --> BID_COM
; BNK2 (SYSBNK) --> BID_AUX (BID_BIOS - 1)
; BNK3 (RAMBNK) --> BID_RAMD0 (0x80)
; BNKM (MAXBNK) --> BID_RAMDN (BID_BIOS - 5)
LD BC,HBF_BNKINFO ; HBIOS BNKINFO function
CALL HBX_INVOKE ; DO IT, D=BID_BIOS, E=BID_USER
LD A,E ; BID_USR
LD (TPABNK),A ; SET BNK0 (TPABNK)
LD A,D ; BID_BIOS
LD (HBX_BNKBIOS),A ; SET HBX_BNKBIOS
DEC A ; BID_AUX
LD (SYSBNK),A ; SET BNK2 (SYSBNK)
SUB 4 ; BID_RAMDN
LD (MAXBNK),A ; SET BNKM (MAXBNK)
LD A,80H ; FIRST PHYSICAL RAM BANK IS ALWAYS 0x80
LD (RAMBNK),A ; SET BNK3 (RAMBNK)
IF BANKED
@@ -130,25 +79,14 @@ HBX_INIT:
CALL MOVE ; Do it
LD A,(TPABNK) ; Set all Bank regs to TPA
COMMON /BANK2/
ORG_BANK2 EQU $
COMMON /B2RAM/
ORG_B2RAM EQU $
ENDIF ;BANKED
; begin debug
CSEG
CALL NEWLINE2
LD DE,HB_STR_TAG
CALL WRITESTR
IF INTPXY
LD DE,HB_STR_INTPXY
ELSE
LD DE,HB_STR_EXTPXY
ENDIF ;INTPXY
CALL WRITESTR
CALL NEWLINE
LD DE,HB_STR_CSEG
CALL WRITESTR
@@ -179,14 +117,25 @@ ORG_B2RAM EQU $
RET
HB_STR_TAG: DB "HBIOS: $"
HB_STR_INTPXY: DB "Internal Proxy$"
HB_STR_EXTPXY: DB "External Proxy$"
HB_STR_CSEG: DB "CSEG=$"
HB_STR_DSEG: DB ", DSEG=$"
HB_STR_BANK2: DB ", BANK2=$"
HB_STR_B2RAM: DB ", B2RAM=$"
HB_STR_RESVD: DB ", RESVD=$"
; end debug
CSEG
HBX_BNKBIOS DEFB 0 ; Bank id of HBIOS bank
;
;==================================================================================================
; HBIOS INTERFACE
;==================================================================================================
;
; TODO: Move the following into ibmv-ww.z80 which is where it belongs.
;
HBX_XCOPY:
LD A,C
LD (HB_SRCBNK),A
@@ -197,159 +146,6 @@ HBX_XCOPY:
HBX_COPY:
JP HBX_BNKCPY
IF INTPXY
;==================================================================================================
; SELECT MEMORY BANK FOR LOWER 32K
;==================================================================================================
HBX_BNKSEL:
LD (HB_CURBNK),A
IF SBC OR ZETA
OUT (MPCL_ROM),A
OUT (MPCL_RAM),A
RET
ENDIF ;SBC OR ZETA
IF ZETA2
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
ADD A,16 ; ADD 16 x 32K - RAM STARTS FROM 512K
;
HBX_ROM:
RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
OUT (MPGSEL_0),A ; BANK_0: 0K - 16K
INC A ;
OUT (MPGSEL_1),A ; BANK_1: 16K - 32K
RET
ENDIF ;ZETA2
IF N8
BIT 7,A
JR Z,HBX_ROM
;
HBX_RAM:
RES 7,A
RLCA
RLCA
RLCA
OUT0 (CPU_BBR),A
LD A,DEFACR | 80H
OUT0 (ACR),A
RET
;
HBX_ROM:
OUT0 (RMAP),A
XOR A
OUT0 (CPU_BBR),A
LD A,DEFACR
OUT0 (ACR),A
RET
ENDIF ; N8
IF MK4
RLCA
JR NC,HBX_BNKSEL1
XOR 00100001B
HBX_BNKSEL1:
RLCA
RLCA
OUT0 (CPU_BBR),A
RET
ENDIF ; MK4
;==================================================================================================
; INTERBANK MEMORY COPY
;==================================================================================================
HBX_BNKCPY:
HB_DI ; NOTE: ONLY REQUIRED WHEN USING IM 1
LD (HBX_STKSAV),SP
LD SP,HBX_TMPSTK
LD A,(HB_CURBNK) ; GET CURRENT BANK
PUSH AF ; AND SAVE TO RESTORE LATER
PUSH BC ; CUR LEN -> (SP)
;
HBX_BC_LOOP:
EX (SP),HL ; HL := CUR LEN, (SP) := CUR SRC
LD BC,HBX_BUFSIZ ; SET BC TO BOUNCE BUFFER SIZE
OR A ; CLEAR CARRY FLAG
SBC HL,BC ; CUR LEN := CUR LEN - BBUF SIZE
JR C,HBX_BC_LAST ; END GAME, LESS THAN BBUF BYTES LEFT
EX (SP),HL ; HL := CUR SRC, (SP) := REM LEN
CALL HBX_BC_ITER ; DO A FULL BBUF SIZE CHUNK
JR HBX_BC_LOOP ; AND REPEAT TILL DONE
;
HBX_BC_LAST:
; HL IS BETWEEN -(BBUF SIZE) AND -1, BC = BBUF SIZE
OR A ; CLEAR CARRY
ADC HL,BC ; HL := REM LEN (0 - 127)
EX (SP),HL ; HL := CUR SRC, (SP) := REM LEN
POP BC ; BC := REM LEN
CALL NZ,HBX_BC_ITER ; DO FINAL CHUNK, BUT ONLY IF NOT ZERO BYTES
POP AF ; RECOVER ORIGINAL BANK
CALL HBX_BNKSEL ; SWITCH TO CURRENT BANK AND EXIT
LD SP,(HBX_STKSAV)
HB_EI ; NOTE: ONLY REQUIRED WHEN USING IM 1
RET
;
HBX_BC_ITER:
; HL = SRC ADR, DE = DEST ADR, BC = LEN
PUSH BC ; SAVE COPY LEN
PUSH DE ; FINAL DEST ON STACK
LD DE,HBX_BUF ; SET DEST TO BUF
LD A,(HB_SRCBNK) ; GET SOURCE BANK
CALL HBX_BNKSEL ; SWITCH TO SOURCE BANK
LDIR ; HL -> BUF (DE), BC BYTES, HL UPDATED SRC ADR
POP DE ; DE := FINAL DEST
POP BC ; GET LEN BACK IN BC
PUSH HL ; SAVE UPDATED SRC ADR
LD HL,HBX_BUF ; SET SRC ADR TO BUF
LD A,(HB_DSTBNK) ; GET DEST BANK
CALL HBX_BNKSEL ; SWITCH TO DEST BANK
LDIR ; BUF (HL) -> DE, BC BYTES, DE UPDATED DEST ADR
POP HL ; RECOVER UPDATED SRC ADR
; HL = UPD SRC, DE = UPD DEST, BC = 0
RET
;==================================================================================================
; ENTRY POINT FOR BIOS FUNCTIONS (TARGET OF RST 08)
;==================================================================================================
HBX_INVOKE:
LD (HBX_INVSP),SP ; SAVE ORIGINAL STACK FRAME
LD A,(HB_CURBNK) ; GET CURRENT BANK
LD (HB_INVBNK),A ; SAVE INVOCATION BANK
; HB_DI
LD SP,HBX_TMPSTK ; USE SMALL TEMP STACK FRAME IN HI MEM FOR BANK SWITCH
LD A,BID_HB ; HBIOS BANK
CALL HBX_BNKSEL ; SELECT IT
LD SP,HB_STACK ; NOW USE FULL HBIOS STACK IN HBIOS BANK
; HB_EI
CALL HB_DISPATCH ; CALL HBIOS FUNCTION DISPATCHER
; HB_DI
LD SP,HBX_TMPSTK ; USE SMALL TEMP STACK FRAME IN HI MEM FOR BANK SWITCH
PUSH AF ; SAVE AF (FUNCTION RETURN)
LD A,(HB_INVBNK) ; LOAD ORIGINAL BANK
CALL HBX_BNKSEL ; SELECT IT
POP AF ; RESTORE AF
LD SP,0 ; RESTORE ORIGINAL STACK FRAME
HBX_INVSP EQU $ - 2
; HB_EI
RET ; RETURN TO CALLER
ENDIF ;INTPXY
;==================================================================================================
; LD A,(C:HL)
;==================================================================================================
@@ -452,10 +248,4 @@ HBX_STKSAV: DEFW 0 ; Saved stack pointer during HBIOS calls
DEFS 32 ; Private stack for HBIOS
HBX_TMPSTK EQU $ ; Top of private stack
IF INTPXY
HBX_BUFSIZ EQU 40H
HBX_BUF: DEFS HBX_BUFSIZ ; Interbank copy buffer
ENDIF ;INTPXY


6
Source/BPBIOS/icfg-ww.z80
View File

@@ -174,7 +174,7 @@ CNTRLR: DEFB 80H ; Controller Types recognized are:
; 90H = HBIOS Disk IO
; First drive (Generic HBIOS drive configuration)
BITS DEFL HB_HDDEV ; First HBIOS Hard Disk Drive
BITS DEFL HB_HDDEV0 ; First HBIOS Hard Disk Drive
BITS DEFL BITS+[UNIT_0 AND 10H] ; If active, set Bit 4
@@ -188,7 +188,7 @@ HDRV0: ; used to convert logical to physical sector addressing
; Second drive (Generic HBIOS drive configuration)
BITS DEFL HB_HDDEV + 1 ; Second HBIOS Hard Disk Drive
BITS DEFL HB_HDDEV1 ; Second HBIOS Hard Disk Drive
BITS DEFL BITS+[UNIT_1 AND 10H] ; If active, set Bit 4
@@ -201,7 +201,7 @@ HDRV1: DEFB BITS ; Set Device, Unit, and Active bits
; Third drive (Generic HBIOS drive configuration)
BITS DEFL HB_HDDEV + 2 ; Third HBIOS Hard Disk Drive
BITS DEFL HB_HDDEV2 ; Third HBIOS Hard Disk Drive
BITS DEFL BITS+[UNIT_2 AND 10H] ; If active, set Bit 4

4
Source/BPBIOS/ramd-ww.z80
View File

@@ -68,7 +68,9 @@ RAMWR2:
ADD A,C ; COMBINE TO GET ACTUAL SOURCE BANK NUM
; SETUP FOR INTERBANK COPY
LD C,A ; SOURCE BANK TO C
LD B,BID_HB ; DEST BANK TO B (HSTBUF IN HBIOS)
;LD B,BID_HB ; DEST BANK TO B (HSTBUF IN HBIOS)
LD A,(HBX_BNKBIOS) ; DEST BANK (HSTBUF IN HBIOS)
LD B,A ; PUT IN B
LD DE,(HB_DSKBUF) ; DEST ADDRESS TO DE; HL ALREADY HAS SOURCE ADDRESS
; REVERSE VALUES IF WRITE
POP AF ; Read or Write?

97
Source/BPBIOS/romwbw-m.lib
View File

@@ -1,97 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew Processors W/ RomWBW HBIOS - **********************
; HBIOS specific customizations
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
;
; NOTE: Must make sure settings below match hardware and
; HBIOS configuration.
;
HBIOS EQU YES ; Use HBIOS functions
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
;
; Set exactly one of the following to YES to specify platform
;
SBC EQU NO
ZETA EQU NO
ZETA2 EQU NO
N8 EQU NO
MK4 EQU YES
;
; SIMH SUPPORT - only used with SBC
IF SBC
SIMH EQU YES ; Set yes if running on SimH
ELSE
SIMH EQU NO
ENDIF
;
; Set to YES FOR BIOS clock support else NO If no clock
;
HBCLK EQU YES ; HBIOS clock driver
;
; Set HB_IODEV to appropriate console device
;
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device
; Change if using PROPIO etc.
;
; Set HB_HDDEV to appropriate hard disk driver
;
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device
;
; Set HB_MDDEV to appropriate memory disk driver
;
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device
;
; Floppy disk support
;
IF MK4 or SIMH
DRV_O SET NO ; YES if system has flopy drives
DRV_P SET NO ; YES if system has flopy drives
ENDIF ;MK4 or SIMH
;
; RAM/ROM disk sizes expressed as count of 2K blocks
;
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block
;
; Layout of RAM banks
;
IF SBC OR ZETA OR ZETA2 OR MK4
BID_RAMD EQU 80H
BID_RAMM EQU 8BH
BID_SYS EQU 8CH
BID_HB EQU 8DH
BID_USR EQU 8EH
BID_COM EQU 8FH
ENDIF
IF N8
BID_RAMD EQU 80H
BID_RAMM EQU 9BH
BID_SYS EQU 9CH
BID_HB EQU 9DH
BID_USR EQU 9EH
BID_COM EQU 9FH
ENDIF
;
IF INTPXY
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block
ELSE
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy
ENDIF
IF INTPXY
HB_EI MACRO
ENDM
HB_DI MACRO
ENDM
ELSE
HB_EI MACRO
EI
ENDM
HB_DI MACRO
DI
ENDM
ENDIF


82
Source/BPBIOS/romwbw-mk4.lib
View File

@@ -1,82 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - D-X Designs Pty Ltd P112 CPU Board - **********************
; HBIOS specific customizations
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
;
; NOTE: Must make sure settings below match hardware and
; HBIOS configuration.
;
HBIOS EQU YES ; Use HBIOS functions
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
;
; Set exactly one of the following to YES to specify platform
;
N8VEM EQU NO
ZETA EQU NO
ZETA2 EQU NO
N8 EQU NO
MK4 EQU YES
;
; Set either the following to YES (or both to NO for no clock code)
;
SIMHCLK EQU NO ; Direct SIMH clock access
HBCLK EQU YES ; HBIOS clock driver
;
; Set HB_IODEV to appropriate console device
;
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device
;
; Set HB_HDDEV to the first (boot) hard disk device unit number
;
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device
;
; Set HB_MDDEV to appropriate memory disk driver
;
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device
;
; RAM/ROM disk sizes expressed as count of 2K blocks
;
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block
;
; Layout of RAM banks
;
IF N8VEM OR ZETA OR ZETA2 OR MK4
BID_RAMD EQU 80H
BID_RAMM EQU 8BH
BID_SYS EQU 8CH
BID_HB EQU 8DH
BID_USR EQU 8EH
BID_COM EQU 8FH
ENDIF
IF N8
BID_RAMD EQU 80H
BID_RAMM EQU 9BH
BID_SYS EQU 9CH
BID_HB EQU 9DH
BID_USR EQU 9EH
BID_COM EQU 9FH
ENDIF
;
IF INTPXY
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block
ELSE
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy
ENDIF
IF INTPXY
HB_EI MACRO
ENDM
HB_DI MACRO
ENDM
ELSE
HB_EI MACRO
EI
ENDM
HB_DI MACRO
DI
ENDM
ENDIF

97
Source/BPBIOS/romwbw-s.lib
View File

@@ -1,97 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - Retro-Brew Processors W/ RomWBW HBIOS - **********************
; HBIOS specific customizations
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
;
; NOTE: Must make sure settings below match hardware and
; HBIOS configuration.
;
HBIOS EQU YES ; Use HBIOS functions
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
;
; Set exactly one of the following to YES to specify platform
;
SBC EQU YES
ZETA EQU NO
ZETA2 EQU NO
N8 EQU NO
MK4 EQU NO
;
; SIMH SUPPORT - only used with SBC
IF SBC
SIMH EQU YES ; Set yes if running on SimH
ELSE
SIMH EQU NO
ENDIF
;
; Set to YES FOR BIOS clock support else NO If no clock
;
HBCLK EQU YES ; HBIOS clock driver
;
; Set HB_IODEV to appropriate console device
;
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device
; Change if using PROPIO etc.
;
; Set HB_HDDEV to appropriate hard disk driver
;
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device
;
; Set HB_MDDEV to appropriate memory disk driver
;
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device
;
; Floppy disk support
;
IF MK4 or SIMH
DRV_O SET NO ; YES if system has flopy drives
DRV_P SET NO ; YES if system has flopy drives
ENDIF ;MK4 or SIMH
;
; RAM/ROM disk sizes expressed as count of 2K blocks
;
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block
;
; Layout of RAM banks
;
IF SBC OR ZETA OR ZETA2 OR MK4
BID_RAMD EQU 80H
BID_RAMM EQU 8BH
BID_SYS EQU 8CH
BID_HB EQU 8DH
BID_USR EQU 8EH
BID_COM EQU 8FH
ENDIF
IF N8
BID_RAMD EQU 80H
BID_RAMM EQU 9BH
BID_SYS EQU 9CH
BID_HB EQU 9DH
BID_USR EQU 9EH
BID_COM EQU 9FH
ENDIF
;
IF INTPXY
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block
ELSE
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy
ENDIF
IF INTPXY
HB_EI MACRO
ENDM
HB_DI MACRO
ENDM
ELSE
HB_EI MACRO
EI
ENDM
HB_DI MACRO
DI
ENDM
ENDIF


82
Source/BPBIOS/romwbw-sim.lib
View File

@@ -1,82 +0,0 @@
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
; B/P BIOS Configuration and Equate File. ** System Dependant **
; - D-X Designs Pty Ltd P112 CPU Board - **********************
; HBIOS specific customizations
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; BIOS Configuration Equates and Macros
;
; NOTE: Must make sure settings below match hardware and
; HBIOS configuration.
;
HBIOS EQU YES ; Use HBIOS functions
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
;
; Set exactly one of the following to YES to specify platform
;
N8VEM EQU YES
ZETA EQU NO
ZETA2 EQU NO
N8 EQU NO
MK4 EQU NO
;
; Set either the following to YES (or both to NO for no clock code)
;
SIMHCLK EQU NO ; Direct SIMH clock access
HBCLK EQU YES ; HBIOS clock driver
;
; Set HB_IODEV to appropriate console device
;
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device
;
; Set HB_HDDEV to the first (boot) hard disk device unit number
;
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device
;
; Set HB_MDDEV to appropriate memory disk driver
;
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device
;
; RAM/ROM disk sizes expressed as count of 2K blocks
;
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block
;
; Layout of RAM banks
;
IF N8VEM OR ZETA OR ZETA2 OR MK4
BID_RAMD EQU 80H
BID_RAMM EQU 8BH
BID_SYS EQU 8CH
BID_HB EQU 8DH
BID_USR EQU 8EH
BID_COM EQU 8FH
ENDIF
IF N8
BID_RAMD EQU 80H
BID_RAMM EQU 9BH
BID_SYS EQU 9CH
BID_HB EQU 9DH
BID_USR EQU 9EH
BID_COM EQU 9FH
ENDIF
;
IF INTPXY
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block
ELSE
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy
ENDIF
IF INTPXY
HB_EI MACRO
ENDM
HB_DI MACRO
ENDM
ELSE
HB_EI MACRO
EI
ENDM
HB_DI MACRO
DI
ENDM
ENDIF

81
Source/BPBIOS/romwbw.lib
View File

@@ -9,89 +9,54 @@
; HBIOS configuration.
;
HBIOS EQU YES ; Use HBIOS functions
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
HBLOC EQU 0FE00H ; Location of HBIOS proxy
MEMTOP EQU HBLOC - 1 ; Last usable address
;
; Set exactly one of the following to YES to specify platform
;
SBC EQU YES
ZETA EQU NO
ZETA2 EQU NO
N8 EQU NO
MK4 EQU NO
;
; SIMH SUPPORT - only used with SBC
IF SBC
SIMH EQU YES ; Set yes if running on SimH
ELSE
SIMH EQU NO
ENDIF
;
; Set to YES FOR BIOS clock support else NO If no clock
;
HBCLK EQU YES ; HBIOS clock driver
HB_RAMBANKS EQU 16 ; For systems with 512K of RAM
;HB_RAMBANKS EQU 32 ; For systems with 1MB of RAM
HB_ROMBANKS EQU 16 ; For systems with 512K of ROM
;HB_ROMBANKS EQU 32 ; For systems with 1MB of ROM
;
; Set HB_IODEV to appropriate console device
;
HB_IODEV EQU 0 ; Assume we want to use first HBIOS serial device
; Change if using PROPIO etc.
;
; Set HB_HDDEV to appropriate hard disk driver
;
HB_HDDEV EQU 2 ; Assumes disk device #2 is first hard disk device
;
; Set HB_MDDEV to appropriate memory disk driver
;
HB_MDDEV EQU 0 ; Assumes disk device #0 is ROM disk device
HB_MDRAM EQU 0 ; HBIOS Disk Device #0 is normally RAM Disk
HB_MDROM EQU 1 ; HBIOS Disk Device #1 is normally ROM Disk
;
; Set HB_HDDEV to appropriate hard disk driver
;
HB_HDDEV0 EQU 2 ; First hard disk is HBIOS Disk Device #2
HB_HDDEV1 EQU 3 ; Second hard disk is HBIOS Disk Device #3
HB_HDDEV2 EQU 4 ; Third hard disk is HBIOS Disk Device #4
;
; Floppy disk support
;
IF MK4 or SIMH
; TODO: Query HBIOS to see if system has floppy drive(s)
;
DRV_O SET NO ; YES if system has flopy drives
DRV_P SET NO ; YES if system has flopy drives
ENDIF ;MK4 or SIMH
;
; RAM/ROM disk sizes expressed as count of 2K blocks
;
HB_RAMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
HB_ROMBLKS EQU 192 ; 512K - 128K reserved / 2K per block
;HB_ROMBLKS EQU 448 ; 1024K - 128K reserved / 2K per block
HB_RAMBLKS EQU (HB_RAMBANKS - 8) * 16
HB_ROMBLKS EQU (HB_ROMBANKS - 4) * 16
;
; Layout of RAM banks
;
IF SBC OR ZETA OR ZETA2 OR MK4
BID_RAMD EQU 80H
BID_RAMM EQU 8BH
BID_SYS EQU 8CH
BID_HB EQU 8DH
BID_USR EQU 8EH
BID_COM EQU 8FH
ENDIF
IF N8
BID_RAMD EQU 80H
BID_RAMM EQU 9BH
BID_SYS EQU 9CH
BID_HB EQU 9DH
BID_USR EQU 9EH
BID_COM EQU 9FH
ENDIF
BID_RAMM EQU 80H + HB_RAMBANKS - 9
BID_SYS EQU 80H + HB_RAMBANKS - 4
BID_HB EQU 80H + HB_RAMBANKS - 3
BID_USR EQU 80H + HB_RAMBANKS - 2
BID_COM EQU 80H + HB_RAMBANKS - 1
;
IF INTPXY
MEMTOP EQU 0FFE0H - 1 ; Start of HBIOS 32 byte control block
ELSE
MEMTOP EQU HBLOC - 1 ; Start of HBIOS 512 byte proxy
ENDIF
IF INTPXY
HB_EI MACRO
ENDM
HB_DI MACRO
ENDM
ELSE
HB_EI MACRO
EI
ENDM
HB_DI MACRO
DI
ENDM
ENDIF


122
Source/BPBIOS/z3base.lib
View File

@@ -1,8 +1,13 @@
; B/P Bios System Z3 Definition File.
; z3base.fp -- B/P Bios System Z3 Definition File for not or partially
; banked system with 512 byte external HBIOS proxy (no
; internal proxy).
; This file is adapted from the basic Z3BASE.LIB configuration file used for
; most ZCPR33 systems. It has added the new definitions for the Resident
; User Space defined in B/P Bios descriptions.
; User Space defined in B/P Bios descriptions and modified for an HBIOS
; implementation with a full external HBIOS proxy (i.e. proxy not internal
; to BPBIOS).
;
;=========================================================================
;== NOTE: The Starting Address of the User Space marks the lower ==
;== base of memory and MUST be entered. B/P Bios Utilities use ==
@@ -14,29 +19,30 @@
; alternative, just leave this file alone and configure everything with
; the utilities provided.
; FFD0 - FFFF 48 Bytes ZCPR3 External Stack
; FF00 - FFCF 208 Bytes Multiple Command Line Buffer
; FE00 - FEFF 256 Bytes Environment Descriptor
; FE00 - FFFF 512 Bytes HBIOS proxy AREA in the top of ram
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer
; FC00 - FCFF 256 Bytes Environment Descriptor
; Bytes 00H-7FH: Z3 Parameters
; Bytes 80H-FFH: Z3 TCAP
; FDFF 1 Byte Wheel byte
; FDF4 - FDFE 11 Bytes Path (5 elements)
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack
; FC00 - FCFF 256 Bytes Named Directory Buffer
; FA00 - FBFF 512 Bytes Flow Command Package
; F200 - F9FF 2.0 KBytes Resident Command Package
; EC00 - F1FF 1.5 KBytes IO Package
; E900 - EBFF .75 KBytes Resident User Space
; FBFF 1 Byte Wheel byte
; FBF4 - FBFE 11 Bytes Path (5 elements)
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack (4x32)
; FAD0 - FAFF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
; F900 - FACF 464 Bytes Named Directory Buffer (25 entries)
; F700 - F9FF 512 Bytes Flow Command Package
; EF00 - F6FF 2.0 KBytes Resident Command Package
; EF00 - EF00 0 KBytes IO Package - no IOP
; EC00 - EEFF 768 Bytes Resident User Space (room for clock driver)
; The remainder is for the Operating System. Exact sizes vary depending
; primarily on the Number and sizes of Hard Drive Partitions, but may be:
; primarily on the Number and sizes of Hard Drive Partitions, typically:
; D100 - EBFF 5.0 KBytes B/P BIOS (unbanked version)
; C300 - D0FF 3.5 KBytes ZSDOS 1.0 BDOS
; BB00 - C2FF 2 KBytes ZCPR 3.3 Command Processor
; 0100 - BAFF ~46 KBytes Transient Program Area
; E100 - EBFF 4.5 KBytes B/P BIOS (banked version)
; D300 - E0FF 3.5 KBytes ZSDOS 1.0 BDOS
; CB00 - D2FF 2 KBytes ZCPR 3.4 Command Processor
; 0100 - C5FF ~50 KBytes Transient Program Area
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
;========================================================================
@@ -46,80 +52,98 @@ TRUE EQU NOT FALSE
YES EQU TRUE
NO EQU FALSE
; The External Stack is placed in the very top position in memory. It is
; mandatory for B/P Bios and ZCPR 3.3.
EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
EXTSTKS EQU YES
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
; place it above the Environment. It is mandatory for ZCPR 3.3.
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
; The Multiple Command Line Buffer is mandatory for ZCPR 3.3. 3.4 & 4.1.
; FD00 - FDCF 208 Bytes
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5
Z3CL EQU MEMTOP+1-Z3CLS-5 ; ZCPR3 Command Line Buffer
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
Z3ENV EQU 0FE00H ; Environment Descriptors
; FC00 - FCFF 256 Bytes Environment Descriptor
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
Z3WHL EQU 0FDFFH ; Wheel Byte Address
; FBFF 1 Byte Wheel byte
Z3WHLS EQU YES
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address
; The Path is mandatory for ZCPR 3.3.
EXPATH EQU 0FDF4H ; External Path starting Address
; FBF4 - FBFE 11 Bytes Path (5 elements)
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
; This defines 5 2-byte Path Elements
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
EXTFCBS EQU YES
EXFCBSZ EQU 36
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
Z3MSGS EQU YES
Z3MSGSZ EQU 80 ; size of buffer
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
SHSTK EQU 0FD00H ; Shell Stack Starting Address
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address
; The External Stack is mandatory for B/P Bios and ZCPR 3.3, 3.4 & 4.1
; FAD0 - FAFF 48 Bytes ; ZCPR3 External Stack (must be 48 bytes)
;EXTSTK EQU 0FAD0H ; ZCPR3 External Stack
EXTSTK EQU SHSTK-48 ; ZCPR3 External Stack
EXTSTKS EQU YES
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
; the named directory buffer.
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer
Z3NDIRS EQU 14 ; Number of Named Directory Elements
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes)
; F900 - FACF 464 Bytes ; Named Directory Buffer - 25 NAMES
Z3NDIRS EQU 25 ; Number of Named Directory Elements
NDIRSZ EQU Z3NDIRS * 18 + 1
; (NDIR Size = Z3NDIRS * 18 + 1 = 451 Bytes)
Z3NDIR EQU SHSTK-(NDIRSZ/256+1)*256 ; Start of Named Directory Buffer
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
FCP EQU 0FA00H ; Start of Flow Command Package
; F700 - F8FF 512 Bytes Flow Command Package
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 0 Bytes)
FCP EQU Z3NDIR-FCPS*128 ; Start of Flow Command Package
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
RCP EQU 0F200H ; Start of Resident Command Processor
; EF00 - F6FF 2.0 KBytes Resident Command Package
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
;RCPS EQU 0 ; (RCP Size = 128 * RCPS = 0 kBytes)
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor
; IO Package definition. Set IOPS to 0 to eliminate IOP
; IO Package definition. Set IOPS to 0 which eliminates IOP
IOP EQU 0EC00H ; Start of IO Package
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
;IOP EQU 0EC00H ; Start of IO Package
; EF00 - EF00 0 KBytes IO Package
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes)
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
IOP EQU RCP-IOPS*128 ; Start of IO Package
;=========================================================================
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
; MUST BE PRESENT!
USPC EQU 0E900H ; Start of Resident User Space (MANDATORY)
;USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes)
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
; EC00 - EEFF 0.75 KBytes Resident User Space
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY)
;--- End of Z3BASE.LIB ---



0
Source/BPBIOS/z3baseft.lib → Source/BPBIOS/z3basef.lib
View File

152
Source/BPBIOS/z3basefn.lib
View File

@@ -1,152 +0,0 @@
; z3base.fp -- B/P Bios System Z3 Definition File for a fully
; banked system with 32 byte external HBIOS proxy and
; internal proxy.
; This file is adapted from the basic Z3BASE.LIB configuration file used for
; most ZCPR33 systems. It has added the new definitions for the Resident
; User Space defined in B/P Bios descriptions.
;=========================================================================
;== NOTE: The Starting Address of the User Space marks the lower ==
;== base of memory and MUST be entered. B/P Bios Utilities use ==
;== this address to locate many portions of the operating system. ==
;=========================================================================
; To change your systems definition, first sketch out the memory map in the
; comment table, then set the equates to reflect the memory map, doing any
; required calculations for element sizes and required spaces. As an
; alternative, just leave this file alone and configure everything with
; the utilities provided. For example reserve top 1k for HBIOS and no IOP.
; FFE0 - FFFF 32 Bytes HBIOS RESERVED AREA (mini proxy)
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
; FE00 - FFAF 432 Bytes Named Directory Buffer
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer
; FC00 - FCFF 256 Bytes Environment Descriptor
; Bytes 00H-7FH: Z3 Parameters
; Bytes 80H-FFH: Z3 TCAP
; FBFF 1 Byte Wheel byte
; FBF4 - FAFE 11 Bytes Path (5 elements)
; FBD0 - FAF3 36 Bytes ZCPR3 External FCB
; FB80 - FACF 80 Bytes ZCPR3 Message Buffers
; FB00 - FA7F 128 Bytes ZCPR3 Shell Stack
; F900 - FAFF 512 Bytes Flow Command Package
; F900 - F900 0 KBytes Resident Command Package
; F900 - F900 0 KBytes IO Package - no IOP
; F900 - F900 0 KBytes Resident User Space (no clk drvr needed)
; The remainder is for the Operating System. Exact sizes vary depending
; primarily on the Number and sizes of Hard Drive Partitions, typically:
; EF00 - F8FF 2.75 KBytes B/P BIOS (unbanked version)
; E580 - EEFF 3.375 KBytes ZSDOS 2.0 BDOS
; DD80 - E47F 2 KBytes ZCPR 4.1 Command Processor
; 0100 - C5FF ~50 KBytes Transient Program Area
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
;========================================================================
FALSE EQU 0
TRUE EQU NOT FALSE
YES EQU TRUE
NO EQU FALSE
; The External Stack is placed in the very top position in memory. It is
; mandatory for B/P Bios and ZCPR 3.3.
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
;EXTSTK EQU 0FBD0H ; ZCPR3 External Stack
EXTSTK EQU MEMTOP+1-48 ; ZCPR3 External Stack
EXTSTKS EQU YES
; ZCPR3 Named Directory Buffer definition.
; FE00 - FFAF 432 Bytes Named Directory Buffer -23 names
Z3NDIRS EQU 23 ; Number of Named Directory Elements
; F800 - F8FF 256 Bytes Named Directory Buffer - 14 NAMES
NDIRSZ EQU Z3NDIRS * 18 + 1
; (NDIR Size = Z3NDIRS * 18 + 1 = 433 Bytes)
Z3NDIR EQU ((EXTSTK-NDIRSZ)/256)*256 ; Start of Named Directory Buffer
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
; place it above the Environment. It is mandatory for ZCPR 3.3.
; FD00 - FDFF 256 Bytes
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5
Z3CL EQU Z3NDIR-Z3CLS-5 ; ZCPR3 Command Line Buffer
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
; FC00 - FCFF 256 Bytes Environment Descriptor
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
; FBFF 1 Byte Wheel byte
Z3WHLS EQU YES
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address
; The Path is mandatory for ZCPR 3.3.
; FBF4 - FBFE 11 Bytes Path (5 elements)
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
; This defines 5 2-byte Path Elements
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
EXTFCBS EQU YES
EXFCBSZ EQU 36
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
Z3MSGS EQU YES
Z3MSGSZ EQU 80 ; size of buffer
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
; F900 - FAFF 512 Bytes Flow Command Package
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 512 Bytes)
FCP EQU SHSTK-FCPS*128 ; Start of Flow Command Package
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
; F900 - F900 0 KBytes Resident Command Package
;RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
RCPS EQU 0 ; (RCP Size = 128 * RCPS = 2 kBytes)
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor
; IO Package definition. Set IOPS to 0 to eliminate IOP
;IOP EQU 0EC00H ; Start of IO Package
; F900 - F900 0 KBytes IO Package
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes)
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
;OPS DEFL 3 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
IOP EQU RCP-IOPS*128 ; Start of IO Package
;=========================================================================
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
; MUST BE PRESENT!
USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes)
;USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
; F900 - F900 0.75 KBytes Resident User Space
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY)
;--- End of Z3BASE.LIB ---


152
Source/BPBIOS/z3basen.lib
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@@ -1,152 +0,0 @@
; z3base.fp -- B/P Bios System Z3 Definition File for not or partially
; banked system with 32 byte external HBIOS proxy and
; internal proxy.
; This file is adapted from the basic Z3BASE.LIB configuration file used for
; most ZCPR33 systems. It has added the new definitions for the Resident
; User Space defined in B/P Bios descriptions.
;=========================================================================
;== NOTE: The Starting Address of the User Space marks the lower ==
;== base of memory and MUST be entered. B/P Bios Utilities use ==
;== this address to locate many portions of the operating system. ==
;=========================================================================
; To change your systems definition, first sketch out the memory map in the
; comment table, then set the equates to reflect the memory map, doing any
; required calculations for element sizes and required spaces. As an
; alternative, just leave this file alone and configure everything with
; the utilities provided. For example reserve top 1k for HBIOS and no IOP.
; FFE0 - FFFF 32 Bytes HBIOS RESERVED AREA (mini proxy)
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
; FE00 - FFAF 432 Bytes Named Directory Buffer
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer
; FC00 - FCFF 256 Bytes Environment Descriptor
; Bytes 00H-7FH: Z3 Parameters
; Bytes 80H-FFH: Z3 TCAP
; FBFF 1 Byte Wheel byte
; FBF4 - FAFE 11 Bytes Path (5 elements)
; FBD0 - FAF3 36 Bytes ZCPR3 External FCB
; FB80 - FACF 80 Bytes ZCPR3 Message Buffers
; FB00 - FA7F 128 Bytes ZCPR3 Shell Stack
; F900 - FAFF 512 Bytes Flow Command Package
; F100 - F8FF 2.0 KBytes Resident Command Package
; F100 - F100 0 KBytes IO Package - no IOP
; EE00 - F0FF 768 Bytes Resident User Space (room for clock driver)
; The remainder is for the Operating System. Exact sizes vary depending
; primarily on the Number and sizes of Hard Drive Partitions, typically:
; DC00 - EDFF 4.5 KBytes B/P BIOS (banked version)
; CE00 - DBFF 3.5 KBytes ZSDOS 1.0 BDOS
; C600 - CDFF 2 KBytes ZCPR 3.3 Command Processor
; 0100 - C5FF ~50 KBytes Transient Program Area
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
;========================================================================
FALSE EQU 0
TRUE EQU NOT FALSE
YES EQU TRUE
NO EQU FALSE
; The External Stack is placed in the very top position in memory. It is
; mandatory for B/P Bios and ZCPR 3.3.
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
;EXTSTK EQU 0FBD0H ; ZCPR3 External Stack
EXTSTK EQU MEMTOP+1-48 ; ZCPR3 External Stack
EXTSTKS EQU YES
; ZCPR3 Named Directory Buffer definition.
; FE00 - FFAF 432 Bytes Named Directory Buffer -23 names
Z3NDIRS EQU 23 ; Number of Named Directory Elements
; F800 - F8FF 256 Bytes Named Directory Buffer - 14 NAMES
NDIRSZ EQU Z3NDIRS * 18 + 1
; (NDIR Size = Z3NDIRS * 18 + 1 = 433 Bytes)
Z3NDIR EQU ((EXTSTK-NDIRSZ)/256)*256 ; Start of Named Directory Buffer
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
; place it above the Environment. It is mandatory for ZCPR 3.3.
; FD00 - FDFF 256 Bytes
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5
Z3CL EQU Z3NDIR-Z3CLS-5 ; ZCPR3 Command Line Buffer
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
; FC00 - FCFF 256 Bytes Environment Descriptor
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
; FBFF 1 Byte Wheel byte
Z3WHLS EQU YES
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address
; The Path is mandatory for ZCPR 3.3.
; FBF4 - FBFE 11 Bytes Path (5 elements)
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
; This defines 5 2-byte Path Elements
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
EXTFCBS EQU YES
EXFCBSZ EQU 36
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
Z3MSGS EQU YES
Z3MSGSZ EQU 80 ; size of buffer
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
; F900 - FAFF 512 Bytes Flow Command Package
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 512 Bytes)
FCP EQU SHSTK-FCPS*128 ; Start of Flow Command Package
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
; F100 - F8FF 2.0 KBytes Resident Command Package
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
;RCPS EQU 0 ; (RCP Size = 128 * RCPS = 2 kBytes)
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor
; IO Package definition. Set IOPS to 0 to eliminate IOP
;IOP EQU 0EC00H ; Start of IO Package
; F100 - F100 0 KBytes IO Package
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes)
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
;OPS DEFL 3 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
IOP EQU RCP-IOPS*128 ; Start of IO Package
;=========================================================================
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
; MUST BE PRESENT!
;USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes)
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
; EE00 - F0FF 0.75 KBytes Resident User Space
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY)
;--- End of Z3BASE.LIB ---


149
Source/BPBIOS/z3baset.lib
View File

@@ -1,149 +0,0 @@
; z3base.fp -- B/P Bios System Z3 Definition File for not or partially
; banked system with 512 byte external HBIOS proxy (no
; internal proxy).
; This file is adapted from the basic Z3BASE.LIB configuration file used for
; most ZCPR33 systems. It has added the new definitions for the Resident
; User Space defined in B/P Bios descriptions and modified for an HBIOS
; implementation with a full external HBIOS proxy (i.e. proxy not internal
; to BPBIOS).
;
;=========================================================================
;== NOTE: The Starting Address of the User Space marks the lower ==
;== base of memory and MUST be entered. B/P Bios Utilities use ==
;== this address to locate many portions of the operating system. ==
;=========================================================================
; To change your systems definition, first sketch out the memory map in the
; comment table, then set the equates to reflect the memory map, doing any
; required calculations for element sizes and required spaces. As an
; alternative, just leave this file alone and configure everything with
; the utilities provided.
; FE00 - FFFF 512 Bytes HBIOS proxy AREA in the top of ram
; FD00 - FDFF 256 Bytes Multiple Command Line Buffer
; FC00 - FCFF 256 Bytes Environment Descriptor
; Bytes 00H-7FH: Z3 Parameters
; Bytes 80H-FFH: Z3 TCAP
; FBFF 1 Byte Wheel byte
; FBF4 - FBFE 11 Bytes Path (5 elements)
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack (4x32)
; FAD0 - FAFF 48 Bytes ZCPR3 External Stack (must be 48 bytes)
; F900 - FACF 464 Bytes Named Directory Buffer (25 entries)
; F700 - F9FF 512 Bytes Flow Command Package
; EF00 - F6FF 2.0 KBytes Resident Command Package
; EF00 - EF00 0 KBytes IO Package - no IOP
; EC00 - EEFF 768 Bytes Resident User Space (room for clock driver)
; The remainder is for the Operating System. Exact sizes vary depending
; primarily on the Number and sizes of Hard Drive Partitions, typically:
; E100 - EBFF 4.5 KBytes B/P BIOS (banked version)
; D300 - E0FF 3.5 KBytes ZSDOS 1.0 BDOS
; CB00 - D2FF 2 KBytes ZCPR 3.4 Command Processor
; 0100 - C5FF ~50 KBytes Transient Program Area
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
;========================================================================
FALSE EQU 0
TRUE EQU NOT FALSE
YES EQU TRUE
NO EQU FALSE
; The Multiple Command Line Buffer is mandatory for ZCPR 3.3. 3.4 & 4.1.
; FD00 - FDCF 208 Bytes
;Z3CL EQU 0FB00H ; ZCPR3 Command Line Buffer
Z3CLS EQU 256-5 ; Size of Command Line Buffer-5
Z3CL EQU MEMTOP+1-Z3CLS-5 ; ZCPR3 Command Line Buffer
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
; FC00 - FCFF 256 Bytes Environment Descriptor
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
Z3ENV EQU (Z3CL-Z3ENVS*128) and 0FF00H
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
; FBFF 1 Byte Wheel byte
Z3WHLS EQU YES
Z3WHL EQU Z3ENV-1 ; Wheel Byte Address
; The Path is mandatory for ZCPR 3.3.
; FBF4 - FBFE 11 Bytes Path (5 elements)
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
; This defines 5 2-byte Path Elements
EXPATH EQU Z3WHL-EXPATHS*2-1 ; External Path starting Address
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
; FBD0 - FBF3 36 Bytes ZCPR3 External FCB
EXTFCBS EQU YES
EXFCBSZ EQU 36
EXTFCB EQU EXPATH-EXFCBSZ ; 36-Byte ZCPR3 External FCB
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
; FB80 - FBCF 80 Bytes ZCPR3 Message Buffers
Z3MSGS EQU YES
Z3MSGSZ EQU 80 ; size of buffer
Z3MSG EQU EXTFCB-Z3MSGSZ ; 80-Byte ZCPR3 Message Buffer
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
; FB00 - FB7F 128 Bytes ZCPR3 Shell Stack
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
SHSTK EQU Z3MSG-SHSTKS*SHSIZE ; Shell Stack Starting Address
; The External Stack is mandatory for B/P Bios and ZCPR 3.3, 3.4 & 4.1
; FAD0 - FAFF 48 Bytes ; ZCPR3 External Stack (must be 48 bytes)
;EXTSTK EQU 0FAD0H ; ZCPR3 External Stack
EXTSTK EQU SHSTK-48 ; ZCPR3 External Stack
EXTSTKS EQU YES
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
; the named directory buffer.
; F900 - FACF 464 Bytes ; Named Directory Buffer - 25 NAMES
Z3NDIRS EQU 25 ; Number of Named Directory Elements
NDIRSZ EQU Z3NDIRS * 18 + 1
; (NDIR Size = Z3NDIRS * 18 + 1 = 451 Bytes)
Z3NDIR EQU SHSTK-(NDIRSZ/256+1)*256 ; Start of Named Directory Buffer
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
; F700 - F8FF 512 Bytes Flow Command Package
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
;FCPS EQU 0 ; (FCP Size = 128 * FCPS = 0 Bytes)
FCP EQU Z3NDIR-FCPS*128 ; Start of Flow Command Package
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
; EF00 - F6FF 2.0 KBytes Resident Command Package
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
;RCPS EQU 0 ; (RCP Size = 128 * RCPS = 0 kBytes)
RCP EQU FCP-RCPS*128 ; Start of Resident Command Processor
; IO Package definition. Set IOPS to 0 which eliminates IOP
;IOP EQU 0EC00H ; Start of IO Package
; EF00 - EF00 0 KBytes IO Package
IOPS DEFL 0 ; (IOP Size = 128 * IOPS = 0 kBytes)
;IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
;IOPS DEFL 10 ; (IOP Size = 128 * IOPS = 1.25 kBytes)
IOP EQU RCP-IOPS*128 ; Start of IO Package
;=========================================================================
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
; MUST BE PRESENT!
;USPCS EQU 0 ; (USPC Size = 128 * USPCS = 0 kBytes)
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
; EC00 - EEFF 0.75 KBytes Resident User Space
USPC EQU IOP-USPCS*128 ; Start of Resident User Space (MANDATORY)
;--- End of Z3BASE.LIB ---


16
Source/BPBIOS/zst.zex Normal file
View File

@@ -0,0 +1,16 @@
;; Set the ZCPR and ZSDOS paths
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0
;; Load ZCPR segments
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,NZDEC23D.Z3T
;; Load date/time extension
ldtimec
;; Initialize the RAM disk if needed and copy some useful file there
if ~EX A0:-RAM.000
putds -d=A:
fileattr a0:*.dat /nd
save 0 a:-ram.000
rcopy ramfiles.txt A0: /Q
fi
;; Load the command history shell and editor
lsh


20
Source/BPBIOS/zstf.zex
View File

@@ -1,16 +1,16 @@
;; set the Zsystem and ZSDOS paths
;; Set the ZCPR and ZSDOS paths
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0
;; enable clock and turn off last access stamping
;; Enable clock and turn off last access stamping
zscfg2 cb +a-
;; load Zsystem segments
jetldr BPBIO.NDR,nzdec23d.z3t,fcp-4t.zrl
;; initialize the RAM disk if needed and copy some useful file there
if ~EX A0:-ram.000
;; Load ZCPR segments
jetldr FCP-4T.ZRL,BPBIO.NDR,NZDEC23D.Z3T
;; Initialize the RAM disk if needed and copy some useful file there
if ~EX A0:-RAM.000
putds -d=A:
fileattr a0:*.dat /nd
save 0 a0:-ram.000
RCOPY RAMFILES.TXT A0: /Q
rcopy ramfiles.txt A0: /Q
fi
;; load the command history shell and editor
LSH

;; Load the command history shell and editor
lsh


13
Source/BPBIOS/zstn.zex
View File

@@ -1,13 +0,0 @@
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,nzdec23d.z3t
ldtimee
;; initialize ram drive if needed
IF ~EX A0:-RAM.000
putds -d=A:
fileattr a0:*.dat /nd
save 0 a:-ram.000
RCOPY RAMFILES.TXT A0: /Q
FI
;; load command history shell and editor
LSH


13
Source/BPBIOS/zstt.zex
View File

@@ -1,13 +0,0 @@
C15:ZPATH $$$$ A0 B0 C15 C0 /D=$$$$ C15 C0
jetldr RCP-16H.ZRL,FCP-4T.ZRL,BPBIO.NDR,nzdec23d.z3t
ldtimec
;; initialize ram drive if needed
IF ~EX A0:-RAM.000
putds -d=A:
fileattr a0:*.dat /nd
save 0 a:-ram.000
RCOPY RAMFILES.TXT A0: /Q
FI
;; load command history shell and editor
LSH


2
Source/Images/d_bp.txt
View File

@@ -54,7 +54,7 @@ cpnet12/*.* 4:
# Add Common Applications
#
Common/All/*.* 15:
Common/CPM22/*.* 0:
Common/CPM22/*.* 15:
#Common/Z/u10/*.* 10:
Common/Z/u14/*.* 14:
Common/Z/u15/*.* 15:

BIN
Source/Images/d_bp/u15/save.com
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Binary file not shown.

2
Source/ver.inc
View File

@@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.124"
#DEFINE BIOSVER "3.1.1-pre.125"

2
Source/ver.lib
View File

@@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.124"
db "3.1.1-pre.125"
endm