Preliminary Zilog SCC Support

- Interrupts and flow control not yet implemented.

ReadMe.md

@@ -7,7 +7,7 @@
 **RomWBW Introduction** \
 Version 3.6 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-28 Oct 2025
+29 Oct 2025
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Introduction
 Wayne Warthen (wwarthen@gmail.com)
-28 Oct 2025
+29 Oct 2025
 
 
 

Source/Doc/Hardware.md

@@ -441,17 +441,19 @@ Z80-based S100 Modular System
 
 #### Supported Hardware
 
+- FP: LEDIO=5
+- PLDSER: IO=172
+- SCC MODE=SZ80, IO=160, CHANNEL A
+- SCC MODE=SZ80, IO=160, CHANNEL B
 - SCON: IO=0
 - ESPSD: IO=128, PRIMARY
 - ESPSD: IO=128, SECONDARY
 - MD: TYPE=RAM
-- PPIDE: MODE=STD, IO=48, MASTER
-- PPIDE: MODE=STD, IO=48, SLAVE
-- PPIDE: MODE=S100A, IO=56, MASTER
-- PPIDE: MODE=S100A, IO=56, SLAVE
-- PPIDE: MODE=S100B, IO=56, MASTER
-- PPIDE: MODE=S100B, IO=56, SLAVE
-- SD: MODE=FZ80, IO=108, UNITS=2
+- PPIDE: MODE=S100A, IO=48, MASTER
+- PPIDE: MODE=S100A, IO=48, SLAVE
+- PPIDE: MODE=S100B, IO=48, MASTER
+- PPIDE: MODE=S100B, IO=48, SLAVE
+
 
 #### Notes:
 
@@ -481,9 +483,13 @@ A T35 FPGA Z80 based S100 SBC
 
 #### Supported Hardware
 
+- FP: LEDIO=255
 - DS5RTC: RTCIO=104, IO=104
-- SSER: IO=52
-- LPT: MODE=S100, IO=199
+- TSER: IO=53
+- PLDSER: IO=172
+- SCC MODE=SZ80, IO=160, CHANNEL A
+- SCC MODE=SZ80, IO=160, CHANNEL B
+- LPT: MODE=T35, IO=199
 - TVGA: IO=192, KBD MODE=T35, KBD IO=3
 - KBD: ENABLED
 - SCON: IO=0
@@ -2365,8 +2371,11 @@ may be discovered by RomWBW in your system.
 | PPPCON    | ParPortProp Serial Console Interface                   |
 | PRPCON    | PropIO Serial Console Interface                        |
 | SCON      | S100 Console                                           |
-| SIO       | Zilog Serial Port Interface                            |
+| SIO       | Zilog Serial Input/Output Controller (SIO)             |
+| SCC       | Zilog Serial Communications Controller (SCC)           |
 | SSER      | Simple Serial Interface                                |
+| TSER      | Trion FPGA Serial Interface                            |
+| PLDSER    | PLD USB Serial Interface                               |
 | UART      | 16C550 Family Serial Interface                         |
 | USB-FIFO  | FT232H-based ECB USB FIFO                              |
 | Z2U       | Zilog Z280 CPU Built-in Serial Ports                   |
@@ -2376,16 +2385,20 @@ discovers for the initial console.  The following character devices are
 scanned in the order shown.  The available character devices depend on
 the active platform and configuration.
 
-#. SSER: Simple Serial Interface
 #. ASCI: Zilog Z180 CPU Built-in Serial Ports
 #. Z2U: Zilog Z280 CPU Built-in Serial Ports
 #. UART: 16C550 Family Serial Interface
 #. DUART: SCC2681 or compatible Dual UART
-#. SIO: Zilog Serial Port Interface
+#. SIO: Zilog Serial Port Interface (SIO)
+#. SCC: Zilog Serial Port Interface (SCC)
 #. EZ80UART: eZ80 Serial Port Interface
 #. ACIA: MC68B50 Asynchronous Communications Interface Adapter
+#. SSER: Simple Serial Interface
+#. TSER: Trion FPGA Serial Interface
+#. PLDSER: PLD USB Serial Interface
 #. USB-FIFO: FT232H-based ECB USB FIFO
 
+
 ## Disk
 
 | **ID**    | **Description**                                        |

Source/HBIOS/Config/SZ80_std.asm

@@ -43,7 +43,7 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
-#DEFINE DEFSERCFG	SER_9600_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+#DEFINE DEFSERCFG	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_SZ80.asm"
 ;

Source/HBIOS/cfg_MASTER.asm

@@ -302,6 +302,28 @@ SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.EQU	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.EQU	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.EQU	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.EQU	2		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.EQU	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCC0MODE	.EQU	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.EQU	$FF		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.EQU	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.EQU	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.EQU	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.EQU	4915200		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.EQU	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.EQU	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.EQU	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.EQU	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.EQU	4915200		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.EQU	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.EQU	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.EQU	4915200		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.EQU	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.EQU	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
 XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)

Source/HBIOS/cfg_SZ80.asm

@@ -45,7 +45,7 @@
 #DEFINE PLATFORM_NAME	"S100 Z80", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
-#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+#DEFINE DEFSERCFG	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
@@ -253,6 +253,28 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	TRUE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.SET	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.SET	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.SET	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.SET	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.SET	4915200		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.SET	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.SET	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.SET	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.SET	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.SET	4915200		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.SET	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.SET	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.SET	4915200		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.SET	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.SET	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)

Source/HBIOS/hbios.asm

@@ -4102,6 +4102,9 @@ HB_PCINITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_PREINIT
 #ENDIF
+#IF (SCCENABLE)
+	.DW	SCC_PREINIT
+#ENDIF
 #IF (EZ80UARTENABLE)
 	.DW	EZUART_PREINIT
 #ENDIF
@@ -4228,6 +4231,9 @@ HB_INITTBL:
 #IF (SIOENABLE)
 	.DW	SIO_INIT
 #ENDIF
+#IF (SCCENABLE)
+	.DW	SCC_INIT
+#ENDIF
 #IF (EZ80UARTENABLE)
 	.DW	EZUART_INIT
 #ENDIF
@@ -8953,6 +8959,15 @@ SIZ_SIO		.EQU	$ - ORG_SIO
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (SCCENABLE)
+ORG_SCC		.EQU	$
+  #INCLUDE "scc.asm"
+SIZ_SCC		.EQU	$ - ORG_SCC
+		MEMECHO	"SCC occupies "
+		MEMECHO	SIZ_SCC
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ACIAENABLE)
 ORG_ACIA	.EQU	$
   #INCLUDE "acia.asm"

Source/HBIOS/hbios.inc

@@ -398,6 +398,7 @@ CIODEV_SSER	.EQU	$0F
 CIODEV_EZ80UART	.EQU	$10
 CIODEV_PLDSER	.EQU	$11
 CIODEV_TSER	.EQU	$12
+CIODEV_SCC	.EQU	$13
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;

Source/HBIOS/invntdev.asm

@@ -639,6 +639,7 @@ PS_SDSSER	.TEXT	"SSER$"
 PS_SDEZ80	.TEXT	"EZ80$"
 PS_SDPLDSER	.TEXT	"PLDSER$"
 PS_SDTSER	.TEXT	"TSER$"
+PS_SDSCC	.TEXT	"SCC$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;

Source/HBIOS/std.asm

@@ -161,6 +161,12 @@ SIOMODE_SMB	.EQU	3		; RCBUS SIO MODULE (SCOTT BAKER)
 SIOMODE_ZP	.EQU	4		; ECB-ZILOG PERIPHERALS BOARD
 SIOMODE_Z80R	.EQU	5		; SIO A/B SWAPPED
 ;
+; SIO MODE SELECTIONS
+;
+SCCMODE_NONE	.EQU	0
+SCCMODE_STD	.EQU	1		; STD REG CFG (KIO)
+SCCMODE_SZ80	.EQU	2		; S100 SERIAL I/O
+;
 ; TYPE OF CONSOLE BELL TO USE
 ;
 CONBELL_NONE	.EQU	0

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	6
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.6.0-dev.37"
+#DEFINE BIOSVER	"3.6.0-dev.38"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	6
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.6.0-dev.37"
+	db	"3.6.0-dev.38"
 	endm