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pull/419/merge v3.5.0-dev.75
Wayne Warthen 1 year ago
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  1. 3
      Doc/ChangeLog.txt
  2. BIN
      Doc/RomWBW Applications.pdf
  3. BIN
      Doc/RomWBW Disk Catalog.pdf
  4. BIN
      Doc/RomWBW Errata.pdf
  5. BIN
      Doc/RomWBW System Guide.pdf
  6. BIN
      Doc/RomWBW User Guide.pdf
  7. 2
      ReadMe.md
  8. 2
      ReadMe.txt
  9. 35
      Source/Doc/UserGuide.md
  10. 94
      Source/HBIOS/cfg_gmz180.asm

3
Doc/ChangeLog.txt
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@ -32,7 +32,8 @@ Version 3.5
- WBW: Substantial customization of NZ-COM disk image
- WBW: Refactor build post-processing (ZRC, ZZRCC, etc.)
- MAP: Improved section Real Time Clock in User Guide document
- WBW: Support for Hitachi HD44780-based LCD display
- WBW: Support for Hitachi HD44780-based LCD display
- DRJ: Added support for Genesis STD Bus Z180 platform
Version 3.4
-----------

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Doc/RomWBW Applications.pdf
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Doc/RomWBW Disk Catalog.pdf
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Doc/RomWBW Errata.pdf
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Doc/RomWBW System Guide.pdf
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2
ReadMe.md
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@ -3,7 +3,7 @@
**RomWBW ReadMe** \
Version 3.5 \
Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
03 Sep 2024
04 Sep 2024
# Overview

2
ReadMe.txt
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@ -1,6 +1,6 @@
RomWBW ReadMe
Wayne Warthen (wwarthen@gmail.com)
03 Sep 2024
04 Sep 2024

35
Source/Doc/UserGuide.md
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@ -262,6 +262,7 @@ is discussed in [Customizing RomWBW].
| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 |
| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 |
| [S100 FPGA Z80]^9^ | S100 | FZ80_std.rom | 9600 |
| [Genesis STD Z180]^12^ | STD | GMZ180_std.rom | 115200 |
| ^1^Designed by Andrew Lynch
| ^2^Designed by Sergey Kiselev
@ -274,6 +275,7 @@ is discussed in [Customizing RomWBW].
| ^9^Designed by John Monahan
| ^10^Designed by Les Bird
| ^11^Designed by Alan Cox
| ^12^Designed by Doug Jackson
RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
including RC26, RC40, RC80, and BP80.
@ -5382,7 +5384,7 @@ the RomWBW HBIOS configuration.
- CH: IO=60
- CHUSB: IO=62
- CHUSB: IO=60
S- MD: TYPE=RAM
- MD: TYPE=RAM
- MD: TYPE=ROM
- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@ -6097,6 +6099,36 @@ SD: MODE=FZ80, IO=108, UNITS=2
- Requires matching FPGA code
### Genesis STD Z180
#### ROM Image File: GMZ180_std.rom
| | |
|-------------------|---------------|
| Default CPU Speed | 18.432 MHz |
| Interrupts | Mode 2 |
| System Timer | Z180 |
| Serial Default | 115200 Baud |
| Memory Manager | Z180 |
| ROM Size | 512 KB |
| RAM Size | 512 KB |
##### Supported Hardware (see [Appendix B - Device Summary]):
DSRTC: MODE=STD, IO=132
INTRTC: ENABLED
ASCI: IO=192, INTERRUPTS ENABLED
ASCI: IO=193, INTERRUPTS ENABLED
MD: TYPE=RAM
MD: TYPE=ROM
IDE: MODE=GIDE, IO=32, MASTER
IDE: MODE=GIDE, IO=32, SLAVE
SD: MODE=GM, IO=132, UNITS=1
##### Notes:
- CPU speed will be dynamically measured at startup if DSRTC is present
## Appendix B - Device Summary
The table below briefly describes each of the possible devices that
@ -6123,6 +6155,7 @@ may be discovered by RomWBW in your system.
| EMM | Disk | Disk drive on Parallel Port emm interface (Zip Drive) |
| FD | Disk | 8272 or compatible Floppy Disk Controller |
| FP | System | Simple LED & Switch Front Panel |
| FV | Video | S100 FPGA Z80 Onboard VGA/Keyboard |
| GDC | Video | uPD7220 Video Display Controller |
| HDSK | Disk | SIMH Simulator Hard Disk |
| ICM | DsKy | ICM7218-based Display/Keypad on PPI |

94
Source/HBIOS/cfg_gmz180.asm
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@ -16,52 +16,52 @@
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RTCIO .EQU $84 ; RTC LATCH REGISTER ADR
;
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
;
PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
;
@ -70,18 +70,18 @@ SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
;
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED
FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED
;
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
;
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU]
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
@ -90,10 +90,10 @@ ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL
LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER
LCDDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY
;
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
@ -122,16 +122,16 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
;
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
;
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
;
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
SSERDATA .EQU $FF ; SSER: DATA PORT
SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK
@ -237,13 +237,13 @@ RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDE0MODE .EQU IDEMODE_GIDE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
@ -271,15 +271,15 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
SDMODE .EQU SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
;
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
@ -307,30 +307,30 @@ PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
;
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
;
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
;
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
;
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
;
@ -338,10 +338,10 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
;
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
;
@ -349,9 +349,9 @@ AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;

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