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eZ80: uart and hbios banking code updated to support the eZ80 for RC2014 configuration

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This commit is contained in:
Dean Netherton
2024-06-02 19:41:35 +10:00
parent 2bc807edc8
commit d358c8bc1c
5 changed files with 102 additions and 74 deletions
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35
Source/Doc/SystemGuide.md
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@@ -393,23 +393,24 @@ All character units are assigned a Device Type ID which indicates
the specific hardware device driver that handles the unit. The table
below enumerates these values.
| **Device Type** | **ID** | **Description** | **Driver** |
|-----------------|-------:|------------------------------------------|------------|
| CIODEV_UART | 0x00 | 16C550 Family Serial Interface | uart.asm |
| CIODEV_ASCI | 0x01 | Z180 Built-in Serial Ports | asci.asm |
| CIODEV_TERM | 0x02 | Terminal | ansi.asm |
| CIODEV_PRPCON | 0x03 | PropIO Serial Console Interface | prp.asm |
| CIODEV_PPPCON | 0x04 | ParPortProp Serial Console Interface | ppp.asm |
| CIODEV_SIO | 0x05 | Zilog Serial Port Interface | sio.asm |
| CIODEV_ACIA | 0x06 | MC68B50 Asynchronous Interface | acia.asm |
| CIODEV_PIO | 0x07 | Zilog Parallel Interface Controller | pio.asm |
| CIODEV_UF | 0x08 | FT232H-based ECB USB FIFO | uf.asm |
| CIODEV_DUART | 0x09 | SCC2681 Family Dual UART | duart.asm |
| CIODEV_Z2U | 0x0A | Zilog Z280 Built-in Serial Ports | z2u.asm |
| CIODEV_LPT | 0x0B | Parallel I/O Controller | lpt.asm |
| CIODEV_ESPCON | 0x0B | ESP32 VGA Console | esp.asm |
| CIODEV_ESPSER | 0x0B | ESP32 Serial Port | esp.asm |
| CIODEV_SCON | 0x0B | S100 Console | scon.asm |
| **Device Type** | **ID** | **Description** | **Driver** |
|-----------------|-------:|------------------------------------------|--------------|
| CIODEV_UART | 0x00 | 16C550 Family Serial Interface | uart.asm |
| CIODEV_ASCI | 0x01 | Z180 Built-in Serial Ports | asci.asm |
| CIODEV_TERM | 0x02 | Terminal | ansi.asm |
| CIODEV_PRPCON | 0x03 | PropIO Serial Console Interface | prp.asm |
| CIODEV_PPPCON | 0x04 | ParPortProp Serial Console Interface | ppp.asm |
| CIODEV_SIO | 0x05 | Zilog Serial Port Interface | sio.asm |
| CIODEV_ACIA | 0x06 | MC68B50 Asynchronous Interface | acia.asm |
| CIODEV_PIO | 0x07 | Zilog Parallel Interface Controller | pio.asm |
| CIODEV_UF | 0x08 | FT232H-based ECB USB FIFO | uf.asm |
| CIODEV_DUART | 0x09 | SCC2681 Family Dual UART | duart.asm |
| CIODEV_Z2U | 0x0A | Zilog Z280 Built-in Serial Ports | z2u.asm |
| CIODEV_LPT | 0x0B | Parallel I/O Controller | lpt.asm |
| CIODEV_ESPCON | 0x0B | ESP32 VGA Console | esp.asm |
| CIODEV_ESPSER | 0x0B | ESP32 Serial Port | esp.asm |
| CIODEV_SCON | 0x0B | S100 Console | scon.asm |
| CIODEV_EZ80UART | 0x10 | eZ80 Built-in UART0 Interface | ez80uart.asm |
Character devices can usually be configured with line characteristics
such as speed, framing, etc. A word value (16 bit) is used to describe

21
Source/HBIOS/cfg_rcez80.asm
View File

@@ -30,7 +30,7 @@ AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
@@ -49,7 +49,7 @@ RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
@@ -107,7 +107,7 @@ PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
@@ -136,7 +136,7 @@ DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
@@ -146,14 +146,14 @@ UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
;
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
@@ -166,6 +166,7 @@ ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
;
EZ80UARTENABLE .EQU TRUE ; EZ80UART: ENABLE EZ80 UART SERIAL DRIVER (EZ80UART.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
@@ -203,7 +204,7 @@ EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDTRACE .EQU 2 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
@@ -259,7 +260,7 @@ SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
;
CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT
CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT
CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -272,9 +273,9 @@ CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK
CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;

107
Source/HBIOS/ez80uart.asm
View File

@@ -5,82 +5,101 @@
;
UART0_LSR .EQU $C5
UART0_THR .EQU $C0
UART0_THR .EQU $C0
UART0_RBR .EQU $C0
LSR_THRE .EQU $20
LSR_DR .EQU $01
#DEFINE IN0_A(p) .DB $ED,$38,p
#DEFINE OUT0_A(p) .DB $ED,$39,p
#DEFINE IN0_B(p) .DB $ED,$00,p
#DEFINE IN0_C(p) .DB $ED,$08,p
#DEFINE IN0_D(p) .DB $ED,$10,p
#DEFINE IN0_E(p) .DB $ED,$18,p
#DEFINE IN0_H(p) .DB $ED,$20,p
#DEFINE IN0_L(p) .DB $ED,$28,p
; #DEFINE CALLIL(a,b) .DB $5B,$CD \ .DW b \ .DB b
#DEFINE OUT0_A(p) .DB $ED,$39,p
#DEFINE OUT0_B(p) .DB $ED,$01,p
#DEFINE OUT0_C(p) .DB $ED,$09,p
#DEFINE OUT0_D(p) .DB $ED,$11,p
#DEFINE OUT0_E(p) .DB $ED,$19,p
#DEFINE OUT0_H(p) .DB $ED,$21,p
#DEFINE OUT0_L(p) .DB $ED,$29,p
; call.IL $01FFxx WHERE xx IS r*4
#DEFINE FIRMWARE_FN(r) .DB $5B,$CD \ .DW ($FF00+(r*4)) \ .DB $01
EZUART_PREINIT:
LD E, 'A'
CALL EZUART_OUT
LD E, 'B'
CALL EZUART_OUT
LD E, 'C'
CALL EZUART_OUT
LD E, 'D'
CALL EZUART_OUT
LD E, 13
CALL EZUART_OUT
LD E, 10
CALL EZUART_OUT
FIRMWARE_FN(0)
LD BC, EZUART_FNTBL
LD DE, EZUART_CFG
CALL CIO_ADDENT
LD (EZUART_ID), A
FIRMWARE_FN(0)
XOR A
RET
EZUART_INIT:
LD E, '1'
CALL EZUART_OUT
LD E, '2'
CALL EZUART_OUT
LD E, '3'
CALL EZUART_OUT
LD E, '4'
CALL EZUART_OUT
LD E, 13
CALL EZUART_OUT
LD E, 10
CALL EZUART_OUT
FIRMWARE_FN(1)
; ;call.il, $001000
; .db $5B,$CD
; .dw $FF00
; .db $01
XOR A
RET
EZUART_IN:
;
; RETRIEVE THE NEXT CHARACTER FROM THE UART AND RETURN IN E
EZUART_IN:
IN0_A (UART0_LSR) ; CHECK FOR RX READY
AND LSR_DR
JR Z, EZUART_IN
IN0_E (UART0_RBR) ; GET THE CHAR
XOR A ; SIGNAL SUCCESS
RET
; OUT CHAR IN E
EZUART_OUT:
; WAIT FOR UART TO BE READY FOR TX
WAIT_FOR_TX_READY:
; IN0 A,(UART0_LSR) ; /*ED38C5*/
IN0_A (UART0_LSR)
IN0_A (UART0_LSR) ; WAIT FOR TX READY
AND LSR_THRE
JR Z,WAIT_FOR_TX_READY
JR Z, EZUART_OUT
; SEND THE CHAR
LD A, E
; OUT0 (UART0_LSR),A ; ED39C0
OUT0_A (UART0_THR)
OUT0_E (UART0_THR) ; SEND THE CHAR
XOR A ; SIGNAL SUCCESS
RET
EZUART_IST:
IN0_A (UART0_LSR) ; CHECK FOR RX READY
AND LSR_DR
RET
EZUART_OST:
IN0_A (UART0_LSR) ; WAIT FOR TX READY
AND LSR_THRE
RET Z
LD A, 1
RET
EZUART_INITDEV:
EZUART_QUERY:
EZUART_DEVICE:
LD A, 0 ; NOT IMPLEMENTED ERROR
RET
EZUART_DEVICE:
LD D, CIODEV_EZ80UART ; D := DEVICE TYPE
LD E, (IY) ; E := PHYSICAL UNIT
LD C, 0 ; C := DEVICE TYPE, 0x00 IS RS-232
LD HL, 0 ; H := MODE, L := BASE I/O ADDRESS
XOR A ; SIGNAL SUCCESS
RET
EZUART_CFG:
EZUART_ID: .DB 0
EZUART_FNTBL:
.DW EZUART_IN

10
Source/HBIOS/hbios.asm
View File

@@ -623,13 +623,14 @@ HBX_ROM:
;
HBX_ROM:
RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
#IF (CPU_FAM == CPU_EZ80)
PUSH BC
#IF (CPUFAM == CPU_EZ80)
EXX
LD BC,EZ80IOBASE<<8+MPGSEL_0
OUT (C),A ; BANK_0: 0K - 16K
INC A
INC BC ; BC = MPGSEL_0
OUT (C),A ; BANK_1: 16K - 32K
EXX
#ELSE
OUT (MPGSEL_0),A ; BANK_0: 0K - 16K
INC A ;
@@ -2191,6 +2192,10 @@ HB_CLRIVT_Z:
LD L,4 ; WE ARE Z280
;
#ENDIF
#IF (CPUFAM == CPU_EZ80)
LD L,5
#ENDIF
;
HB_CPU1:
LD A,L
@@ -7800,6 +7805,7 @@ HB_CPU_STR: .TEXT " Z80$"
.TEXT " Z8S180-K$"
.TEXT " Z8S180-N$"
.TEXT " Z80280$"
.TEXT " eZ80$"
;
PS_STRNUL .TEXT "--$" ; DISPLAY STRING FOR NUL VALUE
;

3
Source/HBIOS/hbios.inc
View File

@@ -187,7 +187,7 @@ DIAG_7SEG .EQU 4 ; 7-SEGMENT
DIAG_FLASH .EQU 5 ; FLASH
DIAG_TRIG .EQU 6 ; TRIGGER
;
DIAG_DISP .EQU DIAG_PROG ; DEFAULT
DIAG_DISP .EQU DIAG_BINARY ; DEFAULT
;
#IF (DIAG_DISP == DIAG_PROG)
DIAG_00 .EQU 00000000B
@@ -323,6 +323,7 @@ CIODEV_ESPCON .EQU $0C
CIODEV_ESPSER .EQU $0D
CIODEV_SCON .EQU $0E
CIODEV_EF .EQU $0F
CIODEV_EZ80UART .EQU $10
;
; SUB TYPES OF CHAR DEVICES
;