From d4a542150b4cb152551ab20dcad8eefc250b35eb Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Thu, 8 Jul 2021 12:03:32 -0700 Subject: [PATCH] DSKYng Support - DSKYng now has same features as original DSKY including debug monitor - Added support for MBS LEDs - Elevated MBS to a platform instead of just a sub-config of SBC --- Doc/ChangeLog.txt | 3 + Source/Apps/tstdskng.asm | 4 +- Source/HBIOS/Build.ps1 | 9 +- Source/HBIOS/Build.sh | 10 +- .../HBIOS/Config/{SBC_mbc.asm => MBC_std.asm} | 8 +- Source/HBIOS/Makefile | 4 +- Source/HBIOS/cfg_dyno.asm | 6 +- Source/HBIOS/cfg_ezz80.asm | 6 +- Source/HBIOS/cfg_master.asm | 14 +- Source/HBIOS/cfg_mbc.asm | 231 ++++++++ Source/HBIOS/cfg_mk4.asm | 13 +- Source/HBIOS/cfg_n8.asm | 17 +- Source/HBIOS/cfg_rcz180.asm | 6 +- Source/HBIOS/cfg_rcz280.asm | 6 +- Source/HBIOS/cfg_rcz80.asm | 6 +- Source/HBIOS/cfg_sbc.asm | 17 +- Source/HBIOS/cfg_scz180.asm | 6 +- Source/HBIOS/cfg_una.asm | 2 +- Source/HBIOS/cfg_zeta.asm | 18 +- Source/HBIOS/cfg_zeta2.asm | 18 +- Source/HBIOS/dbgmon.asm | 47 +- Source/HBIOS/dsky.asm | 59 +- Source/HBIOS/dskyng.asm | 561 ++++++++++++++++++ Source/HBIOS/hbios.asm | 71 ++- Source/HBIOS/imgpad1.asm | 12 - Source/HBIOS/pio.asm | 6 +- Source/HBIOS/ppide.asm | 27 + Source/HBIOS/ppp.asm | 12 +- Source/HBIOS/romldr.asm | 42 +- Source/HBIOS/sd.asm | 8 +- Source/HBIOS/std.asm | 18 +- Source/ver.inc | 2 +- Source/ver.lib | 2 +- 33 files changed, 1127 insertions(+), 144 deletions(-) rename Source/HBIOS/Config/{SBC_mbc.asm => MBC_std.asm} (88%) create mode 100644 Source/HBIOS/cfg_mbc.asm create mode 100644 Source/HBIOS/dskyng.asm delete mode 100644 Source/HBIOS/imgpad1.asm diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 4c990851..18bde264 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -36,6 +36,9 @@ Version 3.1.1 - L?N: Slightly enhanced ZCPRD&J w/ a couple bug fixes - L?N: UNZIPZ4 which handles most modern ZIP file compression algorithms - AJL: Preliminary support for MBC systems +- WBW: Added preliminary support for DSKYng +- WBW: Elevated MBC to a platform +- WBW: Added support for MBC user LEDs Version 3.1 ----------- diff --git a/Source/Apps/tstdskng.asm b/Source/Apps/tstdskng.asm index 32299cc6..d1abd87e 100644 --- a/Source/Apps/tstdskng.asm +++ b/Source/Apps/tstdskng.asm @@ -26,9 +26,9 @@ PPI_BASE: .EQU $60 ; PPI BASE IO PORT ; LED SEGMENTS (BIT VALUES) ; ; +--01--+ -; 20 02 +; 20 02 ; +--40--+ -; 10 04 +; 10 04 ; +--08--+ 80 ; ; KEY CODE MAP (KEY CODES) --CCCRRR diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index 4e146a79..dc192246 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -19,7 +19,7 @@ param([string]$Platform = "", [string]$Config = "", [int]$RomSize = 512, [string # setup mechanism so that multiple configuration are not needed. When building for UNA, the pre-built # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA" $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO" $PlatformListZ280 = "RCZ280" @@ -183,7 +183,6 @@ if ($Platform -ne "UNA") Asm 'tastybasic' Asm 'game' Asm 'usrrom' - Asm 'imgpad1' Asm 'imgpad2' } @@ -194,15 +193,15 @@ if ($Platform -ne "UNA") "Building ${RomName} output files..." # Build 32K OS chunk containing the loader, debug monitor, and two OS images -Concat 'romldr.bin', 'eastaegg.bin','dbgmon.bin', "..\cpm22\cpm_${Bios}.bin", "..\zsdos\zsys_${Bios}.bin" osimg.bin +Concat 'romldr.bin', 'dbgmon.bin', "..\cpm22\cpm_${Bios}.bin", "..\zsdos\zsys_${Bios}.bin" osimg.bin # Build 20K OS chunk containing the loader, debug monitor, and one OS image -Concat 'romldr.bin', 'eastaegg.bin','dbgmon.bin', "..\zsdos\zsys_${Bios}.bin" osimg_small.bin +Concat 'romldr.bin','dbgmon.bin', "..\zsdos\zsys_${Bios}.bin" osimg_small.bin # Build second and third 32K chunks containing supplemental ROM apps (not for UNA) if ($Platform -ne "UNA") { - Concat '..\Forth\camel80.bin', 'nascom.bin', 'tastybasic.bin', 'game.bin', 'imgpad1.bin', 'usrrom.bin' osimg1.bin + Concat '..\Forth\camel80.bin', 'nascom.bin', 'tastybasic.bin', 'game.bin', 'eastaegg.bin', 'usrrom.bin' osimg1.bin Concat 'netboot.mod', 'imgpad2.bin' osimg2.bin } diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index 2009fc85..21adc95f 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -99,20 +99,20 @@ done cp ../Forth/camel80.bin . -make dbgmon.bin romldr.bin eastaegg.bin imgpad1.bin imgpad2.bin +make dbgmon.bin romldr.bin eastaegg.bin imgpad2.bin if [ $platform != UNA ] ; then - make nascom.bin tastybasic.bin game.bin usrrom.bin imgpad1.bin imgpad2.bin + make nascom.bin tastybasic.bin game.bin usrrom.bin imgpad2.bin make hbios_rom.bin hbios_app.bin hbios_img.bin fi echo "Building $romname output files..." -cat romldr.bin eastaegg.bin dbgmon.bin ../CPM22/cpm_$BIOS.bin ../ZSDOS/zsys_$BIOS.bin >osimg.bin -cat romldr.bin eastaegg.bin dbgmon.bin ../ZSDOS/zsys_$BIOS.bin >osimg_small.bin +cat romldr.bin dbgmon.bin ../CPM22/cpm_$BIOS.bin ../ZSDOS/zsys_$BIOS.bin >osimg.bin +cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$BIOS.bin >osimg_small.bin if [ $platform != UNA ] ; then - cat camel80.bin nascom.bin tastybasic.bin game.bin imgpad1.bin usrrom.bin >osimg1.bin + cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin usrrom.bin >osimg1.bin cat netboot.mod imgpad2.bin >osimg2.bin fi diff --git a/Source/HBIOS/Config/SBC_mbc.asm b/Source/HBIOS/Config/MBC_std.asm similarity index 88% rename from Source/HBIOS/Config/SBC_mbc.asm rename to Source/HBIOS/Config/MBC_std.asm index aa533c84..d0248be0 100644 --- a/Source/HBIOS/Config/SBC_mbc.asm +++ b/Source/HBIOS/Config/MBC_std.asm @@ -25,9 +25,9 @@ #DEFINE PLATFORM_NAME "Multi Board Computer" #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_sbc.asm" -; -INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -MEMMGR .SET MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC] +#include "cfg_mbc.asm" ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +DSKYENABLE .SET TRUE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYMODE .SET DSKYMODE_NG ; DSKY VERTSION: DSKYMODE_[V1|NG] diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile index d98c460f..a5790a06 100644 --- a/Source/HBIOS/Makefile +++ b/Source/HBIOS/Makefile @@ -24,7 +24,7 @@ else OBJECTS += RCZ80_zrc.rom RCZ80_zrc.com RCZ80_zrc.upd OBJECTS += SBC_std.rom SBC_std.com SBC_std.upd OBJECTS += SBC_simh.rom SBC_simh.com SBC_simh.upd - OBJECTS += SBC_mbc.rom SBC_mbc.com SBC_mbc.upd + OBJECTS += MBC_std.rom MBC_std.com MBC_std.upd OBJECTS += SCZ180_126.rom SCZ180_126.com SCZ180_126.upd OBJECTS += SCZ180_130.rom SCZ180_130.com SCZ180_130.upd OBJECTS += SCZ180_131.rom SCZ180_131.com SCZ180_131.upd @@ -35,7 +35,7 @@ else endif MOREDIFF = camel80.bin game.bin hbios_rom.bin nascom.bin prefix.bin usrrom.bin \ - dbgmon.bin hbios_app.bin imgpad1.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \ + dbgmon.bin hbios_app.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \ eastaegg.bin hbios_img.bin osimg.bin tastybasic.bin \ game.bin usrrom.bin diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 35aad31c..e05d31b4 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "DYNO" ; -PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -63,6 +63,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -163,6 +164,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -175,7 +177,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 853e2f3f..e8791d78 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "EASYZ80" ; -PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -64,6 +64,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -194,6 +195,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -210,7 +212,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 15f4c167..18f7d6ff 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -10,7 +10,7 @@ ; #DEFINE PLATFORM_NAME "ROMWBW" ; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -63,7 +63,6 @@ MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -91,10 +90,14 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -255,6 +258,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -266,6 +270,7 @@ PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -277,7 +282,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm new file mode 100644 index 00000000..8f08b1da --- /dev/null +++ b/Source/HBIOS/cfg_mbc.asm @@ -0,0 +1,231 @@ +; +;================================================================================================== +; ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC +;================================================================================================== +; +; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD +; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY +; UNDER THIS DIRECTORY. +; +; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS +; FOR THE PLATFORM. +; +#DEFINE PLATFORM_NAME "Multi Board Computer" +; +PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] +CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +; +CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0) +ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0) +MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC] +MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +; +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) +CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY +; +EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT +DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS +DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS +; +LEDENABLE .EQU TRUE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) +; +BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE +CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] +DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS +UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED +UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART +UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART +UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART +UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART +UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART +; +ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] +SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM) +TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG/N8/RC/RCV9958] +TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +; +MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .EQU TRUE ; MD: ENABLE ROM DISK +MDRAM .EQU TRUE ; MD: ENABLE RAM DISK +MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +; +FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] +FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111] +FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111] +FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +; +RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $44 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY +SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +; +PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .EQU $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER +AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4 +; +AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4 +AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] +; +SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index 11dee64f..a5af36f4 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "MARK IV" ; -PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -66,10 +66,14 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -189,6 +193,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -199,6 +204,7 @@ PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -209,7 +215,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index 85c47a57..ad3f1f38 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "N8" ; -PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -48,7 +48,6 @@ N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) ; RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR -PPIBASE .EQU N8_PPI0 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -68,11 +67,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -192,6 +195,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -209,7 +213,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index 3bfccfcc..e709bb45 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -66,6 +66,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -207,6 +208,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -223,7 +225,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm index 9313f04b..a0786854 100644 --- a/Source/HBIOS/cfg_rcz280.asm +++ b/Source/HBIOS/cfg_rcz280.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280] +PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -71,6 +71,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -223,6 +224,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -239,7 +241,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index d57b3e13..480e1dd5 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -65,6 +65,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -212,6 +213,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -228,7 +230,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 6736e21f..aae602e5 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "SBC" ; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -35,7 +35,6 @@ MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -60,11 +59,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -192,6 +195,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -210,7 +214,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 1ccc3846..5e32a44b 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "SCZ180" ; -PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -61,6 +61,7 @@ DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -202,6 +203,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -218,7 +220,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_una.asm b/Source/HBIOS/cfg_una.asm index 8f589937..f2363497 100644 --- a/Source/HBIOS/cfg_una.asm +++ b/Source/HBIOS/cfg_una.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "UNA" ; -PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] ; BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 127a24b0..8acd8239 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "ZETA" ; -PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -35,7 +35,6 @@ MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -52,11 +51,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -137,6 +140,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -144,6 +148,7 @@ SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -152,7 +157,8 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 7bd79fc7..ba3d9758 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "ZETA V2" ; -PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -38,7 +38,6 @@ MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -63,11 +62,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -148,6 +151,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -155,6 +159,7 @@ SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -163,7 +168,8 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/dbgmon.asm b/Source/HBIOS/dbgmon.asm index 5aacfe6c..28bfcf7d 100644 --- a/Source/HBIOS/dbgmon.asm +++ b/Source/HBIOS/dbgmon.asm @@ -953,8 +953,13 @@ TXT_HELP .TEXT "\r\nMonitor Commands (all values in hex):" ; #IF DSKYENABLE ; -#DEFINE DSKY_KBD +#DEFINE DSKY_KBD + #IF (DSKYMODE == DSKYMODE_V1) #INCLUDE "dsky.asm" + #ENDIF + #IF (DSKYMODE == DSKYMODE_NG) +#INCLUDE "dskyng.asm" + #ENDIF ; KY_PR .EQU KY_FW ; USE [FW] FOR [PR] (PORT READ) KY_PW .EQU KY_BK ; USE [BW] FOR [PW] (PORT WRITE) @@ -1352,7 +1357,7 @@ ENCBUF1: INC HL ; BUMP TO NEXT BYTE FOR NEXT PASS PUSH AF ; SAVE IT AND $80 ; ISOLATE HI BIT (DP) - XOR $80 ; FLIP IT + ;XOR $80 ; FLIP IT LD C,A ; SAVE IN C POP AF ; RECOVER ORIGINAL AND $7F ; REMOVE HI BIT (DP) @@ -1373,8 +1378,10 @@ ENCBUF1: POP HL ; RESTORE HL RET ; -CPUUP .DB $84,$CB,$EE,$BB,$80,$BB,$EE,$84 ; "-CPU UP-" (RAW SEG) -MSGBOOT .DB $FF,$9D,$9D,$8F,$20,$80,$80,$80 ; "Boot! " (RAW SEG) +#IF (DSKYMODE == DSKYMODE_V1) +; +CPUUP .DB $04,$4B,$6E,$3B,$00,$3B,$6E,$04 ; "-CPU UP-" (RAW SEG) +MSGBOOT .DB $7F,$1D,$1D,$0F,$A0,$00,$00,$00 ; "Boot! " (RAW SEG) ADDR .DB $17,$18,$19,$10,$00,$00,$00,$00 ; "Adr 0000" (ENCODED) PORT .DB $13,$14,$15,$16,$10,$10,$00,$00 ; "Port 00" (ENCODED) GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) @@ -1385,6 +1392,7 @@ GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) ;_____________________________________________________________________________ ; SEGDECODE: +; ; POS $00 $01 $02 $03 $04 $05 $06 $07 ; GLYPH '0' '1' '2' '3' '4' '5' '6' '7' .DB $7B, $30, $6D, $75, $36, $57, $5F, $70 @@ -1397,6 +1405,37 @@ SEGDECODE: ; GLYPH ' ' '-' '.' 'P' 'o' 'r' 't' 'A' 'd' 'r' 'G' .DB $00, $04, $00, $6E, $1D, $0C, $0F, $7E, $3D, $0C, $5B ; +#ENDIF +; +#IF (DSKYMODE == DSKYMODE_NG) +; +CPUUP .DB $40,$39,$73,$3E,$00,$3E,$73,$40 ; "-CPU UP-" (RAW SEG) +MSGBOOT .DB $7F,$5C,$5C,$78,$A0,$00,$00,$00 ; "Boot! " (RAW SEG) +ADDR .DB $17,$18,$19,$10,$00,$00,$00,$00 ; "Adr 0000" (ENCODED) +PORT .DB $13,$14,$15,$16,$10,$10,$00,$00 ; "Port 00" (ENCODED) +GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) +; +;_HEX_7_SEG_DECODE_TABLE______________________________________________________ +; +; SET BIT 7 TO DISPLAY W/ DECIMAL POINT +;_____________________________________________________________________________ +; +SEGDECODE: +; + ; POS $00 $01 $02 $03 $04 $05 $06 $07 + ; GLYPH '0' '1' '2' '3' '4' '5' '6' '7' + .DB $3F, $06, $58, $4F, $66, $6D, $7D, $07 +; + ; POS $08 $09 $0A $0B $0C $0D $0E $0F + ; GLYPH '8' '9' 'A' 'B' 'C' 'D' 'E' 'F' + .DB $7F, $67, $77, $7C, $39, $5E, $79, $71 +; + ; POS $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A + ; GLYPH ' ' '-' '.' 'P' 'o' 'r' 't' 'A' 'd' 'r' 'G' + .DB $00, $40, $00, $73, $5C, $50, $78, $77, $5E, $50, $3D +; +#ENDIF +; DISPLAYBUF: .FILL 8,0 ; #ELSE diff --git a/Source/HBIOS/dsky.asm b/Source/HBIOS/dsky.asm index 26b9e92a..464836cd 100644 --- a/Source/HBIOS/dsky.asm +++ b/Source/HBIOS/dsky.asm @@ -3,10 +3,13 @@ ; DSKY ROUTINES ;================================================================================================== ; -PPIA .EQU PPIBASE + 0 ; PORT A -PPIB .EQU PPIBASE + 1 ; PORT B -PPIC .EQU PPIBASE + 2 ; PORT C -PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT +; THE DSKY MAY COSESIDE ON THE SAME PPI BUS AS A PPISD. IT MAY NOT +; SHARE A PPI BUS WITH A PPIDE. +; +PPIA .EQU DSKYPPIBASE + 0 ; PORT A +PPIB .EQU DSKYPPIBASE + 1 ; PORT B +PPIC .EQU DSKYPPIBASE + 2 ; PORT C +PPIX .EQU DSKYPPIBASE + 3 ; PPI CONTROL PORT ; ; ICM7218A KEYPAD PPISD ; -------- -------- -------- @@ -26,6 +29,15 @@ PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT ; BITS 7-6 IDENTFY THE COLUMN OF THE KEY PRESSED ; BITS 5-0 ARE A BITMAP, WITH A BIT ON TO INDICATE ROW OF KEY PRESSED ; +; +; LED SEGMENTS (BIT VALUES) +; +; +--40--+ +; 02 20 +; +--04--+ +; 08 10 +; +--01--+ 80 +; ; ____PC0________PC1________PC2________PC3____ ; PB5 | $20 [D] $60 [E] $A0 [F] $E0 [BO] ; PB4 | $10 [A] $50 [B] $90 [C] $D0 [GO] @@ -278,7 +290,12 @@ DSKY_SHOW: LD B,DSKY_BUFLEN ; NUMBER OF DIGITS LD C,PPIA DSKY_HEXOUT2: - OUTI + ;OUTI + LD A,(HL) + XOR $80 ; FIX DOT POLARITY + OUT (C),A + INC HL + DEC B JP Z,DSKY_STROBE ; DO FINAL STROBE AND RETURN CALL DSKY_STROBE ; STROBE BYTE VALUE JR DSKY_HEXOUT2 @@ -301,22 +318,22 @@ DSKY_COFF: ; CLEAR HIGH BIT TO SHOW DECIMAL POINT ; DSKY_NUMS: - .DB $FB ; 0 - .DB $B0 ; 1 - .DB $ED ; 2 - .DB $F5 ; 3 - .DB $B6 ; 4 - .DB $D7 ; 5 - .DB $DF ; 6 - .DB $F0 ; 7 - .DB $FF ; 8 - .DB $F7 ; 9 - .DB $FE ; A - .DB $9F ; B - .DB $CB ; C - .DB $BD ; D - .DB $CF ; E - .DB $CE ; F + .DB $7B ; 0 + .DB $30 ; 1 + .DB $6D ; 2 + .DB $75 ; 3 + .DB $36 ; 4 + .DB $57 ; 5 + .DB $5F ; 6 + .DB $70 ; 7 + .DB $7F ; 8 + .DB $77 ; 9 + .DB $7E ; A + .DB $1F ; B + .DB $4B ; C + .DB $3D ; D + .DB $4F ; E + .DB $4E ; F ; ; SEG DISPLAY WORKING STORAGE ; diff --git a/Source/HBIOS/dskyng.asm b/Source/HBIOS/dskyng.asm new file mode 100644 index 00000000..53305e6a --- /dev/null +++ b/Source/HBIOS/dskyng.asm @@ -0,0 +1,561 @@ +; +;================================================================================================== +; DSKY NEXT GEN ROUTINES +;================================================================================================== +; +; A DSKYNG CAN SHARE A PPI BUS WITH EITHER A PPIDE OR PPISD. +; +; LED SEGMENTS (BIT VALUES) +; +; +--01--+ +; 20 02 +; +--40--+ +; 10 04 +; +--08--+ 80 +; +; KEY CODE MAP (KEY CODES) --CCCRRR +; +; 00 08 10 18 +; 01 09 11 19 +; 02 0A 12 1A +; 03 0B 13 1B +; 04 0C 14 1C +; 05 0D 15 1D +; +; LED BIT MAP (BIT VALUES) +; +; $08 $09 $0A $0B +; --- --- --- --- +; 01 01 01 01 +; 02 02 02 02 +; 04 04 04 04 +; 08 08 08 08 +; 10 10 10 10 +; 20 20 20 20 +; +PPIA .EQU DSKYPPIBASE + 0 ; PORT A +PPIB .EQU DSKYPPIBASE + 1 ; PORT B +PPIC .EQU DSKYPPIBASE + 2 ; PORT C +PPIX .EQU DSKYPPIBASE + 3 ; PPI CONTROL PORT +; +DSKY_PPIX_RD: .EQU %10010010 ; PPIX VALUE FOR READS +DSKY_PPIX_WR: .EQU %10000010 ; PPIX VALUE FOR WRITES +; +; PIO CHANNEL C: +; +; 7 6 5 4 3 2 1 0 +; RES /RD /WR CS CS 0 0 A0 +; +; SETTING BITS 3 & 4 WILL ASSERT /CS ON 3279 +; CLEAR BITS 5 OR 6 TO ASSERT READ/WRITE +; +DSKY_PPI_IDLE: .EQU %01100000 +; +DSKY_CMD_CLR: .EQU %11011111 ; CLEAR (ALL OFF) +DSKY_CMD_CLRX: .EQU %11010011 ; CLEAR (ALL ON) +DSKY_CMD_WDSP: .EQU %10010000 ; WRITE DISPLAY RAM +DSKY_CMD_RDSP: .EQU %01110000 ; READ DISPLAY RAM +DSKY_CMD_CLK: .EQU %00100000 ; SET CLK PRESCALE +DSKY_CMD_FIFO: .EQU %01000000 ; READ FIFO +; +DSKY_PRESCL: .EQU DSKYOSC/100000 ; PRESCALER +; +;__DSKY_INIT_________________________________________________________________________________________ +; +; CONFIGURE PARALLEL PORT AND INITIALIZE 8279 +;____________________________________________________________________________________________________ +; +; +; HARDWARE RESET 8279 BY PULSING RESET LINE +; +DSKY_INIT: +; + ; SETUP PPI + CALL DSKY_PPIRD + ; INIT 8279 VALUES TO IDLE STATE + LD A,DSKY_PPI_IDLE + OUT (PPIC),A + ; PULSE RESET SIGNAL ON 8279 + SET 7,A + OUT (PPIC),A + RES 7,A + OUT (PPIC),A + ; DONE +; +DSKY_REINIT: + CALL DSKY_PPIIDLE + ; SET CLOCK SCALER TO 20 + LD A,DSKY_CMD_CLK | DSKY_PRESCL + CALL DSKY_CMD + LD A,%00001000 ; dan + CALL DSKY_CMD + ; FALL THRU +; +DSKY_RESET: + ; RESET DSKY + LD A,DSKY_CMD_CLR + CALL DSKY_CMD + RET +; +#IFDEF DSKY_KBD +; +KY_0 .EQU $00 +KY_1 .EQU $01 +KY_2 .EQU $02 +KY_3 .EQU $03 +KY_4 .EQU $04 +KY_5 .EQU $05 +KY_6 .EQU $06 +KY_7 .EQU $07 +KY_8 .EQU $08 +KY_9 .EQU $09 +KY_A .EQU $0A +KY_B .EQU $0B +KY_C .EQU $0C +KY_D .EQU $0D +KY_E .EQU $0E +KY_F .EQU $0F +KY_FW .EQU $10 ; FORWARD +KY_BK .EQU $11 ; BACKWARD +KY_CL .EQU $12 ; CLEAR +KY_EN .EQU $13 ; ENTER +KY_DE .EQU $14 ; DEPOSIT +KY_EX .EQU $15 ; EXAMINE +KY_GO .EQU $16 ; GO +KY_BO .EQU $17 ; BOOT +; +;__DSKY_STAT_________________________________________________________________________________________ +; +; CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS +;____________________________________________________________________________________________________ +; +DSKY_STAT: + CALL DSKY_ST + AND $0F ; ISOLATE THE CUR FIFO LEN + RET +; +;__DSKY_GETKEY_____________________________________________________________________________________ +; +; WAIT FOR A DSKY KEYPRESS AND RETURN +;____________________________________________________________________________________________________ +; +DSKY_GETKEY: + CALL DSKY_STAT + JR Z,DSKY_GETKEY ; LOOP IF NOTHING THERE + LD A,DSKY_CMD_FIFO + CALL DSKY_CMD + CALL DSKY_DIN + LD B,24 ; SIZE OF DECODE TABLE + LD C,0 ; INDEX + LD HL,DSKY_KEYMAP ; POINT TO BEGINNING OF TABLE +DSKY_GETKEY1: + CP (HL) ; MATCH? + JR Z,DSKY_GETKEY2 ; FOUND, DONE + INC HL + INC C ; BUMP INDEX + DJNZ DSKY_GETKEY1 ; LOOP UNTIL EOT + LD A,$FF ; NOT FOUND ERR, RETURN $FF + RET +DSKY_GETKEY2: + ; RETURN THE INDEX POSITION WHERE THE SCAN CODE WAS FOUND + LD A,C ; RETURN INDEX VALUE + RET +; +;_KEYMAP_TABLE_____________________________________________________________________________________________________________ +; +DSKY_KEYMAP: + ; POS $00 $01 $02 $03 $04 $05 $06 $07 + ; KEY [0] [1] [2] [3] [4] [5] [6] [7] + .DB $0D, $04, $0C, $14, $03, $0B, $13, $02 +; + ; POS $08 $09 $0A $0B $0C $0D $0E $0F + ; KEY [8] [9] [A] [B] [C] [D] [E] [F] + .DB $0A, $12, $01, $09, $11, $00, $08, $10 +; + ; POS $10 $11 $12 $13 $14 $15 $16 $17 + ; KEY [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO] + .DB $05, $15, $1D, $1C, $1B, $1A, $19, $18 +; +#ENDIF ; DSKY_KBD +; +;================================================================================================== +; DSKY HEX DISPLAY +;================================================================================================== +; +DSKY_HEXOUT: + LD B,DSKY_HEXBUFLEN + LD HL,DSKY_BUF + LD DE,DSKY_HEXBUF +DSKY_HEXOUT1: + LD A,(DE) ; FIRST NIBBLE + SRL A + SRL A + SRL A + SRL A + PUSH HL + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + POP HL + LD (HL),A + INC HL + LD A,(DE) ; SECOND NIBBLE + AND 0FH + PUSH HL + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + POP HL + LD (HL),A + INC HL + INC DE ; NEXT BYTE + DJNZ DSKY_HEXOUT1 + LD HL,DSKY_BUF + JR DSKY_SHOW +; +;================================================================================================== +; DSKY SHOW BUFFER +; HL: ADDRESS OF BUFFER +; ENTER @ SHOWHEX FOR HEX DECODING +; ENTER @ SHOWSEG FOR SEGMENT DECODING +;================================================================================================== +; +DSKY_SHOWHEX: + JR DSKY_SHOW +; +DSKY_SHOWSEG: + JR DSKY_SHOW +; +DSKY_SHOW: +; PUSH HL +; CALL DSKY_RESET +; POP HL + LD C,0 ; STARTING DISPLAY POSITION + LD B,DSKY_BUFLEN ; NUMBER OF CHARS + JP DSKY_PUTSTR +; +; +; +; +; COMMAND IN A +; TRASHES BC +; +DSKY_CMD: + LD B,$01 + JR DSKY_DOUT2 +; +; DATA VALUE IN A +; TRASHES BC +; +DSKY_DOUT: + LD B,$00 +; +DSKY_DOUT2: +; + ; SAVE INCOMING DATA BYTE + PUSH AF +; + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIWR +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT DATA BYTE VALUE + POP AF + OUT (PPIA),A +; + ; PULSE /WR + RES 5,B + OUT (C),B + NOP ; MAY NOT BE NEEDED + SET 5,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; STATUS VALUE IN A +; TRASHES BC +; +DSKY_ST: + LD B,$01 + JR DSKY_DIN2 +; +; DATA VALUE RETURNED IN A +; TRASHES BC +; +DSKY_DIN: + LD B,$00 +; +DSKY_DIN2: + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIRD +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT /RD + RES 6,B + OUT (C),B +; + ; GET VALUE + IN A,(PPIA) +; + ; DEASSERT /RD + SET 6,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; BLANK THE DISPLAY (WITHOUT USING CLEAR) +; +DSKY_BLANK: + LD A,DSKY_CMD_WDSP + CALL DSKY_CMD + LD B,16 +DSKY_BLANK1: + PUSH BC + LD A,$FF + CALL DSKY_DOUT + POP BC + DJNZ DSKY_BLANK1 + RET +; +; WRITE A RAW BYTE VALUE TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE IN A. +; +DSKY_PUTBYTE: + PUSH BC + PUSH AF + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP AF + XOR $FF + CALL DSKY_DOUT + POP BC + RET +; +; READ A RAW BYTE VALUE FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE RETURNED IN A +; +DSKY_GETBYTE: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + CALL DSKY_DIN + XOR $FF + POP BC + RET +; +; WRITE A STRING OF RAW BYTE VALUES TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_PUTSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC +; +DSKY_PUTSTR1: + LD A,(HL) + XOR $FF + INC HL + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTSTR1 + RET +; +; READ A STRING OF RAW BYTE VALUES FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_GETSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + POP BC +; +DSKY_GETSTR1: + PUSH BC + CALL DSKY_DIN + POP BC + XOR $FF + LD (HL),A + INC HL + DJNZ DSKY_GETSTR1 + RET +; +; HL IS ADR OF ENCODED STRING OF BYTES +; B IS LEN OF STRING (BYTES) +; C IS POSITION IN DISPLAY RAM TO WRITE +; +DSKY_PUTENCSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC + EX DE,HL +DSKY_PUTENCSTR1: + LD A,(DE) + INC DE + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + XOR $FF + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTENCSTR1 + RET +; +; SETUP PPI FOR WRITING: PUT PPI PORT A IN OUTPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN OUTPUT MODE +; +DSKY_PPIWR: + PUSH AF +; + ; CHECK FOR WRITE MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_WR + JR Z,DSKY_PPIWR1 +; + ; SET PPI TO WRITE MODE + LD A,DSKY_PPIX_WR + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; + ; RESTORE PORT C (MAY NOT BE NEEDED) + LD A,DSKY_PPI_IDLE + OUT (PPIC),A +; +DSKY_PPIWR1: +; + POP AF + RET +; +; +; +DSKY_ADDHLA: + ADD A,L + LD L,A + RET NC + INC H + RET +; +; SETUP PPI FOR READING: PUT PPI PORT A IN INPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN INPUT MODE +; +DSKY_PPIRD: + PUSH AF +; + ; CHECK FOR READ MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_RD + JR Z,DSKY_PPIRD1 +; + ; SET PPI TO READ MODE + LD A,DSKY_PPIX_RD + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; +; ; DIAGNOSTIC +; LD A,'R' +; CALL COUT +; +DSKY_PPIRD1: + POP AF + RET +; +; RELEASE USE OF PPI +; +DSKY_PPIIDLE: + JR DSKY_PPIRD ; SAME AS READ MODE +; +; +; + +; +; CODES FOR NUMERICS +; HIGH BIT ALWAYS SET TO SUPPRESS DECIMAL POINT +; CLEAR HIGH BIT TO SHOW DECIMAL POINT +; +HEXMAP: +DSKY_NUMS: + .DB $3F ; 0 + .DB $06 ; 1 + .DB $5B ; 2 + .DB $4F ; 3 + .DB $66 ; 4 + .DB $6D ; 5 + .DB $7D ; 6 + .DB $07 ; 7 + .DB $7F ; 8 + .DB $67 ; 9 + .DB $77 ; A + .DB $7C ; B + .DB $39 ; C + .DB $5E ; D + .DB $79 ; E + .DB $71 ; F +; +DSKY_PPIX_VAL: .DB 0 +; +; SEG DISPLAY WORKING STORAGE +; +DSKY_BUF .FILL 8,0 +DSKY_BUFLEN .EQU $ - DSKY_BUF +DSKY_HEXBUF .FILL 4,0 +DSKY_HEXBUFLEN .EQU $ - DSKY_HEXBUF diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index a31c626e..8d534fe9 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -97,10 +97,21 @@ MODCNT .SET MODCNT + 1 #ENDIF ; #IF (LEDENABLE) -#DEFINE LED(N) PUSH AF - #DEFCONT \ LD A,~N - #DEFCONT \ OUT (LEDPORT),A - #DEFCONT \ POP AF + #IF (LEDMODE == LEDMODE_STD) +#DEFINE LED(N) PUSH AF + #DEFCONT \ LD A,~N + #DEFCONT \ OUT (LEDPORT),A + #DEFCONT \ POP AF + #ENDIF + #IF (LEDMODE == LEDMODE_RTC) +#DEFINE LED(N) PUSH AF + #DEFCONT \ LD A,(RTCVAL) + #DEFCONT \ AND %11111100 + #DEFCONT \ OR (N & %00000011) + #DEFCONT \ LD (RTCVAL),A + #DEFCONT \ OUT (LEDPORT),A + #DEFCONT \ POP AF + #ENDIF #ELSE #DEFINE LED(N) \; #ENDIF @@ -1050,6 +1061,16 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n LD A,%00000001 OUT (DIAGPORT),A #ENDIF +#IF (LEDENABLE) + #IF (LEDMODE == LEDMODE_STD) + XOR A ; LED IS INVERTED, TURN IT ON + #ENDIF + #IF (LEDMODE == LEDMODE_RTC) + LD A,%00000001 ; LED 0 + LD (RTCVAL),A ; SAVE TO SHADOW REGISTER + #ENDIF + OUT (LEDPORT),A +#ENDIF ; LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY ; @@ -1222,7 +1243,7 @@ Z280_INITZ: #ENDIF ; DIAG(%00000011) - LED($00) + LED(%00000010) ; ; CHECK BATTERY BACKUP STATUS BEFORE WE COPY PROXY TO UPPER MEMORY ; @@ -1365,7 +1386,7 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK LD A,1 ; SET FOR RECOVERY MODE LD (HB_BOOT_REC),A ; SAVE FOR LATER #ENDIF - #IF (PLATFORM == PLT_SBC) + #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) #IF (BT_REC_TYPE == BT_REC_SBC01) LD A,%00100000 ; DISABLE RTC AND OUT (RTCIO),A ; DRQ DRIVER READ @@ -1398,13 +1419,17 @@ SAVE_REC_M: DIAG(%00001111) ; #IF (DSKYENABLE) + CALL DSKY_INIT + LD HL,MSG_HBVER + 5 LD A,(DSKY_NUMS + RMJ) - AND $7F + ;AND $7F + OR $80 LD (HL),A INC HL LD A,(DSKY_NUMS + RMN) - AND $7F + ;AND $7F + OR $80 LD (HL),A INC HL LD A,(DSKY_NUMS + RUP) @@ -1760,7 +1785,7 @@ NOT_REC_M0: #ENDIF ; DIAG(%01111111) - LED($FF) + LED(%00000011) ; ; PRIOR TO THIS POINT, CONSOLE I/O WAS NOT AVAILABLE UNLESS DIRECTED TO DEBUG OUTPUT I.E. XIO ; NOW THAT HBIOS IS READY, SET THE CONSOLE UNIT TO ACTIVATE CONSOLE I/O @@ -2111,7 +2136,7 @@ HB_WDZ: ; IF PLATFORM HAS A CONFIG JUMPER, CHECK TO SEE IF IT IS JUMPERED. ; IF SO, BYPASS SWITCH TO CRT CONSOLE (FAILSAFE MODE) ; - #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2)) + #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_MBC)) IN A,(RTCIO) ; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER BIT 6,A ; BIT 6 HAS CONFIG JUMPER STATE JR Z,INITSYS3 ; Z=SHORTED, BYPASS CONSOLE SWITCH @@ -2217,14 +2242,14 @@ CALLDUMMY: #IF (BT_REC_TYPE != BT_REC_NONE) ; HB_PCINIT_REC: - #IF (PLATFORM == PLT_SBC) + #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) .DW UART_PREINIT ; .DW CALLDUMMY #ENDIF HB_PCINITRLEN .EQU (($ - HB_PCINIT_REC) / 2) ; HB_INIT_REC: - #IF (PLATFORM == PLT_SBC) + #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) .DW UART_INIT .DW MD_INIT .DW PPIDE_INIT @@ -2339,9 +2364,9 @@ HB_INITTBL: #IF (TMSENABLE) .DW TMS_INIT #ENDIF -#IF (DSKYENABLE) - .DW DSKY_INIT -#ENDIF +;#IF (DSKYENABLE) +; .DW DSKY_INIT +;#ENDIF #IF (MDENABLE) .DW MD_INIT #ENDIF @@ -2789,7 +2814,7 @@ HB_DSKFN: OUT (DIAGPORT),A ; DISPLAY ON DIAG LEDS #ENDIF #IF (LEDENABLE & LEDDISKIO) - LED($FF) + LED(%00000001) #ENDIF LD E,1 ; ONE SECTOR HB_DSKFNADR .EQU $+1 @@ -4817,7 +4842,7 @@ SIZ_SPK .EQU $ - ORG_SPK .ECHO " bytes.\n" #ENDIF ; -#IF (PIO_4P | PIO_ZP | PPI_SBC) +#IF (PIO_4P | PIO_ZP | PIO_SBC) ORG_PIO .EQU $ #INCLUDE "pio.asm" SIZ_PIO .EQU $ - ORG_PIO @@ -4883,7 +4908,12 @@ SIZ_AY38910 .EQU $ - ORG_AY38910 ; #IF (DSKYENABLE) #DEFINE DSKY_KBD + #IF (DSKYMODE == DSKYMODE_V1) #INCLUDE "dsky.asm" + #ENDIF + #IF (DSKYMODE == DSKYMODE_NG) +#INCLUDE "dskyng.asm" + #ENDIF #ENDIF ; ; INCLUDE LZSA2 decompression engine if required. @@ -5899,7 +5929,12 @@ STR_SYSCHK .TEXT "\r\n>>> SYSCHK: $" STR_CONTINUE .TEXT "\r\nContinue (Y/N)? $" ; #IF (DSKYENABLE) ; 'H','B','I','O',' ',' ',' ',' ' -MSG_HBVER .DB $BE,$FF,$8A,$FB,$80,$80,$80,$80 ; "HBIO " + #IF (DSKYMODE == DSKYMODE_V1) +MSG_HBVER .DB $3E,$7F,$0A,$7B,$00,$00,$00,$00 ; "HBIO " + #ENDIF + #IF (DSKYMODE == DSKYMODE_NG) +MSG_HBVER .DB $76,$7F,$30,$3F,$00,$00,$00,$00 ; "HBIO " + #ENDIF #ENDIF ; HB_APPBNK .DB 0 ; START BANK WHEN RUN IN APP MODE diff --git a/Source/HBIOS/imgpad1.asm b/Source/HBIOS/imgpad1.asm deleted file mode 100644 index 2aa54841..00000000 --- a/Source/HBIOS/imgpad1.asm +++ /dev/null @@ -1,12 +0,0 @@ -#INCLUDE "std.asm" -; -SLACK .EQU ($8000-BAS_SIZ-TBC_SIZ-FTH_SIZ-GAM_SIZ-USR_SIZ) - .FILL SLACK,00H -; -MON_STACK .EQU $ -; - .ECHO "Padspace space created: " - .ECHO SLACK - .ECHO " bytes.\n" - - .END \ No newline at end of file diff --git a/Source/HBIOS/pio.asm b/Source/HBIOS/pio.asm index c0d230f7..73e99853 100644 --- a/Source/HBIOS/pio.asm +++ b/Source/HBIOS/pio.asm @@ -929,10 +929,10 @@ DEFPIO(PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,INT_N,INT_N) DEFPIO(PIOZBASE+0,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N) DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N) #ENDIF -; PPI_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC)) +; PIO_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC)) -#IF PPI_SBC -DEFPPI(PPIBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut) +#IF PIO_SBC +DEFPPI(PIOSBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut) #ENDIF ; PIO_CNT .EQU ($ - PIO_CFG) / CFG_SIZ diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index b62e08e9..da6011e2 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -1011,6 +1011,22 @@ PPIDE_RESET: ;OUT (PPIDE_IO_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD OUT (C),A ; WRITE IT +; +; IF A DSKYNG IS ACTIVE AND IS ON THE SAME PPI PORT AS THE PPISD BEING +; RESET, THEN THE DSKYNG WILL ALSO BE RESET. SO, THE RESET CODE IS +; BRACKETED WITH CODE TO SAVE AND RESTORE THE STATE OF THE DSKYNG. +; THERE IS NO CHECK FOR THE SPECIFIC PPI PORT SINCE IT DOES NO HARM +; IF THE DSKYNG IS SAVED AND RESTORED. +; +#IF (DSKYENABLE) + #IF (DSKYMODE == DSKYMODE_NG) + ; SAVE CONTENTS OF DSKY DISPLAY ACROSS RESET + LD B,8 + LD C,0 + LD HL,DSKY_BUF + CALL DSKY_GETSTR + #ENDIF +#ENDIF ; ; PULSE IDE RESET LINE LD A,PPIDE_CTL_RESET @@ -1024,6 +1040,17 @@ PPIDE_RESET: OUT (C),A LD DE,20 CALL VDELAY +; +#IF (DSKYENABLE) + #IF (DSKYMODE == DSKYMODE_NG) + ; REININT DSKY AND RESTORE CONTENTS + CALL DSKY_REINIT + LD B,8 + LD C,0 + LD HL,DSKY_BUF + CALL DSKY_PUTSTR + #ENDIF +#ENDIF ; LD A,%00001010 ; SET ~IEN, NO INTERRUPTS ;OUT (PPIDE_REG_CTRL),A diff --git a/Source/HBIOS/ppp.asm b/Source/HBIOS/ppp.asm index 5a4032fc..d3b59f05 100644 --- a/Source/HBIOS/ppp.asm +++ b/Source/HBIOS/ppp.asm @@ -6,9 +6,9 @@ ; TODO: ; 1) ADD SUPPORT FOR DSKY ; -PPP_IO .EQU PPIBASE + 0 ; PPP DATA I/O (PPI PORT A) -PPP_CTL .EQU PPIBASE + 2 ; PPP CTL LINES (PPI PORT C) -PPP_PPICTL .EQU PPIBASE + 3 ; PPI CONTROL PORT +PPP_IO .EQU PPPBASE + 0 ; PPP DATA I/O (PPI PORT A) +PPP_CTL .EQU PPPBASE + 2 ; PPP CTL LINES (PPI PORT C) +PPP_PPICTL .EQU PPPBASE + 3 ; PPI CONTROL PORT ; ; COMMAND BYTES ; @@ -49,7 +49,7 @@ PPP_CMDVER .EQU $F1 ; SEND FIRMWARE VERSION PPP_INIT: CALL NEWLINE ; FORMATTING PRTS("PPP: IO=0x$") - LD A,PPIBASE + LD A,PPPBASE CALL PRTHEXBYTE ; CALL PPP_INITPPP ; INIT PPP BOARD @@ -358,7 +358,7 @@ PPPCON_DEVICE: LD E,0 ; E := DEVICE NUM, ALWAYS 0 LD C,$BF ; C := DEVICE TYPE, 0xBF IS PROP TERM LD H,0 ; H := 0, DRIVER HAS NO MODES - LD L,PPIBASE ; L := BASE I/O ADDRESS + LD L,PPPBASE ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET ; @@ -694,7 +694,7 @@ PPPSD_DEVICE: LD E,(IY+PPPSD_DEV) ; E := PHYSICAL DEVICE NUMBER LD C,%01010000 ; C := ATTRIBUTES, REMOVABLE, SD CARD LD H,0 ; H := 0, DRIVER HAS NO MODES - LD L,PPIBASE ; L := BASE I/O ADDRESS + LD L,PPPBASE ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET ; diff --git a/Source/HBIOS/romldr.asm b/Source/HBIOS/romldr.asm index 33d3dbfa..ed3e5ee2 100644 --- a/Source/HBIOS/romldr.asm +++ b/Source/HBIOS/romldr.asm @@ -358,6 +358,10 @@ dskycmd: call clrled ; clear LEDs ; call DSKY_GETKEY ; get DSKY key + + call prthexbyte + + cp $FF ; check for error ret z ; abort if so ; @@ -1078,8 +1082,16 @@ clrled: out (DIAGPORT),a ; clear diag leds #endif #if (LEDENABLE) - or $FF ; led is inverted + #if (LEDMODE == LEDMODE_STD) + ld a,$FF ; led is inverted + out (LEDPORT),a ; clear led + #endif + #if (LEDMODE == LEDMODE_RTC) + ; Only bits 0 and 1 of the RTC latch are for the LEDs. Here, + ; we assume that it is OK to zero all bits of the RTC latch. + xor a ; turn off out (LEDPORT),a ; clear led + #endif #endif #endif ret @@ -1903,9 +1915,14 @@ str_err_api .db "Unexpected hardware BIOS API failure",0 ; #if (DSKYENABLE) #define DSKY_KBD + #if (DSKYMODE == DSKYMODE_V1) VDELAY .equ vdelay DLY2 .equ dly2 #include "dsky.asm" + #endif + #if (DSKYMODE == DSKYMODE_NG) +#include "dskyng.asm" + #endif #endif ; ;======================================================================= @@ -1957,10 +1974,18 @@ str_help .db "\r\n" .db 0 ; #if (DSKYENABLE) -msg_sel .db $ff,$9d,$9d,$8f,$ec,$80,$80,$80 ; "boot? " -msg_boot .db $ff,$9d,$9d,$8f,$00,$00,$00,$80 ; "boot... " -msg_load .db $8b,$9d,$fd,$bd,$00,$00,$00,$80 ; "load... " -msg_go .db $db,$9d,$00,$00,$00,$80,$80,$80 ; "go... " + #if (DSKYMODE == DSKYMODE_V1) +msg_sel .db $7f,$1d,$1d,$0f,$6c,$00,$00,$00 ; "boot? " +msg_boot .db $7f,$1d,$1d,$0f,$80,$80,$80,$00 ; "boot... " +msg_load .db $0b,$1d,$7d,$3d,$80,$80,$80,$00 ; "load... " +msg_go .db $5b,$1d,$80,$80,$80,$00,$00,$00 ; "go... " + #endif + #if (DSKYMODE == DSKYMODE_NG) +msg_sel .db $7f,$5c,$5c,$78,$53,$00,$00,$00 ; "boot? " +msg_boot .db $7f,$5c,$5c,$78,$80,$80,$80,$00 ; "boot... " +msg_load .db $38,$5c,$5f,$5e,$80,$80,$80,$00 ; "load... " +msg_go .db $3d,$5c,$80,$80,$80,$00,$00,$00 ; "go... " + #endif #endif ; ;======================================================================= @@ -2050,13 +2075,13 @@ ra_ent(str_fth, 'F', KY_EX, BID_IMG1, $0000, FTH_LOC, FTH_SIZ, FTH_LOC) ra_ent(str_bas, 'B', KY_DE, BID_IMG1, $1700, BAS_LOC, BAS_SIZ, BAS_LOC) ra_ent(str_tbas, 'T', KY_EN, BID_IMG1, $3700, TBC_LOC, TBC_SIZ, TBC_LOC) ra_ent(str_play, 'P', $FF, BID_IMG1, $4000, GAM_LOC, GAM_SIZ, GAM_LOC) -ra_ent(str_user, 'U', $FF, BID_IMG1, $7000, USR_LOC, USR_SIZ, USR_LOC) +ra_ent(str_egg, 'E'+$80, $FF, BID_IMG1, $4900, EGG_LOC, EGG_SIZ, EGG_LOC) +ra_ent(str_user, 'U', $FF, BID_IMG1, $4B00, USR_LOC, USR_SIZ, USR_LOC) ra_ent(str_net, 'N', $FF, BID_IMG2, $0000, NET_LOC, NET_SIZ, NET_LOC) #endif #if (DSKYENABLE) -ra_ent(str_dsky, 'Y'+$80, KY_GO, bid_cur, $1000, MON_LOC, MON_SIZ, MON_DSKY) +ra_ent(str_dsky, 'Y'+$80, KY_GO, BID_IMG0, $1000, MON_LOC, MON_SIZ, MON_DSKY) #endif -ra_ent(str_egg, 'E'+$80, $FF , bid_cur, $0E00, EGG_LOC, EGG_SIZ, EGG_LOC) .dw 0 ; table terminator ; ra_tbl_app: @@ -2068,7 +2093,6 @@ ra_ent(str_zsys, 'Z', KY_FW, bid_cur, $2000, CPM_LOC, CPM_SIZ, CPM_ENT) #if (DSKYENABLE) ra_ent(str_dsky, 'Y'+$80, KY_GO, bid_cur, $1000, MON_LOC, MON_SIZ, MON_DSKY) #endif -ra_ent(str_egg, 'E'+$80, $FF , bid_cur, $0E00, EGG_LOC, EGG_SIZ, EGG_LOC) .dw 0 ; table terminator ; str_mon .db "Monitor",0 diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index 8a082a07..2932a310 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -162,10 +162,10 @@ RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE ; #IF (SDMODE == SDMODE_PPI) ; PPISD SD_DEVMAX .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_PPIBASE .EQU PPIBASE ; BASE IO PORT FOR PPI -SD_PPIB .EQU PPIBASE + 1 ; PPI PORT B (INPUT: DOUT) -SD_PPIC .EQU PPIBASE + 2 ; PPI PORT C (OUTPUT: CS, CLK, DIN) -SD_PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT +SD_PPIBASE .EQU SDPPIBASE ; BASE IO PORT FOR PPI +SD_PPIB .EQU SDPPIBASE + 1 ; PPI PORT B (INPUT: DOUT) +SD_PPIC .EQU SDPPIBASE + 2 ; PPI PORT C (OUTPUT: CS, CLK, DIN) +SD_PPIX .EQU SDPPIBASE + 3 ; PPI CONTROL PORT SD_OPRREG .EQU SD_PPIC ; PPI PORT C IS OPR REG SD_OPRDEF .EQU %00110001 ; CS HI, DI HI SD_INPREG .EQU SD_PPIB ; INPUT REGISTER IS PPI PORT B diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 467d5d9f..bf9bff37 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -55,7 +55,7 @@ PLT_EZZ80 .EQU 9 ; EASY Z80 PLT_SCZ180 .EQU 10 ; SCZ180 PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280 -; +PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER ; ; CPU TYPES ; @@ -141,6 +141,18 @@ CONBELL_NONE .EQU 0 CONBELL_PSG .EQU 1 CONBELL_IOBIT .EQU 2 ; +; LED MODE SELECTIONS +; +LEDMODE_NONE .EQU 0 +LEDMODE_STD .EQU 1 +LEDMODE_RTC .EQU 2 +; +; DSKY MODE SELECTIONS +; +DSKYMODE_NONE .EQU 0 +DSKYMODE_V1 .EQU 1 +DSKYMODE_NG .EQU 2 +; ; FD MODE SELECTIONS ; FDMODE_NONE .EQU 0 @@ -518,7 +530,7 @@ CBIOS_LOC .EQU CBIOS_END - CBIOS_SIZ ; START OF CBIOS CPM_ENT .EQU CBIOS_LOC ; CPM ENTRY POINT (IN CBIOS) -LDR_SIZ .EQU $0E00 +LDR_SIZ .EQU $1000 MON_LOC .EQU $F000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM MON_SIZ .EQU $1000 - HBX_SIZ ; SIZE OF MONITOR BINARY IMAGE @@ -545,7 +557,7 @@ GAM_SIZ .EQU $0900 GAM_END .EQU GAM_LOC + GAM_SIZ USR_LOC .EQU $0200 ; USER -USR_SIZ .EQU $1000 +USR_SIZ .EQU $8000 - FTH_SIZ - BAS_SIZ - TBC_SIZ - GAM_SIZ - EGG_SIZ USR_END .EQU USR_LOC + USR_SIZ NET_LOC .EQU $0100 ; NETWORK BOOT diff --git a/Source/ver.inc b/Source/ver.inc index 9e818c93..96741d7f 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 1 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "3.1.1-pre.84" +#DEFINE BIOSVER "3.1.1-pre.85" diff --git a/Source/ver.lib b/Source/ver.lib index 46b36210..b8bc7696 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 1 rup equ 1 rtp equ 0 biosver macro - db "3.1.1-pre.84" + db "3.1.1-pre.85" endm