diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf index 6d3c6ae4..dfeb9c34 100644 Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md index 0515648a..f693e46e 100644 --- a/Source/Doc/Hardware.md +++ b/Source/Doc/Hardware.md @@ -3,7 +3,9 @@ $include{"Book.h"}$ $define{doc_author}{Mark Pruden \& Wayne Warthen}$ $define{doc_authmail}{}$ -# Supported Hardware Platforms +# Overview + +## Supported Hardware Platforms This section contains a summary of the system configuration target for each of the pre-built ROM images included in the RomWBW @@ -12,16 +14,16 @@ distribution. It is intended to help you select the correct ROM image and understand the basic hardware components supported. Detailed hardware system configuration information should be obtained -from your system provider/designer. +from your system provider/designer. The table below summarizes the hardware platforms currently supported by RomWBW along with the standard pre-built ROM image(s). | **Description** | **Bus** | **ROM Image File** | **Baud Rate** | |-------------------------------------------------------------|---------|------------------------------|--------------:| -| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 | +| [RetroBrew Z80 SBC V2]^1^ | ECB | SBC_std.rom | 38400 | | [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 | -| [RetroBrew N8 Z180 SBC]^1^ (date >= 2312) | ECB | N8_std.rom | 38400 | +| [N8 Z180 SBC]^1^ (date >= 2312) | ECB | N8_std.rom | 38400 | | [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 | | [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 | | [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 | @@ -44,22 +46,22 @@ by RomWBW along with the standard pre-built ROM image(s). | [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 | | [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 | | [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 | -| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc_std.rom | 115200 | -| [Z80 ZRC CPU Module (RAM)]^7^ | RCBus | RCZ80_zrc_ram_std.rom | 115200 | -| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512_std.rom | 115200 | -| [Z80 EaZy80-512 CPU Module]^7^ | RCBus | RCZ80_ez512_std.rom | 115200 | -| [Z80 K80W CPU Module]^7^ | RCBus | RCZ80_k80w_std.rom | 115200 | -| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc_std.rom | 115200 | -| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc_std.rom | 115200 | -| [Z280 ZZRCC CPU Module (RAM)]^7^ | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 | -| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb_std.rom | 115200 | +| [ZRC Z80 CPU Module]^7^ | RCBus | RCZ80_zrc_std.rom | 115200 | +| [ZRC Z80 CPU Module (RAM)]^7^ | RCBus | RCZ80_zrc_ram_std.rom | 115200 | +| [ZRC512 Z80 CPU Module]^7^ | RCBus | RCZ80_zrc512_std.rom | 115200 | +| [EaZy80-512 Z80 CPU Module]^7^ | RCBus | RCZ80_ez512_std.rom | 115200 | +| [K80W Z80 CPU Module]^7^ | RCBus | RCZ80_k80w_std.rom | 115200 | +| [Z1RCC Z180 CPU Module]^7^ | RCBus | RCZ180_z1rcc_std.rom | 115200 | +| [ZZRCC Z280 CPU Module]^7^ | RCBus | RCZ280_zzrcc_std.rom | 115200 | +| [ZZRCC Z280 CPU Module (RAM)]^7^ | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 | +| [ZZ80MB Z280 SBC]^7^ | RCBus | RCZ280_zz80mb_std.rom | 115200 | | [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 | -| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 | +| [S100 Computers Z180 SBC]^9^ | S100 | S100_std.rom | 57600 | | [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 | | [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 | -| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 | +| [EP Mini-ITX Z180]^11^ | RCBus | EPITX_std.rom | 115200 | | [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 | -| [FPGA Z80 S100]^9^ | S100 | FZ80_std.rom | 9600 | +| [S100 Computers FPGA Z80 SBC]^9^ | S100 | FZ80_std.rom | 9600 | | [Genesis STD Z180]^12^ | STD | GMZ180_std.rom | 115200 | | ^1^Designed by Andrew Lynch @@ -91,6 +93,8 @@ CPU, so the ext/nat selection only applies to them. Z80 CPUs have no built-in bank switching logic, so they are always configured for external bank switching. +## General Guidance + The standard ROM images will detect and install support for certain devices and peripherals that are on-board or frequently used with each platform. If the device or peripheral is not detected at boot, @@ -100,24 +104,40 @@ In some cases, support for multiple hardware components with potentially conflicting resource usage are handled by a single ROM image. It is up to the user to ensure that no conflicting hardware is in use. +CPU speed will be dynamically measured at startup if DSRTC is present + All pre-built ROM images are pure binary files (they are not "hex" files). They are intended to be programmed starting at the very start of the ROM chip (address 0). Most of the pre-built images are 512KB in size. If your system utilizes a larger ROM, you can just program the image into the first 512KB of the ROM for now. +For this document port addresses `IO=xxx` are represented in decimal. + `\clearpage`{=latex} # Platform Configurations -## Duodyne +## Duodyne Z80 System + +Duodyne is a third generation ROMWBW focused retrocomputer incorporating lessons +learned and improvements from my original ECB Z80 SBC (aka N8VEM) and the nhyodyne +modular computer. It is literally designed around ROMWBW from the start for a +robust OS and software environment. + +Duodyne is a new design which integrates many functions into larger, modular +boards on a backplane. The intent is to create a powerful and capable system +like an SBC, but with modularity and an expandable backplane. -### Duodyne Z80 System +* Creator: Andrew Lynch +* Retrobrew Forums: [Introducing duodyne retrocomputer](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=765) +* Github: [DuoDyne](https://github.com/lynchaj/duodyne) #### ROM Image File: DUO_std.rom | | | |-------------------|---------------| +| Bus | Duo | | Default CPU Speed | 8.000 MHz | | Interrupts | Mode 2 | | System Timer | CTC | @@ -152,20 +172,21 @@ program the image into the first 512KB of the ROM for now. - SPK: IO=148 - CTC: IO=96, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} -## Dyno +## Dyno Z180 SBC -### Dyno Z180 SBC +The Dyno Computer is a Zilog Z180-based computer initially designed to run Wayne Warthen’s ROMWBW + +* Creator: Steve García +* Google Groups: [An Introduction](https://groups.google.com/g/retro-comp/c/niwPLsuc8R0) +* Website: [Dyno Computer](http://dynocomputer.fun/) #### ROM Image File: DYNO_std.rom | | | |-------------------|---------------| +| Bus | Dyno•Bus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -186,25 +207,30 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=76, MASTER - PPIDE: IO=76, SLAVE -#### Notes: - `\clearpage`{=latex} -## EP Mini-ITX +## EP Mini-ITX Z180 -### EP Mini-ITX Z180 +EtchedPixels Z180 Mini-ITX. The SC126 was almost my ideal retrobrew Z80/Z180 system but +with a couple of niggles and lack of a convenient case option. +This is the same core Z180 CPU/RAM/ROM design taken the other direction, of expandability. + +* Creator: Alan Cox +* Google Groups: [Another new board](https://groups.google.com/g/rc2014-z80/c/rhXBX9ff184) +* Github: [Z180MiniITX](https://github.com/EtchedPixels/Z180MiniITX) #### ROM Image File: EPITX_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|--------------| +| Bus | RCBus + UEXT | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware @@ -220,18 +246,28 @@ program the image into the first 512KB of the ROM for now. - FD: MODE=EPFDC, IO=72, DRIVE 1, TYPE=3.5" HD - SD: MODE=EPITX, IO=66, UNITS=1 -#### Notes: - `\clearpage`{=latex} -## Easy Z80 +## Easy/Tiny Z80 ### Easy Z80 SBC +This project is a simple, easy to understand, yet capable single board computer. +It reuses the same memory paging mechanism I've implemented in Zeta SBC V2. +It uses Zilog Z80 SIO/O and Z80 CTC peripheral ICs and implements daisy chain +mode 2 interrupt configuration + +(Not to be confused with EaZy80) + +* Creator: Sergey Kiselev +* Google Groups: [Easy Z80 - Single Board Computer](https://groups.google.com/g/rc2014-z80/c/UfWIoJgm9Gs) +* Github: [Easy_Z80](https://github.com/skiselev/easy_z80) + #### ROM Image File: EZZ80_easy_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 10.000 MHz | | Interrupts | Mode 2 | | System Timer | CTC | @@ -269,18 +305,23 @@ program the image into the first 512KB of the ROM for now. - SD: MODE=PIO, IO=105, UNITS=1 - CTC: IO=136, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### Tiny Z80 SBC +Tiny Z80 is a business card sized (size?!) single board computer (SBC). +It is mostly compatible with Easy Z80, and offers similar capabilities +Tiny Z80 includes a USB to Serial converter IC on board connected to one +of the SIO ports, for ease of use with modern computers. + +* Creator: Sergey Kiselev +* Github: [Tiny_Z80](https://github.com/skiselev/tiny_z80) + #### ROM Image File: EZZ80_tiny_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 16.000 MHz | | Interrupts | Mode 2 | | System Timer | CTC | @@ -318,20 +359,20 @@ program the image into the first 512KB of the ROM for now. - SD: MODE=PIO, IO=105, UNITS=1 - CTC: IO=16, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} -## FPGA Z80 +## S100 Computers FPGA Z80 SBC -### FPGA Z80 S100 +An FPGA Z80 based S100 SBC + +* Creator: John Monahan | +* Website: [S100 Computers FPGA Z80 SBC](http://www.s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm) #### ROM Image File: FZ80_std.rom | | | |-------------------|---------------| +| Bus | S100 | | Default CPU Speed | 8.000 MHz | | Interrupts | None | | System Timer | None | @@ -360,14 +401,17 @@ program the image into the first 512KB of the ROM for now. `\clearpage`{=latex} -## Genesis +## Genesis STD Z180 + +todo ??? -### Genesis STD Z180 +* Creator: Doug Jackson #### ROM Image File: GMZ180_std.rom | | | |-------------------|---------------| +| Bus | STD | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -389,20 +433,20 @@ program the image into the first 512KB of the ROM for now. - IDE: MODE=GIDE, IO=32, SLAVE - SD: MODE=GM, IO=132, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} -## Heathkit H8 +## Heath H8 Z80 System + +Turn your H8 into a RomWBW CP/M computer -### Heath H8 Z80 System +* Creator: Les Bird +* Github Wiki: [H8-Z80-ROMWBW-V1.0](https://github.com/sebhc/sebhc/wiki/H8-Z80-ROMWBW-V1.0) #### ROM Image File: HEATH_std.rom | | | |-------------------|---------------| +| Bus | H8 | | Default CPU Speed | 16.384 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -428,18 +472,21 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - AY38910: MODE=MSX, IO=160, CLOCK=1789772 HZ -#### Notes: - `\clearpage`{=latex} ## Mark IV Z180 SBC -### Mark IV Z180 SBC +The Z180 Mark IV is a single board computer, meaning it may run stand-alone. +It also has an interface to the RetroBrew bus (ECB) for access to additional peripheral boards. + +* Creator: John Coffman +* Retrobrew Wiki: [Z180 Mark IV](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:z180_mark_iv:z180_mark_iv) #### ROM Image File: MK4_std.rom | | | |-------------------|---------------| +| Bus | ECB | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -473,20 +520,22 @@ program the image into the first 512KB of the ROM for now. - IDE: MODE=MK4, IO=128, SLAVE - SD: MODE=MK4, IO=137, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} -## NABU +## NABU w/ RomWBW Option Board + +No modifications to the NABU motherboard needed. Leave the standard NABU ROM in its socket +on the motherboard, no need to remove it. You can switch back to standard NABU mode +by changing one jumper on the Option Card -### NABU w/ RomWBW Option Board +* Creator: Les Bird +* Github Wiki: [NABU RomWBW Option Card](https://github.com/sebhc/sebhc/wiki/NABU#nabu-romwbw-option-card) #### ROM Image File: NABU_std.rom | | | |-------------------|---------------| +| Bus | NABU | | Default CPU Speed | 3.580 MHz | | Interrupts | Mode 2 | | System Timer | TMS | @@ -514,21 +563,35 @@ program the image into the first 512KB of the ROM for now. `\clearpage`{=latex} -## Nhyodyne +## Nhyodyne Z80 MBC + +Nhyodyne: A Modular Backplane Computer (MBC). -### Nhyodyne Z80 MBC +The purpose of this project is to revisit the design concepts behind my original +Z80 SBC (aka test prototype) which has evolved into the SBC V2-005 over several +years. Attempt to introduce some new concepts to make the design more modular, +flexible, and less expensive. + +The MBC consists of four core boards: Z80 backplane, Z80 processor, Z80 clock, +and Z80 ROM. These are sufficient to build a working system of minimum capability. + +* Creator: Andrew Lynch +* Retrobrew Forums: [Z80 Multi Board Computer](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=568) +* Github: [NhyoDyne](https://github.com/lynchaj/nhyodyne) +* Retrobrew Wiki: [Z80 Modular Backplane Computer](https://www.retrobrewcomputers.org/doku.php?id=builderpages:lynchaj:start) #### ROM Image File: MBC_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 8.000 MHz | -| Interrupts | None | -| System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | MBC | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|------------| +| Bus | MBC | +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 38400 Baud | +| Memory Manager | MBC | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware @@ -559,27 +622,37 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=96, SLAVE - SPK: IO=112 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ## RetroBrew Z80 -### RetroBrew Z80 SBC +### RetroBrew Z80 SBC V2 + +The SBC V2 is a Zilog Z80 processor board. It's a 100x160mm board that is capable of +functioning both as a standalone SBC or as attached to the ECB bus. + +Previously known as the N8VEM SBC, after Andrews Ham radio call sign, development +began in 2006 wth V1 and is currently still in development, it launched a tsunami +of developments based on the Euro Card Bus (ECB) standard. + +* Creator: Andrew Lynch +* Github: [SBC-V2-005](https://github.com/b1ackmai1er/SBC-V2-005) (May not be official) +* Github: [SBC-V2-004](https://github.com/b1ackmai1er/SBC-V2-004) +* Retrobrew Wiki: [SBC V2](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:sbc_v2:start) +* Blog: [Building the SBCV2 Z80](https://simmohacks.com/wordpress/2018/11/17/building-the-retrobrew-computers-ecb-sbcv2-z80-computer) #### ROM Image File: SBC_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 8.000 MHz | -| Interrupts | None | -| System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | SBC | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|------------| +| Bus | ECB | +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 38400 Baud | +| Memory Manager | SBC | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware @@ -605,18 +678,17 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=96, MASTER - PPIDE: IO=96, SLAVE -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### RetroBrew Z80 SimH +Image for Altair Z80 SimH emulator + #### ROM Image File: SBC_simh.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 8.000 MHz | | Interrupts | Mode 1 | | System Timer | SimH | @@ -633,22 +705,27 @@ program the image into the first 512KB of the ROM for now. - MD: TYPE=ROM - HDSK: IO=253, DEVICE COUNT=2 - #### Notes: -- Image for SimH emulator - CPU speed and Serial configuration not relevant in emulator `\clearpage`{=latex} -## RetroBrew N8 +## N8 Z180 SBC + +The N8 is intended to be a “home brew” style computer in the style of early 1980's +all-in-one home computers with a usable set of features such as color graphics, +audio, an assortment of mass storage options, a variety of ports, etc. Although +a bus expansion is supported no additional boards are required. -### RetroBrew N8 Z180 SBC +* Creator: Andrew Lynch +* Retrobrew Wiki: [The N8](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:n8:n8) #### ROM Image File: N8_std.rom | | | |-------------------|---------------| +| Bus | ECB | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -673,7 +750,6 @@ program the image into the first 512KB of the ROM for now. #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present - SD Card interface is configured for CSIO (N8 date code >= 2312) `\clearpage`{=latex} @@ -682,10 +758,13 @@ program the image into the first 512KB of the ROM for now. ### RCBus Z80 CPU Module +Generic Rom Image. + #### ROM Image File: RCZ80_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 7.372 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -722,18 +801,17 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### RCBus Z80 CPU Module (KIO) +Generic Rom Image. SIO Serial baud rate managed by CTC + #### ROM Image File: RCZ80_kio_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 7.372 MHz | | Interrupts | Mode 2 | | System Timer | CTC | @@ -770,19 +848,23 @@ program the image into the first 512KB of the ROM for now. - KIO: IO=128 - CTC: IO=132, TIMER MODE=TIMER/16, DIVISOR=9216, HI=256, LO=36, INTERRUPTS ENABLED -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present -- SIO Serial baud rate managed by CTC - `\clearpage`{=latex} ### Z80-512K CPU/RAM/ROM Module +Z80-512K is an RCBus and RC2014* compatible module, designed to run RomWBW firmware +including CP/M, ZSDOS, and various applications under these OSes. Z80-512K combines +functionality of CPU, RAM, and ROM on a single module, thus saving space on the backplane. + +* Creator: Sergey Kiselev +* Google Groups: [Z80-512K](https://groups.google.com/g/rc2014-z80/c/SkOqm_LX910) +* Github: [Z80-512K](https://github.com/skiselev/Z80-512K) + #### ROM Image File: RCZ80_skz_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 7.372 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -819,18 +901,27 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC Z80 CPU Module -`\clearpage`{=latex} +ZRC is derived from the ZoRC experiment. The basic notion is that large RAM and fast +serial upload enable a diskless CP/M SBC. However, just in case that idea didn't work +out, ZRC has an optional compact flash interface. The targeted software for ZRC is ROMWBW. + +ZRC is actually contains no ROM and 2MB of RAM. The first 512KB of RAM is loaded from +disk and then handled like ROM. + +TODO The differences in these 2 builds needs highlighting -### Z80 ZRC CPU Module +* Creator: Bill Shen +* Retrobrew Wiki: [ZRC, Z80 RAM CPLD for ROMWBW](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc) #### ROM Image File: RCZ80_zrc_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -869,20 +960,19 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ZRC is actually contains no ROM and 2MB of RAM. The first 512KB - of RAM is loaded from disk and then handled like ROM. -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC Z80 CPU Module (RAM) -`\clearpage`{=latex} +ROMless boot -- HBIOS is loaded from disk at boot -### Z80 ZRC CPU Module (RAM) +TODO Unsure what he differences are ??? #### ROM Image File: RCZ80_zrc_ram_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -920,19 +1010,22 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC512 Z80 CPU Module -`\clearpage`{=latex} +ZRC512 is a faster and hobbyist-friendly variant of ZRC. +It is designed specifically for ROM-less RomWBW. HBIOS is loaded from disk at boot -### Z80 ZRC512 CPU Module +* Creator: Bill Shen +* Google Groups: [Bill Shen's ZRC512 SBC / RC2014 board](https://groups.google.com/g/retro-comp/c/bILDMVI97vo) +* Retrobrew Wiki: [ZRC512, A Hobbyist-friendly Z80 SBC for ROM-less RomWBW](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc512:zrc512home) #### ROM Image File: RCZ80_zrc512_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 22.000 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -970,19 +1063,26 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### EaZy80-512 Z80 CPU Module -`\clearpage`{=latex} +Eazy80-512 is Eazy80 rev2 pc board configured with 512K RAM to run RomWBW. +The design was derived from modifications to Eazy80 Rev1 that supported RomWBW. -### Z80 EaZy80-512 CPU Module +HBIOS is loaded from disk at boot by ROM monitor + +(Not to be confused with EasyZ80) + +* Creator: Bill Shen +* VCF Forums: [Eazy80, a glue-less, CP/M capable Z80 SBC](https://forum.vcfed.org/index.php?threads/eazy80-a-glue-less-cp-m-capable-z80-sbc.1251160) +* Retrobrew Wiki: [Eazy80 Rev2, Glue-less Configuration](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:eazy80:eazy80rev2:eazy80rev2home) #### ROM Image File: RCZ80_ez512_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 22.000 MHz | | Interrupts | Mode 2 | | System Timer | None | @@ -1002,19 +1102,21 @@ program the image into the first 512KB of the ROM for now. - KIO: IO=0 - CTC: IO=4 -#### Notes: +`\clearpage`{=latex} -- HBIOS is loaded from disk at boot by ROM monitor -- CPU speed will be dynamically measured at startup if DSRTC is present +### K80W Z80 CPU Module -`\clearpage`{=latex} +K80W is similar to K80. It is a 22MHz Z80 SBC with KIO (Z84C90) as the I/O device. +It is designed to run RomWBW. The current version is rev 2.1 replacing the older K80W rev 1 -### Z80 K80W CPU Module +* Creator: Bill Shen +* Retrobrew Wiki: [K80W Rev2.1, A RomWBW-capable Z80 SBC](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:k80:k80w_r21) #### ROM Image File: RCZ80_k80w_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 22.000 MHz | | Interrupts | Mode 2 | | System Timer | None | @@ -1052,20 +1154,19 @@ program the image into the first 512KB of the ROM for now. - KIO: IO=128 - CTC: IO=132 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ## RCBus Z180 ### RCBus Z180 CPU Module (External) +Generic Rom Image. For use with Z2 bank switched memory board (Z2 external memory management) + #### ROM Image File: RCZ180_ext_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1103,19 +1204,17 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: - -- For use with Z2 bank switched memory board (Z2 external memory management) -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### RCBus Z180 CPU Module (Native) +Generic Rom Image. For use with linear memory board (Z180 native memory management) + #### ROM Image File: RCZ180_nat_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1153,19 +1252,25 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- For use with linear memory board (Z180 native memory management) -- CPU speed will be dynamically measured at startup if DSRTC is present +### Z1RCC Z180 CPU Module -`\clearpage`{=latex} +Z1RCC is a 2“x4” RomWBW-capable Z180 SBC. + +Z1RCC has no flash memory on board but has a small (64 bytes) bootstrap ROM in CPLD +so that Z180 boots from this bootstrap ROM, copies a loader from CF disk to top 32K of RAM, +runs the loader to bring in the 480K RomWBW image from CF disk, then start RomWBW from 0x0 -### Z180 Z1RCC CPU Module +* Creator: Bill Shen +* Google Groups: [RomWBW for Z80 with 512K RAM 0K ROM](https://groups.google.com/g/retro-comp/c/29DOV4eO6MU) +* Retrobrew Wiki: [Z1RCC, A RC2014-Compatible, RomWBW-Capable Z180 SBC](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:z1rcc:rev0:home) #### ROM Image File: RCZ180_z1rcc_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1202,21 +1307,19 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: - -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ## RCBus Z280 ### RCBus Z280 CPU Module (External) +Generic Rom Image. For use with Z2 bank switched memory board (Z2 external memory management) + #### ROM Image File: RCZ280_ext_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 12.000 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -1255,18 +1358,17 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: - -- For use with Z2 bank switched memory board (Z2 external memory management) - `\clearpage`{=latex} ### RCBus Z280 CPU Module (Native) +Generic Rom Image. For use with linear memory board (Z280 native memory management) + #### ROM Image File: RCZ280_nat_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 12.000 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1304,18 +1406,25 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- For use with linear memory board (Z280 native memory management) +### ZZRCC Z280 CPU Module -`\clearpage`{=latex} +ZZRCC follows the basic concept of ZRCC that uses a small CPLD to bootstrap from CF disk. +Because Z280 has a native serial-bootstrap capability, the CPLD is even simpler than that +of ZRCC. ZZRCC is Z280 operating in Z80-compatible mode. It is designed for RC2014 bus + +ZZRCC actually contains no ROM and 512KB of RAM. The first 256KB of RAM is loaded from disk +and then handled like ROM. -### Z280 ZZRCC CPU Module +* Creator: Bill Shen +* Retrobrew Wiki: [ZZRCC, a SBC for RC2014 based on Z280](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc) #### ROM Image File: RCZ280_zzrcc_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1354,20 +1463,22 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} -- ZZRCC actually contains no ROM and 512KB of RAM. The first 256KB - of RAM is loaded from disk and then handled like ROM. -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZZRCC Z280 CPU Module (RAM) -`\clearpage`{=latex} +todo need to clarify the differences in the RAM vs STD versions -### Z280 ZZRCC CPU Module (RAM) +ROMless boot -- HBIOS is loaded from disk at boot + +* Creator: Bill Shen +* Retrobrew Wiki: [ZZRCC, a SBC for RC2014 based on Z280](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc) #### ROM Image File: RCZ280_zzrcc_ram_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1405,19 +1516,23 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZZ80MB Z280 SBC -`\clearpage`{=latex} +ZZ80MB is a Z280-based motherboard with RC2014 expansion slots. It is based on the ZZ80RC-CF design, +but with two additional expansion slots added. ZZ80MB is designed with an EPROM programmer function +such that it can boot from serial port, load EPROM programming image through the serial port +and program an EPROM. This feature can be used to program EPROM for other computers -### Z280 ZZ80MB SBC +* Creator: Bill Shen +* Retrobrew Wiki: [ZZ80MB, A Z280-based SBC with RC2014 Expansion](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zz80mb:zz80mbr3) #### ROM Image File: RCZ280_zz80mb_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 12.000 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1456,20 +1571,24 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +## RCBus eZ80 CPU Module -`\clearpage`{=latex} +The eZ80 for RCBus/RC2014 is a module designed for the RCBus and RC2014 backplanes. -## RCBus eZ80 +Its designed as a 'compatible upgrade' to the stock Z80 CPU. The eZ80 is a CPU that was +first released by Zilog about 20 years ago, and still available from the manufacturer today -### RCBus eZ80 CPU Module +* Creator: Dean Netherton +* Github: [eZ80 for the RCBus/RC2014](https://github.com/dinoboards/ez80-for-rc) +* Hackaday: [eZ80 CPU for RC2014 and other backplanes](https://hackaday.io/project/196330-ez80-cpu-for-rc2014-and-other-backplanes) #### ROM Image File: RCEZ80_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 20.000 MHz | | Interrupts | Mode 1 | | System Timer | EZ80 | @@ -1499,18 +1618,22 @@ program the image into the first 512KB of the ROM for now. - EZ80: RTC DRIVER - EZ80: UART DRIVER -#### Notes: - `\clearpage`{=latex} -## Rhyophyre +## Rhyophyre Z180 SBC + +Single Board Computer featuring Zilog Z180 processor and NEC µPD7220 +Graphics Display Controller -### Rhyophyre Z180 SBC +* Creator: Andrew Lynch +* Retrobrew Forums: [Z180 upd7220 GDC SBC](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=699) +* Github: [rhyophyre](https://github.com/lynchaj/rhyophyre) #### ROM Image File: RPH_std.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 18.432 MHz | | Interrupts | None | | System Timer | None | @@ -1531,20 +1654,26 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=136, MASTER - PPIDE: IO=136, SLAVE -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +## S100 Computers Z180 SBC -`\clearpage`{=latex} +A Z180 board which contains a flash RAM, a USB port interface and an SD Card that can immediately boot up CPM. +While it is on an S100 Bus board, initially that board has only 8 significant chips and works as a self contained +computer outside the bus with a simple 9V power supply. -## S100 +Later on it can be built up further with more chips, placed in an S100 bus and one by one programed to interface +with the 100's of S100 bus cards that are out there. It can in fact behave as a S100 bus master or slave +as defined by the IEEE-696 specs. -### S100 Computers Z180 +* Creator: John Monahan | +* Website: [S100 Computers Z180 SBC](http://www.s100computers.com/My%20System%20Pages/Z180%20SBC/Z180%20SBC.htm) #### ROM Image File: S100_std.rom | | | |-------------------|---------------| +| Bus | S100 | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1579,12 +1708,28 @@ program the image into the first 512KB of the ROM for now. ## Small Computer Central Z180 +Small Computer Central provides an extensive range hardware based around the +Zilog ecosystem. This section lists configurations specifically for the Z180 processor + +If you are using a Z80 processor you will probably be using the general `RCZ80_std` +configuration - [RCBus Z80 CPU Module]. However please consult +[Firmware, RomWBW, RCZ80_std](https://smallcomputercentral.com/firmware/firmware-romwbw-rcz80_std/) +for furher information and to ensure compatibility with your Z80 system. + +* Creator: Stephen Cousins +* Website: [Small Computer Central](https://smallcomputercentral.com) + ### SC126 Z180 SBC +SC126 is a Z180 Motherboard. + +* Website: [SC126 – Z180 Motherboard](https://smallcomputercentral.com/rcbus/sc100-series/sc126-z180-motherboard-rc2014/) + #### ROM Image File: SCZ180_sc126_std.rom | | | |-------------------|---------------| +| Bus | BP80 | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1623,7 +1768,6 @@ program the image into the first 512KB of the ROM for now. #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present - When disabled, watchdog requires /IM to be pulsed. If an RCBus module holds the CPU in WAIT for more than this, the watchdog will fire when disabled with random consequences. The Pico SD does this at power-on. @@ -1632,10 +1776,15 @@ program the image into the first 512KB of the ROM for now. ### SC130 Z180 SBC +SC130 is an entry-level Z180 Motherboard designed primarily to run RomWBW (and CP/M) + +* Website: [SC136 – Z180 Motherboard](https://smallcomputercentral.com/rcbus/sc100-series/sc130-z180-motherboard) + #### ROM Image File: SCZ180_sc130_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1673,18 +1822,19 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### SC131 Z180 Pocket Comp +SC131 is a pocket-sized Z180 RomWBW CP/M computer. + +* Website: [SC131 – Z180 Pocket Computer](https://smallcomputercentral.com/sc131-z180-pocket-computer/) + #### ROM Image File: SCZ180_sc131_std.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1702,16 +1852,19 @@ program the image into the first 512KB of the ROM for now. - MD: TYPE=ROM - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: - `\clearpage`{=latex} ### SC140 Z180 CPU Module +SC140 is a Z180 SBC / Z50Bus Card card. + +* Website: [SC140 – Z180 SBC / Z50Bus Card](https://smallcomputercentral.com/z50bus-4/sc140-z180-sbc-z50bus-card/) + #### ROM Image File: SCZ180_sc140_std.rom | | | |-------------------|---------------| +| Bus | Z50 | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1749,18 +1902,19 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### SC503 Z180 CPU Module +SC503 is a Z180 Processor card designed for Z50Bus. + +* Website: [SC503 – Z180 Processor (Z50Bus)](https://smallcomputercentral.com/z50bus-4/sc503-z180-processor-z50bus/) + #### ROM Image File: SCZ180_sc503_std.rom | | | |-------------------|---------------| +| Bus | Z50 | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1798,18 +1952,22 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - `\clearpage`{=latex} ### SC700 Z180 CPU Module +This configuration is specifically for systems based on the +Z180 CPU (eg. SC722) with 1MB linear memory (eg. SC721) + +* Website: [SC700 Series](https://smallcomputercentral.com/rcbus/sc700-series/) +* Website: [SC721 – RCBus Memory Module](https://smallcomputercentral.com/rcbus/sc700-series/sc721-rcbus-memory-module/) +* Website: [SC722 – RCBus Z180 CPU Module](https://smallcomputercentral.com/rcbus/sc700-series/sc722-rcbus-z180-cpu-module/) + #### ROM Image File: SCZ180_sc700_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1848,20 +2006,25 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: +\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +## Z80-Retro SBC -\clearpage`{=latex} +The system comprises a Z80 retro computer board, and optonal VGA text video card, +and PIO Keyboard and Sound Card. The system uses a custom 60 pin bus on a standard header. -## Z80-Retro +(Not to be confused with a similar named project presented by John's Basement on youTube) -### Z80-Retro SBC +* Creator: Peter Wilson +* Github: [Z80-Retro](https://github.com/peterw8102/Z80-Retro) +* Github Wiki: [Welcome to the Z80-Retro wiki!](https://github.com/peterw8102/Z80-Retro/wiki) +* OSHWLab: [Simple Z80 SBC](https://oshwlab.com/peterw8102/simple-z80) #### ROM Image File: Z80RETRO_std.rom | | | |-------------------|---------------| +| Bus | 60 pin | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 2 | | System Timer | None | @@ -1878,18 +2041,21 @@ program the image into the first 512KB of the ROM for now. - MD: TYPE=ROM - SD: MODE=Z80R, IO=104, UNITS=1 -#### Notes: - `\clearpage`{=latex} -## Zeta +## Zeta Z80 SBC + +Zeta SBC is an Zilog Z80 based single board computer. It is inspired by Ampro Little Board Z80 +and N8VEM project. Zeta SBC is software compatible with N8VEM SBC and Disk I/O boards. -### Zeta Z80 SBC +* Creator: Sergey Kiselev +* Retrobrew Wiki: [Zeta SBC](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:zeta:start) #### ROM Image File: ZETA_std.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 8.000 MHz | | Interrupts | None | | System Timer | None | @@ -1911,7 +2077,6 @@ program the image into the first 512KB of the ROM for now. #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present - If ParPortProp is installed, initial console output is determined by JP1: - Shorted: console to on-board serial port @@ -1919,14 +2084,26 @@ program the image into the first 512KB of the ROM for now. `\clearpage`{=latex} -## Zeta V2 +## Zeta V2 Z80 SBC + +Zeta SBC V2 is a redesigned version of Zeta SBC. + +Compared to the first version this version features updated MMU with four banks, each one of +those banks can be mapped to any 16 KiB page in 1 MiB on-board memory. It adds Z80 CTC which +is used for generating periodic interrupts and as a vectored interrupt controller for UART +and PPI. The FDC is replaced with 37C65. Compared to FDC9266 used in Zeta SBC it integrates +input/output buffers and floppy disk control latch. Additionally 37C65 FDC is easier to obtain +than FDC9266. And lastly it is made using CMOS technology and more power efficient than FDC9266 -### Zeta V2 Z80 SBC +* Creator: Sergey Kiselev +* Github: [Zeta SBC V2](https://github.com/skiselev/zeta_sbc) +* Retrobrew Wiki: [Zeta SBC V2](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:zetav2:start) #### ROM Image File: ZETA2_std.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 8.000 MHz | | Interrupts | Mode 2 | | System Timer | CTC | @@ -1949,7 +2126,6 @@ program the image into the first 512KB of the ROM for now. #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present - If ParPortProp is installed, initial console output is determined by JP1: - Shorted: console to on-board serial port