From b560f1d3a9ecb3fb574b7aea529c663558a5f383 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Thu, 30 May 2019 19:31:00 +0800
Subject: [PATCH 01/16] Resync

---
 Source/HBIOS/hbios.asm | 70 +++++++++++++++++++++++++++++++-----------
 Source/HBIOS/std.asm   | 16 +++++-----
 2 files changed, 60 insertions(+), 26 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 0b5b113b..3773112a 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -945,11 +945,13 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	LD	HL,MSG_HBVER
 	CALL	DSKY_SHOWSEG
 #ENDIF
-
-#IF	(WBWDEBUG=USEMIO)		; BUFFER OUTPUT UNTIL
+;
+#IF (WBWDEBUG == USEMIO)		; BUFFER OUTPUT UNTIL
 	CALL	MIO_INIT		; WE GET TO BOOT MESSAGE
 #ENDIF
 ;
+#IF 0
+;
 ; TEST DEBUG ***************************************************************************************
 ;
 	PRTS("DEBUG-IVT$")
@@ -959,6 +961,7 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 ;
 ; TEST DEBUG ***************************************************************************************
 ;
+#ENDIF
 ;
 ; DISCOVER CPU TYPE
 ;
@@ -1031,7 +1034,8 @@ HB_CPU1:
 ;
 ; PRE-CONSOLE INITIALIZATION
 ;
-
+#IF 0
+;
 ; TEST DEBUG ***************************************************************************************
 ;
 	CALL	NEWLINE
@@ -1039,6 +1043,8 @@ HB_CPU1:
 ;
 ; TEST DEBUG ***************************************************************************************
 ;
+#ENDIF
+;
 #IF (ASCIENABLE)
 	CALL	ASCI_PREINIT
 #ENDIF
@@ -1054,12 +1060,17 @@ HB_CPU1:
 #IF (PIO_4P | PIO_ZP)
 	CALL	PIO_PREINIT
 #ENDIF
+;
+#IF 0
+;
 ; TEST DEBUG ***************************************************************************************
 ;
 	CALL	NEWLINE
 	CALL	REGDMP
 ;
 ; TEST DEBUG ***************************************************************************************
+;
+#ENDIF
 ;
 	DIAG(%01111111)
 ;
@@ -1070,7 +1081,7 @@ HB_CPU1:
 	XOR	A			; INITIALLY, FIRST SERIAL UNIT IS CONSOLE
 	LD	(CB_CONDEV),A		; SAVE IT, ACTIVATES CONSOLE ON HBIOS
 
-#IF	(WBWDEBUG=USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
+#IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
 	LD	E,(HL)
 	INC	HL
@@ -1088,6 +1099,8 @@ NXTMIO:	LD	A,(HL)
 ;	CALL	WRITESTR		; WRITESTR WILL WORK WILL ONLY PRINT UP TO FIRST $
 #ENDIF
 ;
+#IF 0
+;
 ; TEST DEBUG ***************************************************************************************
 ;
 	CALL	NEWLINE2
@@ -1097,6 +1110,8 @@ NXTMIO:	LD	A,(HL)
 ;
 ; TEST DEBUG ***************************************************************************************
 ;
+#ENDIF
+;
 ; ANNOUNCE HBIOS
 ;
 	CALL	NEWLINE2
@@ -1322,16 +1337,34 @@ PSCNX	.EQU	$ + 1
 ;
 	CALL	NEWLINE2
 	PRTX(STR_PLATFORM)
+;
+	LD	A,(HB_CPUTYPE)		; GET CPU TYPE
+	OR	A			; SET FLAGS
+	LD	DE,HB_STRZ80		; Z80
+	JR	Z,HB_PCPU		; IF Z80, PRINT IT
+	DEC	A			; NEXT CPU TYPE
+	LD	DE,HB_STRZ180		; Z80180
+	JR	Z,HB_PCPU		; IF Z80180, PRINT IT
+	DEC	A			; NEXT CPU TYPE
+	LD	DE,HB_STRZS180K		; Z8S180 REV K
+	JR	Z,HB_PCPU		; IF Z8S180-K, PRINT IT
+	LD	DE,HB_STRZS180N		; Z8S180 REV N
+	JR	HB_PCPU			; PRINT Z8S180-N
+;
+HB_STRZ80	.TEXT	" Z80$"
+HB_STRZ180	.TEXT	" Z80180$"
+HB_STRZS180K	.TEXT	" Z8S180-K$"
+HB_STRZS180N	.TEXT	" Z8S180-N$"
+;
+HB_PCPU:
+	CALL	WRITESTR		; PRINT IT
+;
 	PRTS(" @ $")
 	LD	HL,(CB_CPUKHZ)
 	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
 	PRTS("MHz$")
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-	LD	A,(HB_CPUTYPE)		; GET CPU TYPE
-	PRTS(" REV=$")
-	ADD	A,$30			; MAKE DISPLAYABLE DIGIT
-	CALL	COUT
 	PRTS(" IO=0x$")
 	LD	A,Z180_BASE
 	CALL	PRTHEXBYTE
@@ -1339,8 +1372,6 @@ PSCNX	.EQU	$ + 1
 ;
 ; DISPLAY CPU CONFIG
 ;
-	;CALL	PRTSTRD
-	;.TEXT	", $"
 	CALL	NEWLINE
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
 	LD	A,Z180_MEMWAIT
@@ -2746,10 +2777,10 @@ SIZ_PIO		.EQU	$ - ORG_PIO
 #INCLUDE "bcd.asm"
 #INCLUDE "decode.asm"
 ;
-#IF	WBWDEBUG=USEXIO
+#IF (WBWDEBUG == USEXIO)
 #INCLUDE "xio.asm"
 #ENDIF
-#IF	WBWDEBUG=USEMIO
+#IF (WBWDEBUG == USEMIO)
 #INCLUDE "mio.asm"
 #ENDIF
 ;
@@ -3544,11 +3575,12 @@ COUT:
 ;
 COUT1:
 ;	
-#IF	WBWDEBUG=USEXIO
+#IF (WBWDEBUG == USEXIO)
 	LD	A,E			; GET OUTPUT CHAR BACK TO ACCUM
 	CALL	XIO_OUTC		; OUTPUT VIA XIO
 #ENDIF
-#IF	WBWDEBUG=USEMIO
+;
+#IF (WBWDEBUG == USEMIO)
 	LD	A,E
 	CALL	MIO_OUTC		; OUTPUT VIA MIO
 #ENDIF
@@ -3582,10 +3614,11 @@ CIN:
 ;
 CIN1:
 ;
-#IF	WBWDEBUG=USEXIO
+#IF (WBWDEBUG == USEXIO)
 	CALL	XIO_INC			; GET CHAR
 #ENDIF
-#IF	WBWDEBUG=USEMIO
+;
+#IF (WBWDEBUG == USEMIO)
 	CALL	MIO_INC			; GET CHAR
 #ENDIF
 ;
@@ -3617,10 +3650,11 @@ CST:
 ;
 CST1:
 ;
-#IF	WBWDEBUG=USEXIO
+#IF (WBWDEBUG == USEXIO)
 	CALL	XIO_IST			; GET STATUS
 #ENDIF
-#IF	WBWDEBUG=USEMIO
+;
+#IF (WBWDEBUG == USEMIO)
 	CALL	MIO_IST			; GET STATUS
 #ENDIF
 ;
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 371c5299..e7822b92 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -276,31 +276,31 @@ IVT_PIO3	.EQU	24
 ; SET PLATFORM NAME STRING
 ;
 #IF (PLATFORM == PLT_SBC)
-  #DEFINE 	PLATFORM_NAME	"SBC Z80"
+  #DEFINE 	PLATFORM_NAME	"SBC"
 #ENDIF
 #IF (PLATFORM == PLT_ZETA)
-  #DEFINE 	PLATFORM_NAME	"ZETA Z80"
+  #DEFINE 	PLATFORM_NAME	"ZETA"
 #ENDIF
 #IF (PLATFORM == PLT_ZETA2)
-  #DEFINE 	PLATFORM_NAME	"ZETA Z80 V2"
+  #DEFINE 	PLATFORM_NAME	"ZETA V2"
 #ENDIF
 #IF (PLATFORM == PLT_N8)
-  #DEFINE 	PLATFORM_NAME	"N8 Z180"
+  #DEFINE 	PLATFORM_NAME	"N8"
 #ENDIF
 #IF (PLATFORM == PLT_MK4)
-  #DEFINE 	PLATFORM_NAME	"MARK IV Z180"
+  #DEFINE 	PLATFORM_NAME	"MARK IV"
 #ENDIF
 #IF (PLATFORM == PLT_UNA)
   #DEFINE	PLATFORM_NAME	"UNA"
 #ENDIF
 #IF (PLATFORM == PLT_RCZ80)
-  #DEFINE	PLATFORM_NAME	"RC2014 Z80"
+  #DEFINE	PLATFORM_NAME	"RC2014"
 #ENDIF
 #IF (PLATFORM == PLT_RCZ180)
-  #DEFINE	PLATFORM_NAME	"RC2014 Z180"
+  #DEFINE	PLATFORM_NAME	"RC2014"
 #ENDIF
 #IF (PLATFORM == PLT_EZZ80)
-  #DEFINE	PLATFORM_NAME	"EASY Z80"
+  #DEFINE	PLATFORM_NAME	"EASY"
 #ENDIF
 ;
 ; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS

From 248097630810ccc342cd0f00343eb18827accfc7 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 14 Jul 2019 20:38:51 +0800
Subject: [PATCH 02/16] Update pio.asm

Major restructure
---
 Source/HBIOS/pio.asm | 1200 ++++++++++++++++++++++++++----------------
 1 file changed, 742 insertions(+), 458 deletions(-)

diff --git a/Source/HBIOS/pio.asm b/Source/HBIOS/pio.asm
index e9327111..841c04ad 100644
--- a/Source/HBIOS/pio.asm
+++ b/Source/HBIOS/pio.asm
@@ -3,46 +3,58 @@
 ;
 ; HBIOS initializes driver by:
 ;
-; 1) Performing Pre-initialization
+; 1) Calling Pre-initialization
 ;
-;    This involves setting up all the data structures decribing the devices.
+;    This involves setting up all the data structures describing the devices.
 ;    If possible, do a hardware test to verify it is available for adding to available devices.
 ;
-; 2) Performing individual device/unit initialization.
+; 2) Calling device initialization.
 ;
 ;    Hardware initialization.
 ;    Configure to initial state or to a new state.
+;
 ; Implementation limitations:
 ;
 ; The fully functionality of the Z80 PIO can only be realized by using Z80 interrupt mode 2.
 ; Registers cannot be interrogated for interrupts status and the originating interrupt
 ; device cannot be determine.
 ;
-; Full implementation of IM2 functionality in an ECB-ZP and ECB-4P board would require the 
-; allocation of an interrupt handler for each chip channel. Thus, 10 interrupt handler
+; Full implementation of IM2 functionality for an ECB-ZP and ECB-4P board would require the 
+; allocation of an interrupt handler for each chip channel. Thus, 12 interrupt handlers
 ; would be required to support this configuration. As the HBIOS only has an allocation of
 ; 16, a full implmentation is impractical.
 ;
-; The compromise solution is for the driver to allow IM2 only on the first PIO on each board.
-; So, a ECB-4PIO would be fully interrupt drived in all modes but a ECB-ZP would only allow
-; PIO 0 to be interrupt drived and PIO 1,2,3 would be limited to Bit mode or blind read and
-; writed to the input/output ports.
+; The compromise solution is to allow 4 interrupts for the PIO driver.; All remaining PIO's
+; are limited to Bit mode or blind read and writed to the input/output ports.
 ;
 ; Zilog PIO reset state:
 ;
-; Both port mask registers are reset to inhibit All port data bits.
-; Port data bus lines are set to a high-impedance state and the Ready "handshake"
-; Mode 1 is automatically selected.
-; The vector address registers are not reset.
-; Both port interrupt enable flip-flops are reset.
-; Both port output registers are reset.
-;
-; Program a channel
-;
-;		LD		C,PIOBC		; C -> PIO Channel B control
-;		LD		B,5		; 5 bytes to send
-;		LD		HL,PT		; HL -> Initialization data
-;		OTIR				; send bytes
+;	Both port mask registers are reset to inhibit All port data bits.
+;	Port data bus lines are set to a high-impedance state and the Ready "handshake"
+;	Mode 1 (output) is automatically selected.
+;	The vector address registers are not reset.
+;	Both port interrupt enable flip-flops are reset.
+;	Both port output registers are reset.
+;
+; Register addressing for ECB-ZP and ECB-4P assuming base address 90h and 88h respectively.
+;
+; PIO ----ZP---- ----4P----
+;  0  DATA 0 90h DATA 0 B8h
+;  0  DATA 1 91h DATA 1 B9h
+;  0  CMD  0 92h CMD  0 BAh
+;  0  CMD  1 93h CMD  1 BBh
+;  1  DATA 0 94h DATA 0 BCh
+;  1  DATA 1 95h DATA 1 BDh
+;  1  CMD  0 96h CMD  0 BEh
+;  1  CMD  1 97h CMD  1 BFh
+;  2             DATA 0 C0h
+;  2             DATA 1 C1h
+;  2             CMD  0 C2h
+;  2             CMD  1 C3h
+;  3             DATA 0 C4h
+;  3             DATA 1 C5h
+;  3             CMD  0 C6h
+;  3             CMD  1 C7h
 ;
 PIODEBUG	.EQU	1
 ;
@@ -58,307 +70,613 @@ PIO_ZPIO	.EQU	1
 PIO_8255	.EQU	2
 PIO_PORT	.EQU	3
 
-;INT_POOL	.EQU	HBX_IVT+IVT_PIO0
+; SET MAXIMUM NUMBER OF INTERRUPTS AVAILABLE FOR ALL
+; ENSURE INTERRUPTS ARE NOT TURNED ON IF IM2 IS NOT SET.
 
 INT_ALLOC	.DB	0
 INT_N		.EQU	00000000B
 #IF	(INTMODE == 2)
-INT_Y		.EQU	INT_N
+INT_Y		.EQU	00000100B
 INT_ALLOW	.EQU	4
 #ELSE
-INT_Y		.EQU	00000100B
+INT_Y		.EQU	INT_N
 INT_ALLOW	.EQU	0
 #ENDIF
-
-INT_0		.EQU	00000000B
-INT_1		.EQU	00000001B
-INT_2		.EQU	00000010B
-INT_3		.EQU	00000011B
 ;
+INT0		.EQU	00000000B
+INT1		.EQU	00000001B
+INT2		.EQU	00000010B
+INT3		.EQU	00000011B
 ;
 ; SETUP THE DISPATCH TABLE ENTRIES
 ;
-; WE CANT PRINT ANYTHING TO HBIOS CONSOLE AT THIS POINT
 ; PIO_CNT HOLDS THE NUMBER OF DEVICED CALCULATED FROM THE NUMBER OF DEFPIO MACROS
 ; PIO_CNT SHOULD INCREASE BY 2 FOR EVERY PIO CHIP ADDED.
 ;
+; PIO_PREINIT WILL READ THROUGH ALL PIOCFG TABLES AND CONFIGURE EACH TABLE.
+; IT WITH THEN CALL PIO_INITUNIT TO INITIALIZE EACH DEVICE TO ITS DEFAULT STATE
+; 
+; EXPECTS NOTHING ON ENTRY
+;
 PIO_PREINIT:
+	CALL	NEWLINE		;D
 	LD	B,PIO_CNT		; LOOP CONTROL
 	LD	C,0			; PHYSICAL UNIT INDEX
 	XOR	A			; ZERO TO ACCUM
-	LD	(PIO_DEV),A		; CURRENT DEVICE NUMBER
+;	LD	(PIO_DEV),A		; CURRENT DEVICE NUMBER
+	LD	(INT_ALLOC),A		; START WITH NO INTERRUPTS ALLOCATED
 PIO_PREINIT0:	
 	PUSH	BC			; SAVE LOOP CONTROL
-	LD	A,C			; PHYSICAL UNIT TO A
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
+	LD	A,C			; INITIALIZE THE UNIT
+
+	PUSH	AF		;D
+	LD	A,'u'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	CALL	PRTHEXBYTE	;D	UNIT
+	CALL	PC_SPACE	;D
+
+	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
 	RLCA				; ...
 	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+	RLCA
+;	RLCA
 	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+	PUSH	AF
+	CALL	ADDHLA			; HL := ENTRY ADDRESS
+	POP	AF
 	CALL	ADDHLA			; HL := ENTRY ADDRESS
 	PUSH	HL			; SAVE IT
-	PUSH	HL			; COPY CFG DATA PTR
 	POP	IY			; ... TO IY
-	CALL	PIO_INITUNIT		; HAND OFF TO GENERIC INIT CODE
-	POP	DE			; GET ENTRY ADDRESS BACK, BUT PUT IN DE
-	POP	BC			; RESTORE LOOP CONTROL
-;
+
+	LD	(HL),C
+
+	PUSH	AF		;D
+	LD	A,'c'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	PUSH	HL		;D
+	POP	BC		;D
+	CALL	PRTHEXWORD	;D	CONFIG TABLE
+	CALL	PC_SPACE	;D
+	POP	BC		;D
+
 	LD	A,(IY+1)		; GET THE PIO TYPE DETECTED
-	OR	A			; SET FLAGS
-	JR	Z,PIO_PREINIT2		; SKIP IT IF NOTHING FOUND
-;	
-	PUSH	BC			; SAVE LOOP CONTROL
-	PUSH	AF
-	DEC	A
-	LD	BC,PIO_FNTBL		; BC := FUNCTION TABLE ADDRESS
-	JR	Z,TYPFND		; ADD ENTRY IF PIO FOUND, BC:D
-	DEC	A
-	LD	BC,PPI_FNTBL		; BC := FUNCTION TABLE ADDRESS
-	JR	Z,TYPFND
-	DEC	A
-	LD	BC,PRT_FNTBL
-	JR	NZ,TYPDUN
-TYPFND:	CALL	CIO_ADDENT		; ADD ENTRY IF PIO FOUND, BC:DE
-TYPDUN:	POP	AF
-	POP	BC			; RESTORE LOOP CONTROL
-;
-PIO_PREINIT2:	
-	INC	C			; NEXT PHYSICAL UNIT
-	DJNZ	PIO_PREINIT0		; LOOP UNTIL DONE
-;
-#IF (INTMODE == 2)
-	; SETUP PIO INTERRUPT VECTOR IN IVT
-	LD	HL,PIO0INT
-;	LD	(HBX_IVT + IVT_PIO0),HL
-	LD	(HB_IVT09 + 1),HL	; WW: IVT INDEX 9 FOR PIO0
-#ENDIF
-PIO_PREINIT3:
-	XOR	A			; SIGNAL SUCCESS
-	RET				; AND RETURN
-;
-; WHEN WE GET HERE IY POINTS TO THE PIO_CFG TABLE WE ARE WORKING ON.
-;
-PIO_INITUNIT:
-	LD	A,C			; SET THE UNIT NUMBER
-	LD	(IY),A	
+	CP	PIO_PORT		; SET FLAGS
 
-	LD	DE,-1			; LEAVE CONFIG ALONE
-	JP	PIO_INITDEV		; IMPLEMENT IT AND RETURN
-;	XOR	A			; SIGNAL SUCCESS
-;	RET				; AND RETURN
-;
-PIO_INIT:
-	LD	B,PIO_CNT		; COUNT OF POSSIBLE PIO UNITS
-	LD	C,0			; INDEX INTO PIO CONFIG TABLE
-PIO_INIT1:
-	PUSH	BC			; SAVE LOOP CONTROL
-	
-	LD	A,C			; PHYSICAL UNIT TO A
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
-	RLCA				; ...
-	RLCA				; ... TO GET OFFSET INTO CFG TABLE
-	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	PUSH	HL			; COPY CFG DATA PTR
-	POP	IY			; ... TO IY
-	
-	LD	A,(IY+1)		; GET PIO TYPE
-	OR	A			; SET FLAGS
-	CALL	NZ,PIO_PRTCFG		; PRINT IF NOT ZERO
-	
-	PUSH	DE	
-	LD	DE,$FFFF		; INITIALIZE DEVICE/CHANNEL
-	CALL	PIO_INITDEV		; BASED ON DPW
-	POP	DE
+	PUSH	AF		;D
+	LD	A,'t'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	CALL	PRTHEXBYTE	;D	TYPE
+	CALL	PC_SPACE	;D
 
-	POP	BC			; RESTORE LOOP CONTROL
-	INC	C			; NEXT UNIT
-	DJNZ	PIO_INIT1		; LOOP TILL DONE
-;
-	XOR	A			; SIGNAL SUCCESS
-	RET				; DONE
-;
-; EXAMPLE CODE
-;
-PIO_LPT:
-	IN		A,($F6)		; get device status
-	AND		$20		; device ready?
-	JR		Z,PIO_LPT	; no, busy wait
-	IN		A,($F5)		; get transmit buffer register status ready?
-	AND		$20		; ready?
-	JR		Z,PIO_LPT	; no, busy wait
-	LD		A,C		; ready, char A for output through data port
-	OUT		($F0),A		; output char
-	RET
+;	JR	Z,BADINIT
 
+;	PUSH	BC			; SAVE LOOP CONTROL
+;	LD	BC,PIO_FNTBL		; BC := FUNCTION TABLE ADDRESS	
+;	DEC	A
+;	JR	Z,TYPFND		; SKIP IT IF NOTHING FOUND
+;	LD	BC,PPI_FNTBL		; BC := FUNCTION TABLE ADDRESS
+;	DEC	A
+;	JR	Z,TYPFND		; ADD ENTRY IF PIO FOUND, BC:DE
+;	LD	BC,PRT_FNTBL
+;	DEC	A
+;	JR	Z,TYPFND
+;	POP	BC
+;	JR	BADINIT
 
+	PUSH	HL
+	LD	DE,-1			; INITIALIZE THIS DEVICE WITH
+	CALL	PIO_INITDEV		; DEFAULT VALUES
+	POP	HL
 
-; ------------------------------------
-; ZILOG PIO FUNCTION TABLE ROUTINES
-;-------------------------------------
+;	JR	NZ,SKPINIT
+
+	; AT THIS POINT WE KNOW WE
+	; HAVE A VALID DEVICE SO ADD IT
 	
-PIO_IN:
-	LD	C,(IY+3)
-	IN	A,(C)
-	LD	E,A
-	XOR	A			; SIGNAL SUCCESS
-	RET
+	LD	A,8			; CALCULATE THE FUNCTION TABLE 
+	CALL	ADDHLA			; POSITION WHICH FOLLOWS THE
+	PUSH	HL			; CONFIGURATION TABLE OF EACH
+	POP	BC			; DEVICE
 
-;
-PIO0INT:
-PIO1INT:
-PIO2INT:
-PIO3INT:
-PIO4INT:
-PIO5INT:
-PIO6INT:
-PIO7INT:
-PIO8INT:
-PIO9INT:
-	OR	$FF			; NZ SET TO INDICATE INT HANDLED
-	RET
-;
-; ON ENTRY IY POINTS TO THE DEVICE RECORD
-; E CONTAINS THE CHARACTER TO OUTPUT
-; WE RETREIVE THE CMD PORT ADDRESS AND CALCULATE THE 
-; DATA PORT AND WRITE THE CHARACTER TO IT.
-;
-PIO_OUT:
-	LD	C,(IY+3)
-	OUT	(C),E
-	XOR	A			; SIGNAL SUCCESS
-	RET
+TYPFND:	PUSH	AF		;D
+	LD	A,'f'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+	PUSH	BC		;D
+	CALL	PRTHEXWORD	;D	FUNCTION TABLE
+	POP	BC		;D
+	CALL	NEWLINE		;D
 
-	LD	C,(IY+3)		; GET PORT
-	LD	A,(IY+4)		; GET MODE (B7B6)
+	PUSH	IY			; ADD ENTRY IF PIO FOUND, BC:DE
+	POP	DE			; BC: DRIVER FUNCTION TABLE
+	CALL	CIO_ADDENT		; DE: ADDRESS OF UNIT INSTANCE DATA
 
+BADINIT:POP	BC			; RESTORE LOOP CONTROL
 
-PIO_IST:
-	RET	
-;	
-PIO_OST:
-	RET
+	INC	C			; NEXT PHYSICAL UNIT
+SKPINIT:DJNZ	PIO_PREINIT0		; LOOP UNTIL DONE
+
+	PUSH	AF		;D
+	PRTS("INTS=$")		;D
+	LD	A,(INT_ALLOC)	;D
+	CALL	PRTHEXBYTE	;D
+	POP	AF		;D
+	PUSH	DE		;D
+	LD	DE,CIO_TBL-3	;D
+	CALL	DUMP_BUFFER	;D
+	POP	DE		;D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+	
+; PIO_INITDEV - INITIALIZE DEVICE
 ;
-; PIO_INITDEV - Configure device.
-; If DE = FFFF then extract the configuration information from the table of devices and program the device using those settings.
-; Otherwise use the configuration information in DE to program those settings and save them in the device table
+; IF DE = FFFF THEN THE SETUP PARAMETER WORD WILL BE READ FROM THE DEVICE CONFIGURATION  
+; TABLE POINTED TO BY IY AND THE PIO PORT WILL BE PROGRAMMED BASED ON THAT CONFIGURATION. 
 ;
-;  SETUP PARAMETER WORD:
-;  +-------------------------------+ +-------+-----------+---+-------+
-;  |         BIT CONTROL           | | MODE  | C2 C1 C0  | A |  INT  |
-;  +-------------------------------+ --------------------+-----------+
-;    F   E   D   C   B   A   9   8     7   6   5   4   3   2   1   0
-;       -- MSB (D REGISTER) --           -- LSB (E REGISTER) --
-;
-;
-; MSB = BIT MAP USE IN MODE 3 
-; MODE B7 B6 = 00 Mode 0 Output
-;              01 Mode 1 Input
-;              10 Mode 2 Bidir
-;              11 Mode 3 Bit Mode
-; CHIP CHANNEL B5 B4 B3 001 Channel 1
-;                       010 Channel 2
-;                       100 Channel 3
-; INTERRUPT ALLOCATED B2 = 0 NOT ALLOCATED
-;                        = 1 IS ALLOCATED
-;
-; WHICH IVT IS ALLOCATES B1 B0 00 IVT_PIO0
-;                              01 IVT_PIO1
-;                              10 IVT_PIO2
-;                              11 IVT_PIO3
+; OTHERWISE THE PIO PORT WILL BE PROGRAMMED BY THE SETUP PARAMETER WORD IN DE AND THIS 
+; WILL BE SAVED IN THE DEVICE CONFIGURATION TABLE POINTED TO BY IY.
+;
+; ALL OTHER CONFIGURATION OF THE DEVICE CONFIGURATION TABLE IS DONE UPSTEAM BY PIO_PREINIT 
+
 PIO_INITDEV:
 	; TEST FOR -1 (FFFF) WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
 	LD	A,D			; TEST DE FOR
 	AND	E			; ... VALUE OF -1
 	INC	A			; ... SO Z SET IF -1
 	JR	NZ,PIO_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
-;
-	; LOAD EXISTING CONFIG TO REINIT
+PIO_INITDEV0:
+	; LOAD EXISTING CONFIG (DCW) TO REINIT
 	LD	E,(IY+4)		; LOW BYTE
 	LD	D,(IY+5)		; HIGH BYTE	
 ;
-PIO_INITDEV1:
-	; WHICH DEVICE TYPE?
+PIO_INITDEV1:				; WHICH DEVICE TYPE?
 	LD	A,(IY+1)
 	CP	PIO_ZPIO		
-	JR	Z,SET_PIO
+	JR	Z,SETPIO0
 	CP	PIO_8255
-	JR	Z,SET_8255
+	JP	Z,SET_8255
 	CP	PIO_PORT
-	JR	Z,SET_PORT
-PIO_BAD:OR	$FF			; UNKNOWN DEVICE
+	JP	Z,SET_PORT
+BAD_SET:OR	$FF			; UNKNOWN DEVICE
 	RET
 
-SET_PORT:
-	; DEVICE TYPE IS I/O PORT SO JUST WRITE $00 TO IT
-	LD	C,(IY+3)
-	OUT	(C),A
-	XOR	A
+SETPIO0:LD	A,E			; GET MODE 
+	AND	11000000B		; BITS (B7B6)
+	CP	10000000B		; IS IT BIDIR?
+	JR	NZ,SETPIO1
+	LD	A,(IY+2)		; GET CHANNEL
+	OR	A
+	JR	NZ,BAD_SET		; CAN'T DO ON CH1
+
+	; VALIDATE INTERRUPT REQUEST
+	; GRANT INTERRUPT IF THERE IS A FREE INTERRUPT
+	; GRANT INTERRUPT IF AN INTERRUPT IS ALREADY ALLOCATED TO THIS UNIT
+
+SETPIO1:PUSH	AF		;D
+	LD	A,'['		;D
+	CALL	COUT		;D
+	LD	A,(IY)		;D
+	CALL	PRTHEXBYTE	;D
+	LD	A,']'		;D
+	CALL	COUT		;D
+	POP	AF		;D
+
+	BIT	2,E			; SKIP IF WE ARE NOT REQUESTING 
+	JP	Z,SETPIO2		; AN INTERRUPT
+
+	PRTS("[INTREQ]$")	;D
+
+;	LD	A,(IY+4)		; GET CURRENT INTERRUPT SETTING
+;	BIT	2,A			; SKIP IF IT IS ALREADY
+;	JP	NZ,SETPIO2		; ALLOCATED TO THIS UNIT
+
+	LD	A,(INT_ALLOC)		; WE NEED TO ALLOCATE AN
+	CP	INT_ALLOW		; INTERRUPT. DO WE HAVE 
+	JR	NC,BAD_SET		; ONE FREE?
+
+	PRTS("[ALLOCINT]$")	;D
+
+	; WHICH INTERRUPT IS FREE ?
+	; SCAN THROUGH THE CFG TABLES
+	; AND FIND A FREE ONE
+
+	PUSH	AF			; NESTED LOOP
+	LD	DE,32			; OUTSIDE LOOP IS INTERRUPT
+	LD	B,INT_ALLOW		; INSIDE LOOP IS DEVICE
+SETPIOP: LD	C,B 
+	 DEC	C
+	 PUSH	BC
+	 LD	B,PIO_CNT
+	 LD	HL,PIO_CFG+4
+SETPIOX: LD	A,(HL)
+	 BIT	2,A			; JUMP TO NEXT DEVICE
+	 JR	Z,SETPIOY		; IF NO INTERRUPT ON 
+	 AND	00000011B		; THIS DEVICE
+
+	 CP	C			; IF WE MATCH AN INTERRUPT HERE THEN IT IS NOT FREE.
+	 JR	NZ,SETPIOY		; SO EXIT INSIDE LOOP AND TRY NEXT INTERRUPT
+
+	 XOR	A			; WE MATCH INT 0 - IF WE ARE CHECKING FOR IT THEN
+	 OR	C			; WE REGARD IS AS FREE.
+	 JR	NZ,SETPIOZ
+
+SETPIOY: ADD	HL,DE			
+	 DJNZ	SETPIOX
+
+	 JR	SETPIOQ			; WE GET HERE IF THE CURRENT INTERRUPT
+					; WAS NOT MATCHED SO IT IS FREE
+SETPIOZ: POP	BC
+	DJNZ	SETPIOP
+	POP	AF
+
+	PRTS("[NONEFREE]$")
 	RET
+
+SETPIOQ:PUSH	AF			; AVAILABLE INTERRUPT IS IN C
+	PRTS("[FREE]=$")
+	LD	A,C
+	CALL	PRTHEXBYTE
+	POP	AF
+
+	POP	AF			
+	POP	AF
+
+SETPIOR:
+	LD	HL,INT_ALLOC		; INCREASE THE COUNT
+	INC	(HL)			; OF USED INTERRUPTS
+	LD	A,(HL)
+
+;	LD	A,(IY)			; IS THIS UNIT 
+;	INC	A			; UNITIALIZED?
+;	JR	Z,SETPIO6
+
+	LD	A,(IY+4)		; IT IS UNITIALIZED SO
+	OR	C			; SAVE THE ALLOCATES 
+	LD	(IY+4),A		; INTERRUPT
+;
+;
+; FOR THIS DEVICE AND INTERRUPT, UPDATE THE CONFIG TABLE FOR THIS DEVICE.
+; PIO_IN, PIO_OUT, PIO_IST, PIO_OST ENTRIES NEED TO BE REDIRECTED.
+; INTERRUPT VECTOR NEEDS TO BE UPDATED
 ;
-SET_PIO:
-	; DEVICE TYPE IS Z80 PIO SO DETERMINE MODE TO SET
-	; BIDIR MODE CAN ONLY BE SET ON CHANNEL 0
-	; BITCTRL MODE REQUIRES A I/O DIRECTION TO BE SET
+	LD	A,(IY+0)
+	LD	HL,0
+	; SETUP SIO INTERRUPT VECTOR IN IVT
+	LD	HL,HB_IVT09+1
+
+	CALL	SPK_BEEP
+
+
+SETPIO6:RET	
+
+	; EXIT WITH FREE INTERRUPT IN C
+
+	LD	A,C
+	LD	(INT_ALLOC),A
+
+;	CALL	SPK_BEEP
+
+	LD	A,E
+	AND	11000000B
+	OR	00000100B
+	OR	C
+	LD	E,A
+	LD	(IY+5),A
+;
+	; TODO: DEALLOCATE AN INTERRUPT
+;
+;	LD	A,(INT_ALLOC)
+;	DEC	A
+;	LD	(INT_ALLOC),A
+;
+SETPIO2:
+
+;	DE CONTAINS THE MODE IF INTERRUPT ROUTINE SKIPPED
+
+	PRTS("[NOINTREQ]$")	;D
+
+;	LD	A,(IY+4)
+	LD	A,E			; GET MODE AND CREATE COMMAND
+	AND	11000000B		; $B0
+	OR	00001111B		; $0F	
+
 	LD	C,(IY+3)		; GET DATA PORT
 	INC	C			; POINT TO CMD
-	INC	C			; PORT
-	LD	A,(IY+4)		; GET MODE (B7B6)
-	AND	11010000B		; KEEP MODE & CHANNEL
-	CP	10010000B		; SET CH1 & BIDIR
-	JR	Z,PIO_BAD		; CAN'T DO ON CH1
-	AND	11000000B		; $B0
-	OR	00001111B		; $0F
+	INC	C			; PORT	
 	OUT	(C),A			; SET MODE
 	CP	(M_BitCtrl | $0F)	; IF MODE 3
-	JR	NZ,SET_NM3		
-	LD	A,(IY+5)		; SET I/O
+	JR	NZ,SETPIO3		
+	LD	A,(IY+5)		; SET I/O DIRECTION
 	OUT	(C),A			; FOR MODE 3
-SET_NM3:; INTERUPT HANDLING
-	LD	A,(IY+4)		; CHECK IF INTERRUPT
-	BIT	2,A			; REQUEST BIT SET
-	JR	Z,NOINT1
-
-	LD	A,(INT_ALLOC)		; DO WE HAVE AN
-	CP	INT_ALLOW+1		; INTERRUPT FREE?
-	JR	NC,BADSET
-	
-	INC	A			; ONE INTERRUPT
-	LD	(INT_ALLOC),A		; USED
 
-	; THE TRICKY BIT - SETUP THE RIGHT INTERRUPT VECTOR
+SETPIO3:; INTERUPT HANDLING
 
-NOINT1:	LD	A,00000111B		; $07 
-	OUT	(C),A			; NO INTERRUPTS
-	DEC	C
-	DEC	C
-	LD	A,$FF			; DEFAULT VALUE
+	JP	SETPIO4
+
+	; SETUP THE INTERRUPT VECTOR
+
+	LD	A,E
+	AND	00000011B
+;	DEC	A			; INDEX INTO THE
+	ADD	A,A			; THE VECTOR TABLE
+	ADD	A,A			; 
+	LD	C,A
+	LD	B,0
+	LD	HL,HB_IVT07+1
+	ADD	HL,BC			; GET THE ADDRESS OF
+	PUSH	DE
+	LD	D,(HL)			; THAT INTERRUPT
+	INC	HL			; HANDLER
+	LD	E,(HL)
+	LD	HL,HBX_IVT+IVT_PIO0	; POPULATE THE
+	LD	A,L			; GET LOW BYTE OF IVT ADDRESS
+	ADD	HL,BC			; INTERRUPT TABLE
+	LD	(HL),D			; WITH THE INTERRUPT
+	INC	HL			; HANDLER ADDRESS FOR
+	LD	(HL),E			; THIS UNIT
+	POP	DE
+	LD	HL,INT_ALLOC
+	LD	C,(HL)
+	LD	B,0
+	LD	HL,PRTTAB-1		; SAVE THE DATA	
+	ADD	HL,BC			; PORT FOR EACH INTERRUPT
+	LD	C,(IY+3)		
+	LD	(HL),C
+
+	INC	C			; POINT TO CMD PORT
+	INC	C
+	DI				; SET THE VECTOR ADDRESS
 	OUT	(C),A
+
+;	LD	A,10000011B		; ENABLE INTERRUPTS ON
+	OUT	(C),A			; THIS UNIT
+	EI	
+;	JR	GUD_SET
+;
+SETPIO4:LD	A,00000111B		; $07 
+	OUT	(C),A			; NO INTERRUPTS
+;
+;	SUCCESSFULL SO SAVE DEVICE CONFIGURATION WORD (DCW)
+;
+GUD_SET:LD	(IY+4),E		; LOW BYTE
+	LD	(IY+5),D		; HIGH BYTE	
+;
+;	UPDATE THE DEVICE TABLE WITH THE ADDRESSES FOR THE CORRECT ROUTINE.
+;
+	LD	HL,INTMATRIX		; POINT TO EITHER THE INTERRUPT
+	LD	HL,POLMATRIX		; MATRIX OR THE POLLED MATRIX
+	PUSH	HL	
+
+	PUSH	IY			; CALCULATE THE DESTINATION
+	POP	HL			; ADDRESS IN THE PIO_CFG TABLE
+	LD	BC,8			; FOR THE FOUR ADDESSES TO BE 
+	ADD	HL,BC			; COPIED TO 
+
+
+;	LD	B,0			; 00000000 CALCULATE THE SOURCE ADDRESS
+	LD	C,E			; XX?????? FROM THE MATRIX. EACH ENTRY 
+	SRL	C			; 0XX????? IN THE MATRIX IS 8 BYTES SO
+	SRL	C			; 00XX???? SOURCE = MATRIX BASE + (8 * MODE)
+	SRL	C			; 000XX???
+	POP	DE			; LOAD THE MATRIX BASE
+;	LD	DE,POLMATRIX
+	EX	DE,HL
+	ADD	HL,BC			; HL = SOURCE
+
+	LD	C,8			; COPY 8 BYTES
+	LDIR
+
+;	PUSH	IY
+;	POP	DE
+;	CALL	DUMP_BUFFER
+
 	XOR	A
 	RET
-BADSET:	LD	A,$FF
-	RET
 
-SET_8255:
-	RET	
+PRTTAB:	.DB	0
+	.DB	0
+	.DB	0
+	.DB	0
+;
+;-----------------------------------------------------------------------------
+;
+; INPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+#DEFINE	PIOMIVT(PIOIN,PIOIST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH ERROR IF THERE IS	\
+#DEFCONT ;	ALREADY	A CHARACTER IN BUFFER	\
+#DEFCONT ;\
+#DEFCONT ;	OTHERWISE CHANGE THE STATUS TO	\
+#DEFCONT ;	SHOW THERE IS ONE CHARACTER IN	\
+#DEFCONT ;	THE BUFFER AND READ IT IN AND	\
+#DEFCONT ;	AND STORE IT.RETURN GOOD STATUS.\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_CIST)
+#DEFCONT \	OR	A
+#DEFCONT \	JR	NZ,_OVFL
+#DEFCONT \	LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	LD	A,1
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	IN	A,(C)
+#DEFCONT \	LD	(_CICH),A
+#DEFCONT \	OR	$FF
+#DEFCONT \	RET
+#DEFCONT \_OVFL:XOR	A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT ;\
+#DEFCONT \PIOIN:CALL	PIOIST
+#DEFCONT \	JR	Z,PIOIN
+#DEFCONT \	LD	A,(_CICH)
+#DEFCONT \	LD	E,A
+#DEFCONT \	XOR	A
+#DEFCONT \	LD	(_CIST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	If THERE A CHARACTER		\
+#DEFCONT ;	AVAILABLE? RETURN NUMBER	\
+#DEFCONT ;	IN A - 0 OR 1			\
+#DEFCONT ;\
+#DEFCONT \PIOIST:LD	A,(_CIST)
+#DEFCONT \	AND	00000001B
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	CIST :	01 = CHARACTER READY ELSE NOT READY	\
+#DEFCONT ;	CISH :	CHARACTER STORED BY INTERRUPT		\
+#DEFCONT ;\
+#DEFCONT \_CIST	.DB	00
+#DEFCONT \_CICH	.DB	00
+;
+PIOIVT0:.MODULE	PIOIVT0
+PIOMIVT(PIO0IN,PI0_IST,PRTTAB+0)
+PIOIVT1:.MODULE PIOIVT1
+PIOMIVT(PIO1IN,PI1_IST,PRTTAB+1)
+PIOIVT2:.MODULE PIOIVT2
+PIOMIVT(PIO2IN,PI2_IST,PRTTAB+2)
+PIOIVT3:.MODULE PIOIVT3
+PIOMIVT(PIO3IN,PI3_IST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; OUTPUT INTERRUPT VECTOR MACRO AND DEFINITION FOR FOUR PORTS
+;
+; AN INTERRUPT IS GENERATED WHEN THE RECEIVING DEVICE CAN ACCEPT A CHARACTER
+;
+#DEFINE	PIOMOVT(PIOOUT,PIOOST,PIOPRT) 		\
+#DEFCONT ;\
+#DEFCONT ;	RETURN IF WE ARE WAITING FOR A	\
+#DEFCONT ;	CHARACTER (COST = 00)		\
+#DEFCONT ;\
+#DEFCONT ;	IF ZERO CHARACTERS READY 
+#DEFCONT ;	(COST = 01) CHANGE STATUS TO	\
+#DEFCONT ;	WAITING FOR CHARACTER (COST 00)	\
+#DEFCONT ;\
+#DEFCONT ;	IF A CHARACTER IS READY THEN	\
+#DEFCONT ;	OUTPUT AND CHANGE STATUS TO	\
+#DEFCONT ;	ZERO CHARACTERS READY		\
+#DEFCONT ;\
+#DEFCONT \	LD	A,(_COST)
+#DEFCONT \ 	DEC	A
+#DEFCONT \	RET	M
+#DEFCONT \	JR	Z,_WFC
+#DEFCONT \	LD	A,(_COCH)
+#DEFCONT \	LD	E,A
+#DEFCONT \_ONOW:LD	A,(PIOPRT)
+#DEFCONT \	LD	C,A
+#DEFCONT \	OUT	(C),E
+#DEFCONT \ 	LD	A,1
+#DEFCONT \_WFC:	LD	(_COST),A
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	WAIT FOR SPACE FOR THE CHARACTER\
+#DEFCONT ;	IF WE ARE WAITING FOR A		\
+#DEFCONT ;	CHARACTRE THEN OUTPUT IT NOW	\
+#DEFCONT ;	OTHERWISE STORE IT UNTIL THE	\
+#DEFCONT ;	INTERRUPT CALLS FOR IT		\
+#DEFCONT ;\
+#DEFCONT \PIOOUT:LD	A,(_COST)
+#DEFCONT \	CP	2
+#DEFCONT \	JR	C,_ONOW
+#DEFCONT \	LD	A,E
+#DEFCONT \	LD	(_COCH),A
+#DEFCONT \	LD	A,2
+#DEFCONT \	LD	(_COST),A
+#DEFCONT \	JR	PIOOUT
+#DEFCONT ;\
+#DEFCONT ;	RETURN WITH NUMBER OF		\
+#DEFCONT ;	CHARACTERS AVAILABLE 0 or 1	\
+#DEFCONT ;\
+#DEFCONT \PIOOST:LD	A,(_COST)
+#DEFCONT \	DEC	A
+#DEFCONT \	DEC	A
+#DEFCONT \	RET	Z
+#DEFCONT \	LD	A,1
+#DEFCONT \	RET
+#DEFCONT ;\
+#DEFCONT ;	COST :	00 WAITING FOR CHARACTER\
+#DEFCONT ;		01 ZERO CHARACTERS READY\
+#DEFCONT ;		02 ONE CHARACTER READY	\
+#DEFCONT ;	COCH :	CHARACTER TO OUTPUT	\
+#DEFCONT ;\
+#DEFCONT \_COST	.DB	01
+#DEFCONT \_COCH	.DB	00
+;
+PIOOVT0:.MODULE	PIOOVT0
+PIOMOVT(PIO0OUT,PI0_OST,PRTTAB+0)
+PIOOVT1:.MODULE PIOOVT1
+PIOMOVT(PIO1OUT,PI1_OST,PRTTAB+1)
+PIOOVT2:.MODULE PIOOVT2
+PIOMOVT(PIO2OUT,PI2_OST,PRTTAB+2)
+PIOOVT3:.MODULE PIOOVT3
+PIOMOVT(PIO3OUT,PI3_OST,PRTTAB+3)
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT OUTPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS RETURN ERROR, CHARACTER RETURNED IS UNDEFINED.
+; OUTPUT WILL ALWAYS RETURN SUCCESS
+; INPUT-STATUS WILL ALWAYS RETURN 0 CHARACTERS IN BUFFER.
+; OUTPUT-STATUS WILL ALWAYS RETURN 1 CHARACTER SPACE IN BUFFER.
 
-SET_BYE:
-	XOR	A			; SIGNAL SUCCESS
+PIOSHO_IN:
+	LD	A,1
 	RET
-;	
-PIO_ZP0:
-PIO_ZP1:
-PIO_4P0:
-PIO_4P1:
-PIO_4P2:
-PIO_4P3:
-PIO_4P4:
-PIO_4P5:
-PIO_4P6:
-PIO_4P7:OR	$FF			; NZ SET TO INDICATE INT HANDLED
+;
+PIOSHO_OUT:	
+	LD	C,(IY+3)
+	OUT	(C),E
+	XOR	A
+	RET
+;
+PIOSHO_IST:	XOR	A
+	RET
+;
+PIOSH_OST:	
+	LD	A,1
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; NON INTERRUPT INPUT ROUTINE - SHARED
+;
+; INPUT WILL ALWAYS A CHARACTER AND SUCCESS.
+; OUTPUT WILL ALWAYS RETURN FAILURE
+; INPUT STATUS WILL ALWAYS RETURN 1 CHARACTER IN BUFFER.
+;OUTPUT-STATUS WILL ALWAYS RETURN 0 CHARACTER SPACE IN BUFFER.
+;
+PIOSHI_IN:
+	LD	C,(IY+3)
+	IN	A,(C)
+	LD	E,A
+	XOR	A
 	RET
 ;
-; ON ENTRY IY POINTS TO THE DEVICE RECORD	
-; WE GET AND RETURN THE CONFIGURATION WORD IN DE
+PIOSHI_OUT:
+	LD	A,1
+	RET
+;
+PIOSH_IST:
+	LD	A,1
+	RET
+;
+PIOSHI_OST:
+	XOR	A
+	RET
+;
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. GET AND RETURN THE CONFIGURATION WORD IN DE
 ;
 PIO_QUERY:
 PPI_QUERY:
@@ -367,17 +685,37 @@ PPI_QUERY:
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
-; ON ENTRY IY POINTS TO THE DEVICE RECORD
-; FOR CHARACTER DEVICES BIT 6 OF ATTRIBUTE
-; INDICATES PARALLEL PORT IF 1 SO WE SET IT.
-; 
+;-----------------------------------------------------------------------------
+;
+; ON ENTRY IY POINTS TO THE DEVICE RECORD. FOR CHARACTER DEVICES BIT 6 OF ATTRIBUTE
+; INDICATES PARALLEL PORT IF 1 SO WE SET IT. COMMON TO ALL PORTS
+;
 PIO_DEVICE:
 PPI_DEVICE:
 	LD	D,CIODEV_PIO		; D := DEVICE TYPE
 	LD	E,(IY)			; E := PHYSICAL UNIT
 	LD	C,$40			; C := ATTRIBUTE
 	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+INTMATRIX:
+	.DW	PIO0IN,	PIO0OUT, PI0_IST, PI0_OST
+	.DW	PIO1IN,	PIO1OUT, PI1_IST, PI1_OST
+	.DW	PIO2IN,	PIO2OUT, PI2_IST, PI2_OST
+	.DW	PIO3IN,	PIO3OUT, PI3_IST, PI3_OST
+POLMATRIX:
+	.DW	PIOSHO_IN, PIOSHO_OUT, PIOSHO_IST, PIOSH_OST	; OUTPUT
+	.DW	PIOSHI_IN, PIOSHI_OUT, PIOSH_IST,  PIOSHI_OST	; INPUT
+	.DW	0,0,0,0						; BIDIR	
+	.DW	0,0,0,0						; BIT MODE
+
+SET_8255:
 	RET	
+;
+SET_BYE:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+	
 
 ; ------------------------------------
 ; i8255 FUNCTION TABLE ROUTINES
@@ -438,7 +776,14 @@ PIO_PRTCFG:
 	LD	D,(IY+5)		; ... WORD TO DE
 	CALL	PS_PRTPC0		; PRINT CONFIG
 ;
-	XOR	A
+	LD	A,(IY+4)		; PRINT
+	BIT	2,A			; ALLOCATED
+	JR	Z,NOINT			; INTERRUPT
+	PRTS("/i$")
+	LD	A,(IY+4)
+	AND	00000011B
+	CALL	PRTDECB
+NOINT:	XOR	A
 	RET
 ;
 ; WORKING VARIABLES
@@ -460,237 +805,176 @@ PIO_STR_PORT	.DB	"IO Port$"
 ;
 ; Z80 PIO PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. TWO PORTS
 ;
-#DEFINE	DEFPIO(MPIO_TYPE,MPIO_BASE,MPIO_CH0,MPIO_CH1,MPIO_CH0X,MPIO_CH1X,MPIO_FT0,MPIO_FT1,MPIO_IN0,MPIO_IN1) \
+;	32 BYTE DATA STRUCTURE FOR EACH PORT
+;
+;	.DB	0		; IY+0 CIO DEVICE NUMBER 			(SET DURING PRE-INIT, THEN FIXED)
+;	.DB	0		; IY+1 PIO TYPE 				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+2 PIO CHANNEL				(SET AT ASSEMBLY, FIXED)
+;	.DB	PIOBASE+2	; IY+3 BASE DATA PORT				(SET AT ASSEMBLY, FIXED)
+;	.DB	0		; IY+4 SPW - MODE 3 I/O DIRECTION BYTE		(SET AT ASSEMBLE, SET WITH INIT)
+;	.DB	0		; IY+5 SPW - MODE, INTERRUPT			(SET AT ASSEMBLY, SET WITH INIT)
+;	.DW	0		; IY+6/7 FUNCTION TABLE				(SET AT ASSEMBLY, SET DURING PRE-INIT AND AT INIT)
+;	.DW	PIO_IN		; IY+8  ADDR FOR DEVICE INPUT			(SET WITH INIT)
+;	.DW	PIO_OUT		; IY+10 ADDR FOR DEVICE OUTPUT			(SET WITH INIT)
+;	.DW	PIO_IST		; IY+12 ADDR FOR DEVICE INPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_OST		; IY+14 ADDR FOR DEVICE OUTPUT STATUS		(SET WITH INIT)
+;	.DW	PIO_INITDEV	; IY+16 ADDR FOR INITIALIZE DEVICE ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_QUERY	; IY+18 ADDR FOR QUERY DEVICE RECORD ROUTINE	(SET AT ASSEMBLY, FIXED)
+;	.DW	PIO_DEVICE	; IY+20 ADDR FOR DEVICE TYPE ROUTINE		(SET AT ASSEMBLY, FIXED)
+;	.FILL	10
+
+;	SETUP PARAMETER WORD:
+;
+;	+-------------------------------+ +-------+-----------+---+-------+
+;	|         BIT CONTROL           | | MODE  |           | A |  INT  |
+;	+-------------------------------+ --------------------+-----------+
+;	 F   E   D   C   B   A   9   8     7   6   5   4   3   2   1   0
+;	-- MSB (D REGISTER) --           -- LSB (E REGISTER) --
+;
+;
+; 	MSB = BIT CONTROL MAP USE IN MODE 3 
+;
+; 	MODE B7 B6 =	00 Mode 0 Output
+;			01 Mode 1 Input
+;			10 Mode 2 Bidir
+;			11 Mode 3 Bit Mode
+;
+;	INTERRUPT ALLOCATED B2	= 0 NOT ALLOCATED
+;				= 1 IS ALLOCATED
+;
+;	WHICH IVT IS ALLOCATES B1 B0	00 IVT_PIO0
+;					01 IVT_PIO1
+;					10 IVT_PIO2
+;					11 IVT_PIO3
+;	
+#DEFINE	DEFPIO(MPIOBASE,MPIOCH0,MPIOCH1,MPIOCH0X,MPIOCH1X,MPIOIN0,MPIOIN1) \
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPIO_TYPE
+#DEFCONT \ .DB	PIO_ZPIO
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPIO_BASE
-#DEFCONT \ .DB	(MPIO_CH0 | 00001000B | MPIO_IN0)
-#DEFCONT \ .DB	MPIO_CH0X
-#DEFCONT \ .DW	MPIO_FT0
+#DEFCONT \ .DB	MPIOBASE
+#DEFCONT \ .DB	(MPIOCH0|MPIOIN0)
+#DEFCONT \ .DB	MPIOCH0X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 10	
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPIO_TYPE
+#DEFCONT \ .DB	PIO_ZPIO
 #DEFCONT \ .DB	1
-#DEFCONT \ .DB	MPIO_BASE+1
-#DEFCONT \ .DB	(MPIO_CH1 | 00010000B | MPIO_IN1)
-#DEFCONT \ .DB	MPIO_CH1X
-#DEFCONT \ .DW	MPIO_FT1
+#DEFCONT \ .DB	MPIOBASE+1
+#DEFCONT \ .DB	(MPIOCH1|MPIOIN1)
+#DEFCONT \ .DB	MPIOCH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
+#DEFCONT \ .FILL 10	
 ;
 ; i8255 PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. THREE PORTS
 ;
-#DEFINE	DEFPPI(MPPI_TYPE,MPPI_BASE,MPPI_CH1,MPPI_CH2,MPPI_CH3,MPPI_CH1X,MPPI_CH2X,MPPI_CH3X) \
+#DEFINE	DEFPPI(MPPIBASE,MPPICH1,MPPICH2,MPPICH3,MPPICH1X,MPPICH2X,MPPICH3X) \
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPPI_TYPE
+#DEFCONT \ .DB	PIO_8255
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPPI_BASE+0
-#DEFCONT \ .DB	(MPPI_CH1 | 00001000B)
-#DEFCONT \ .DB	MPPI_CH1X
-#DEFCONT \ .DW	
+#DEFCONT \ .DB	MPPIBASE
+#DEFCONT \ .DB	(MPPICH1|00001000B)
+#DEFCONT \ .DB	MPPICH1X
+#DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 10
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPPI_TYPE
+#DEFCONT \ .DB	PIO_8255
 #DEFCONT \ .DB	1
-#DEFCONT \ .DB	MPPI_BASE+2
-#DEFCONT \ .DB	(MPPI_CH2 | 00010000B)
-#DEFCONT \ .DB	MPPI_CH2X
+#DEFCONT \ .DB	MPPIBASE+2
+#DEFCONT \ .DB	(MPPICH2|00010000B)
+#DEFCONT \ .DB	MPPICH2X
 #DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 10
 #DEFCONT \ .DB	0
-#DEFCONT \ .DB	MPPI_TYPE
+#DEFCONT \ .DB	PIO_8255
 #DEFCONT \ .DB	2
-#DEFCONT \ .DB	MPPI_BASE+4
-#DEFCONT \ .DB	(MPPI_CH3 | 00100000B)
-#DEFCONT \ .DB	MPPI_CH3X
+#DEFCONT \ .DB	MPPIBASE+4
+#DEFCONT \ .DB	(MPPICH3|00100000B)
+#DEFCONT \ .DB	MPPICH3X
 #DEFCONT \ .DW	0
+#DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
+#DEFCONT \ .FILL 10
 ;
 ; HERE WE ACTUALLY DEFINE THE HARDWARE THAT THE HBIOS CAN ACCESS
 ; THE INIT ROUTINES READ AND SET THE INITIAL MODES FROM THIS INFO
 ;
 PIO_CFG:
-
-#IF	PIO_ZP
-DEFPIO(PIO_ZPIO,PIOZBASE+0,M_Output,M_BitCtrl,M_BitAllOut,M_BitAllOut,PIO0FT,PIO1FT,INT_Y,INT_N)
-DEFPIO(PIO_ZPIO,PIOZBASE+4,M_Output,M_BitCtrl,M_BitAllOut,M_BitAllOut,PIO2FT,PIO3FT,INT_Y,INT_N)
-#ENDIF
+;
 #IF	PIO_4P
-DEFPIO(PIO_ZPIO,PIO4BASE+0,M_Output,M_BitCtrl,M_BitAllOut,M_BitAllOut,PIO4FT,PIO5FT,INT_N,INT_N)
-DEFPIO(PIO_ZPIO,PIO4BASE+4,M_Output,M_Input,M_BitAllOut,M_BitAllOut,PIO6FT,PIO7FT,INT_N,INT_N)
-DEFPIO(PIO_ZPIO,PIO4BASE+8,M_Output,M_Output,M_BitAllOut,M_BitAllOut,PIO8FT,PIO9FT,INT_N,INT_N)
-DEFPIO(PIO_ZPIO,PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,PIO10FT,PIO11FT,INT_N,INT_N)
+DEFPIO(PIO4BASE+0,M_Output,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+4,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+8,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,INT_N,INT_N)
+#ENDIF
+#IF	PIO_ZP
+DEFPIO(PIOZBASE+0,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
+DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
 #ENDIF
 ; PPI_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC))
 
 #IF 	PPI_SBC
-DEFPPI(PIO_8255,PPIBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut)
+DEFPPI(PPIBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut)
 #ENDIF
 ;
-;	; PIO CHANNEL A
-;	.DB	0			; CIO DEVICE NUMBER 				(SET DURING PRE-INIT, THEN FIXED)
-;	.DB	0			; PIO TYPE 					(SET AT ASSEMBLY, FIXED)
-;	.DB	0			; FREE
-;	.DB	PIOBASE+2		; BASE DATA PORT (DATA PORT)			(SET AT ASSEMBLY, FIXED)
-;	.DB	0			; SPW - MODE 3 I/O DIRECTION BYTE		(SET AT ASSEMBLE, SET WITH INIT)
-	.DB	0			; SPW - MODE, CHANNEL				(SET AT ASSEMBLY, SET WITH INIT, CHANNEL FIXED)
-;	.DW	0			; FUNCTION TABLE				(SET AT ASSEMBLY, SET DURING PRE-INIT AND AT INIT)
-
-PIO_CNT	.EQU	($ - PIO_CFG) / 8 	
+PIO_CNT	.EQU	($ - PIO_CFG) / 32 	
 ;
-
-; DRIVER FUNCTION TABLE FOR Z80 PIO's
-; EACH PIO NEEDS A FUNCTION TABLE
-; ECB-ZP : PIO0FT-PIO3FT
-; ECB-4P : PIO4FT-PIO11FT
-
-PIO_FNTBL:
+;-------------------------------------------------------------------
+; WHEN WE GET HERE IY POINTS TO THE PIO_CFG TABLE WE ARE WORKING ON.
+; C IS THE UNIT NUMBER
+;-------------------------------------------------------------------
 ;
-#IF	PIO_ZP
-PIO0FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO0FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO1FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO1FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO2FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO2FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO3FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO3FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-#ENDIF
+;PIO_INITUNIT:
+;	LD	A,C			; SET THE UNIT NUMBER
+;	LD	(IY),A	
 ;
-#IF	PIO_4P
-PIO4FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO4FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO5FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO5FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO6FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO6FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO7FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO7FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO8FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO8FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO9FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO9FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO10FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO10FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-PIO11FT	.DW	PIO_IN
-	.DW	PIO_OUT
-	.DW	PIO_IST
-	.DW	PIO_OST
-	.DW	PIO_INITDEV
-	.DW	PIO_QUERY
-	.DW	PIO_DEVICE
-#IF (($ - PIO11FT) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PIO FUNCTION TABLE ***\n"
-#ENDIF
-#ENDIF
+;	LD	DE,-1			; LEAVE CONFIG ALONE
+;	CALL	PIO_INITDEV		; IMPLEMENT IT AND RETURN
+;	XOR	A			; SIGNAL SUCCESS
+;	RET				; AND RETURN
 ;
-; DRIVER FUNCTION TABLE FOR i8255's
-;
-PPI_FNTBL:
-	.DW	PPI_IN
-	.DW	PPI_OUT
-	.DW	PPI_IST
-	.DW	PPI_OST
-	.DW	PPI_INITDEV
-	.DW	PPI_QUERY
-	.DW	PPI_DEVICE
-#IF (($ - PPI_FNTBL) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PPI FUNCTION TABLE ***\n"
-#ENDIF
+PIO_INIT:
+;	CALL	SPK_BEEP
+	LD	B,PIO_CNT		; COUNT OF POSSIBLE PIO UNITS
+	LD	C,0			; INDEX INTO PIO CONFIG TABLE
+PIO_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	
+	LD	A,C			; PHYSICAL UNIT TO A
+	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+	RLCA				; ...
+	RLCA				; ... TO GET OFFSET INTO CFG TABLE
+	RLCA
+;	RLCA
+	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+	PUSH	AF
+	CALL	ADDHLA			; HL := ENTRY ADDRESS
+	POP	AF
+	CALL	ADDHLA			; HL := ENTRY ADDRESS
+	PUSH	HL			; COPY CFG DATA PTR
+	POP	IY			; ... TO IY
+
+	LD	A,(IY+1)		; GET PIO TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,PIO_PRTCFG		; PRINT IF NOT ZERO
+	
+;	PUSH	DE	
+;	LD	DE,$FFFF		; INITIALIZE DEVICE/CHANNEL
+;	CALL	PIO_INITDEV		; BASED ON DPW
+;	POP	DE
+
+	POP	BC			; RESTORE LOOP CONTROL
+	INC	C			; NEXT UNIT
+	DJNZ	PIO_INIT1		; LOOP TILL DONE
 ;
-; DRIVER FUNCTION TABLE FOR I/O PORT
-;
-PRT_FNTBL:
-	.DW	PPI_IN
-	.DW	PPI_OUT
-	.DW	PPI_IST
-	.DW	PPI_OST
-	.DW	PPI_INITDEV
-	.DW	PPI_QUERY
-	.DW	PPI_DEVICE
-#IF (($ - PRT_FNTBL) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID PPI FUNCTION TABLE ***\n"
-#ENDIF
\ No newline at end of file
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+SET_PORT:
+	; DEVICE TYPE IS I/O PORT SO JUST WRITE $00 TO IT
+	LD	C,(IY+3)
+	OUT	(C),A
+	XOR	A
+	RET

From c210b5941ea34a34427c5c2507a4ef90e9fe2f37 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Mon, 15 Jul 2019 22:44:18 +0800
Subject: [PATCH 03/16] Update pio.asm

---
 Source/HBIOS/pio.asm | 134 +++++++++++++++++++++++++------------------
 1 file changed, 78 insertions(+), 56 deletions(-)

diff --git a/Source/HBIOS/pio.asm b/Source/HBIOS/pio.asm
index 841c04ad..c5a2314b 100644
--- a/Source/HBIOS/pio.asm
+++ b/Source/HBIOS/pio.asm
@@ -87,6 +87,7 @@ INT0		.EQU	00000000B
 INT1		.EQU	00000001B
 INT2		.EQU	00000010B
 INT3		.EQU	00000011B
+
 ;
 ; SETUP THE DISPATCH TABLE ENTRIES
 ;
@@ -107,27 +108,29 @@ PIO_PREINIT:
 	LD	(INT_ALLOC),A		; START WITH NO INTERRUPTS ALLOCATED
 PIO_PREINIT0:	
 	PUSH	BC			; SAVE LOOP CONTROL
-	LD	A,C			; INITIALIZE THE UNIT
-
-	PUSH	AF		;D
-	LD	A,'u'		;D
-	CALL	COUT		;D
-	POP	AF		;D
-	CALL	PRTHEXBYTE	;D	UNIT
-	CALL	PC_SPACE	;D
-
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
-	RLCA				; ...
-	RLCA				; ... TO GET OFFSET INTO CFG TABLE
-	RLCA
+;	LD	A,C			; INITIALIZE THE UNIT
+
+;	PUSH	AF		;D
+;	LD	A,'u'		;D
+;	CALL	COUT		;D
+;	POP	AF		;D
+;	CALL	PRTHEXBYTE	;D	UNIT
+;	CALL	PC_SPACE	;D
+
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
 ;	RLCA
-	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
-	PUSH	AF
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	POP	AF
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	PUSH	HL			; SAVE IT
-	POP	IY			; ... TO IY
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; SAVE IT
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG
 
 	LD	(HL),C
 
@@ -211,6 +214,27 @@ SKPINIT:DJNZ	PIO_PREINIT0		; LOOP UNTIL DONE
 	POP	DE		;D
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND RETURN
+;
+; X24
+;
+;
+CFG_SIZ		.EQU	24
+;
+IDXCFG:	LD	A,C
+	RLCA				; X 2
+	RLCA				; X 4
+	RLCA				; X 8
+	LD	H,0
+	LD	L,A			; HL = X 8
+	PUSH	HL
+	ADD	HL,HL			; HL = X 16
+	POP	DE
+	ADD	HL,DE			; HL = X 24
+	LD	DE,PIO_CFG
+	ADD	HL,DE
+	PUSH	HL			; COPY CFG DATA PTR
+	POP	IY			; ... TO IY
+	RET
 	
 ; PIO_INITDEV - INITIALIZE DEVICE
 ;
@@ -285,7 +309,7 @@ SETPIO1:PUSH	AF		;D
 	; AND FIND A FREE ONE
 
 	PUSH	AF			; NESTED LOOP
-	LD	DE,32			; OUTSIDE LOOP IS INTERRUPT
+	LD	DE,CFG_SIZ		; OUTSIDE LOOP IS INTERRUPT
 	LD	B,INT_ALLOW		; INSIDE LOOP IS DEVICE
 SETPIOP: LD	C,B 
 	 DEC	C
@@ -325,8 +349,7 @@ SETPIOQ:PUSH	AF			; AVAILABLE INTERRUPT IS IN C
 	POP	AF			
 	POP	AF
 
-SETPIOR:
-	LD	HL,INT_ALLOC		; INCREASE THE COUNT
+SETPIOR:LD	HL,INT_ALLOC		; INCREASE THE COUNT
 	INC	(HL)			; OF USED INTERRUPTS
 	LD	A,(HL)
 
@@ -338,19 +361,17 @@ SETPIOR:
 	OR	C			; SAVE THE ALLOCATES 
 	LD	(IY+4),A		; INTERRUPT
 ;
-;
 ; FOR THIS DEVICE AND INTERRUPT, UPDATE THE CONFIG TABLE FOR THIS DEVICE.
 ; PIO_IN, PIO_OUT, PIO_IST, PIO_OST ENTRIES NEED TO BE REDIRECTED.
 ; INTERRUPT VECTOR NEEDS TO BE UPDATED
 ;
 	LD	A,(IY+0)
 	LD	HL,0
-	; SETUP SIO INTERRUPT VECTOR IN IVT
-	LD	HL,HB_IVT09+1
+	; SETUP PIO INTERRUPT VECTOR IN IVT
+	LD	HL,HBX_IV09+1
 
 	CALL	SPK_BEEP
-
-
+;
 SETPIO6:RET	
 
 	; EXIT WITH FREE INTERRUPT IN C
@@ -358,8 +379,6 @@ SETPIO6:RET
 	LD	A,C
 	LD	(INT_ALLOC),A
 
-;	CALL	SPK_BEEP
-
 	LD	A,E
 	AND	11000000B
 	OR	00000100B
@@ -406,13 +425,13 @@ SETPIO3:; INTERUPT HANDLING
 	ADD	A,A			; 
 	LD	C,A
 	LD	B,0
-	LD	HL,HB_IVT07+1
+	LD	HL,HBX_IV09+1
 	ADD	HL,BC			; GET THE ADDRESS OF
 	PUSH	DE
 	LD	D,(HL)			; THAT INTERRUPT
 	INC	HL			; HANDLER
 	LD	E,(HL)
-	LD	HL,HBX_IVT+IVT_PIO0	; POPULATE THE
+	LD	HL,0	;HBX_IVT+IVT_PIO0	; POPULATE THE
 	LD	A,L			; GET LOW BYTE OF IVT ADDRESS
 	ADD	HL,BC			; INTERRUPT TABLE
 	LD	(HL),D			; WITH THE INTERRUPT
@@ -447,16 +466,18 @@ GUD_SET:LD	(IY+4),E		; LOW BYTE
 ;
 ;	UPDATE THE DEVICE TABLE WITH THE ADDRESSES FOR THE CORRECT ROUTINE.
 ;
+	LD	A,E
+	AND	00000111B
 	LD	HL,INTMATRIX		; POINT TO EITHER THE INTERRUPT
+	JR	NZ, USEIM
 	LD	HL,POLMATRIX		; MATRIX OR THE POLLED MATRIX
-	PUSH	HL	
+USEIM:	PUSH	HL	
 
 	PUSH	IY			; CALCULATE THE DESTINATION
 	POP	HL			; ADDRESS IN THE PIO_CFG TABLE
 	LD	BC,8			; FOR THE FOUR ADDESSES TO BE 
 	ADD	HL,BC			; COPIED TO 
 
-
 ;	LD	B,0			; 00000000 CALCULATE THE SOURCE ADDRESS
 	LD	C,E			; XX?????? FROM THE MATRIX. EACH ENTRY 
 	SRL	C			; 0XX????? IN THE MATRIX IS 8 BYTES SO
@@ -715,8 +736,7 @@ SET_8255:
 SET_BYE:
 	XOR	A			; SIGNAL SUCCESS
 	RET
-	
-
+;
 ; ------------------------------------
 ; i8255 FUNCTION TABLE ROUTINES
 ;-------------------------------------
@@ -767,7 +787,7 @@ PIO_PRTCFG:
 	CALL	WRITESTR		; PRINT IT
 ;
 	; ALL DONE IF NO PIO WAS DETECTED
-	LD	A,(IY+1)		; GET SIO TYPE BYTE
+	LD	A,(IY+1)		; GET PIO TYPE BYTE
 	OR	A			; SET FLAGS
 	RET	Z			; IF ZERO, NOT PRESENT
 ;
@@ -822,7 +842,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 ;	.DW	PIO_QUERY	; IY+18 ADDR FOR QUERY DEVICE RECORD ROUTINE	(SET AT ASSEMBLY, FIXED)
 ;	.DW	PIO_DEVICE	; IY+20 ADDR FOR DEVICE TYPE ROUTINE		(SET AT ASSEMBLY, FIXED)
 ;	.FILL	10
-
+;
 ;	SETUP PARAMETER WORD:
 ;
 ;	+-------------------------------+ +-------+-----------+---+-------+
@@ -856,7 +876,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 #DEFCONT \ .DB	MPIOCH0X
 #DEFCONT \ .DW	0
 #DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
-#DEFCONT \ .FILL 10	
+#DEFCONT \ .FILL 2	
 #DEFCONT \ .DB	0
 #DEFCONT \ .DB	PIO_ZPIO
 #DEFCONT \ .DB	1
@@ -865,7 +885,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 #DEFCONT \ .DB	MPIOCH1X
 #DEFCONT \ .DW	0
 #DEFCONT \ .DW	0,0,0,0, PIO_INITDEV,PIO_QUERY,PIO_DEVICE
-#DEFCONT \ .FILL 10	
+#DEFCONT \ .FILL 2	
 ;
 ; i8255 PORT TABLE - EACH ENTRY IS FOR 1 CHIP I.E. THREE PORTS
 ;
@@ -878,7 +898,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 #DEFCONT \ .DB	MPPICH1X
 #DEFCONT \ .DW	0
 #DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
-#DEFCONT \ .FILL 10
+#DEFCONT \ .FILL 2
 #DEFCONT \ .DB	0
 #DEFCONT \ .DB	PIO_8255
 #DEFCONT \ .DB	1
@@ -887,7 +907,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 #DEFCONT \ .DB	MPPICH2X
 #DEFCONT \ .DW	0
 #DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
-#DEFCONT \ .FILL 10
+#DEFCONT \ .FILL 2
 #DEFCONT \ .DB	0
 #DEFCONT \ .DB	PIO_8255
 #DEFCONT \ .DB	2
@@ -896,7 +916,7 @@ PIO_STR_PORT	.DB	"IO Port$"
 #DEFCONT \ .DB	MPPICH3X
 #DEFCONT \ .DW	0
 #DEFCONT \ .DW	PPI_IN,PPI_OUT,PPI_IST,PPI_OST,PPI_INITDEV,PPI_QUERY,PPI_DEVICE
-#DEFCONT \ .FILL 10
+#DEFCONT \ .FILL 2
 ;
 ; HERE WE ACTUALLY DEFINE THE HARDWARE THAT THE HBIOS CAN ACCESS
 ; THE INIT ROUTINES READ AND SET THE INITIAL MODES FROM THIS INFO
@@ -919,7 +939,7 @@ DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N)
 DEFPPI(PPIBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut)
 #ENDIF
 ;
-PIO_CNT	.EQU	($ - PIO_CFG) / 32 	
+PIO_CNT	.EQU	($ - PIO_CFG) / CFG_SIZ 	
 ;
 ;-------------------------------------------------------------------
 ; WHEN WE GET HERE IY POINTS TO THE PIO_CFG TABLE WE ARE WORKING ON.
@@ -942,19 +962,21 @@ PIO_INIT:
 PIO_INIT1:
 	PUSH	BC			; SAVE LOOP CONTROL
 	
-	LD	A,C			; PHYSICAL UNIT TO A
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
-	RLCA				; ...
-	RLCA				; ... TO GET OFFSET INTO CFG TABLE
-	RLCA
+;	LD	A,C			; PHYSICAL UNIT TO A
+;	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (32 BYTES)
+;	RLCA				; ...
+;	RLCA				; ... TO GET OFFSET INTO CFG TABLE
 ;	RLCA
-	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
-	PUSH	AF
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	POP	AF
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	PUSH	HL			; COPY CFG DATA PTR
-	POP	IY			; ... TO IY
+;;	RLCA
+;	LD	HL,PIO_CFG		; POINT TO START OF CFG TABLE
+;	PUSH	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	POP	AF
+;	CALL	ADDHLA			; HL := ENTRY ADDRESS
+;	PUSH	HL			; COPY CFG DATA PTR
+;	POP	IY			; ... TO IY
+
+	CALL	IDXCFG
 
 	LD	A,(IY+1)		; GET PIO TYPE
 	OR	A			; SET FLAGS

From 32bdecb828f8d535b93a4c0e27dc7a8d0b1784eb Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 28 Jul 2019 16:06:36 +0800
Subject: [PATCH 04/16] Add usb-fifo driver

---
 Source/HBIOS/cfg_sbc.asm |   2 +
 Source/HBIOS/plt_sbc.inc |   4 +-
 Source/HBIOS/usbfifo.asm | 178 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 183 insertions(+), 1 deletion(-)
 create mode 100644 Source/HBIOS/usbfifo.asm

diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 3fcc40d3..63f3a32f 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -101,3 +101,5 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index d64bc4fa..7ca70514 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -21,4 +21,6 @@ RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
 SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
 PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
\ No newline at end of file
+PIO4BASE	.EQU	$90		; ECB-4PIO DEFAULT PIO DEFAULT
+;
+FIFO_BASE       .EQU	$0C		; ECB USB-FIFO DEFAULT PORT
diff --git a/Source/HBIOS/usbfifo.asm b/Source/HBIOS/usbfifo.asm
new file mode 100644
index 00000000..8b935b8e
--- /dev/null
+++ b/Source/HBIOS/usbfifo.asm
@@ -0,0 +1,178 @@
+FIFO_DATA       .EQU	(FIFO_BASE+0)
+FIFO_STATUS     .EQU	(FIFO_BASE+1)
+FIFO_SEND_IMM   .EQU	(FIFO_BASE+2)
+;
+;==================================================================================================
+;
+UF_PREINIT:
+;
+; SETUP THE DISPATCH TABLE ENTRY
+;
+	LD	HL,UF_CFG		; POINT TO START OF CFG TABLE
+	PUSH	HL			; COPY CFG DATA PTR
+	PUSH	HL
+	POP	IY			; ... TO IY
+	CALL	UF_INITUNIT		; HAND OFF TO GENERIC INIT CODE
+	POP	DE			; GET ENTRY ADDRESS BACK, BUT PUT IN DE
+	LD	BC,UF_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY IF FOUND, BC:DE
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; INITIALIZATION ROUTINE
+;
+UF_INITUNIT:
+	CALL	UF_DETECT		; DETERMINE TYPE
+	OR	A			; SET FLAGS
+	RET	Z			; ABORT IF NOTHING THERE
+
+	; SET DEFAULT CONFIG
+	LD	DE,-1			; LEAVE CONFIG ALONE
+	JR	UF_INITDEV		; IMPLEMENT IT AND RETURN
+;
+;
+;
+UF_INIT:
+	LD	HL,UF_CFG		; POINT TO START OF CFG TABLE
+	PUSH	HL			; COPY CFG DATA PTR
+	POP	IY			; ... TO IY
+;
+	LD	A,1			; SET TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,UF_PRTCFG		; PRINT IF NOT ZERO
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+UF_IN:
+	CALL	UF_IST			; CHAR WAITING?
+	JR	Z,UF_IN			; LOOP IF NOT
+	LD	C,FIFO_DATA		; C := INPUT PORT
+	IN	E,(C)			; GET CHAR
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; OUTPUT THE CHARACTER IN E
+;
+UF_OUT:
+	CALL	UF_OST			; READY FOR CHAR?
+	JR	Z,UF_OUT		; LOOP IF NOT
+	LD	C,FIFO_DATA
+	OUT	(C),E
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; INPUT STATUS - CAN WE SEND A CHARACTERV
+;
+UF_IST:
+	IN	A,(FIFO_STATUS)		; IS THE QUEUE EMPTY?
+	RLCA
+	CPL
+	AND	00000001B
+	RET
+;
+; OUTPUT STATUS - CAN WE OUTPUT A CHARACTER
+;
+UF_OST:
+	IN	A,(FIFO_STATUS)		; IS THE SEND BUFFER FULL?
+	CPL
+	AND	00000001B
+	RET	
+;
+; INITIALIZATION THE SETUP PARAMETER WORD AND INITIALIZE DEVICE
+; SAVE NEW SPW IF NOT A RE-INIT. ALWAYS INITIALIZE DEVICE.
+; SPW IS NOT VAIDATED BUT IT IS USED FOR ANYTHING.
+;
+UF_INITDEV:
+;
+	; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
+	LD	A,D			; TEST DE FOR
+	AND	E			; ... VALUE OF -1
+	INC	A			; ... SO Z SET IF -1
+	JR	NZ,UF_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
+;
+	; GET CURRENT PSW BECAUSE WE ALWAYS RESAVE AT END
+	LD	E,(IY+0)		; LOW BYTE
+	LD	D,(IY+1)		; HIGH BYTE	
+;
+UF_INITDEV1:
+	XOR	A			; INTERRUPTS OFF
+	OR	00110000B
+	OUT	(FIFO_STATUS),A
+
+UF_FLUSH:
+	IN	A,(FIFO_STATUS)		; IS THERE ANY DATA
+	RLCA				; IN THE BUFFER ?
+	JR	C,UFBUFEMPTY		; EXIT IF EMPTY
+
+	IN	A,(FIFO_DATA)		; CLEAR BUFFER BY READING
+	JR	UF_FLUSH		; ALL THE DATA
+UFBUFEMPTY:
+
+	LD	(IY + 0),E		; SAVE LOW WORD
+	LD	(IY + 1),D		; SAVE HI WORD
+
+	RET				; NZ STATUS HERE INDICATES FAIL.
+;
+;	USB-FIFO WILL A SERIAL DEVICE AT DEFAULT SERIAL MODE
+;
+UF_QUERY:
+	LD	E,(IY+0)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+1)		; SECOND CONFIG BYTE TO D
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;	USB-FIFO WILL APPEAR AS A SERIAL DEVICE
+;
+UF_DEVICE:
+	LD	D,CIODEV_SIO		; D := DEVICE TYPE
+	XOR	A			; SIGNAL SUCCESS
+	LD	E,A			; E := PHYSICAL UNIT
+	LD	C,A			; C := DEVICE TYPE, 0x00 IS RS-232
+	RET
+;
+; USB-FIFO DETECTION ROUTINE
+;
+UF_DETECT:
+	LD	A,1			; 0 = NONE
+	RET
+;
+; ANNOUNCE DEVICE DESCRIPTION AND PORT
+;
+UF_PRTCFG:
+	CALL	NEWLINE
+	PRTS("USB-FIFO: IO=0x$")	; PRINT DEVICE
+
+	LD	A,FIFO_BASE
+	CALL	PRTHEXBYTE		; PRINT PORT
+;
+	XOR	A
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+UF_FNTBL:
+	.DW	UF_IN
+	.DW	UF_OUT
+	.DW	UF_IST
+	.DW	UF_OST
+	.DW	UF_INITDEV
+	.DW	UF_QUERY
+	.DW	UF_DEVICE
+#IF (($ - UF_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID SIO FUNCTION TABLE ***\n"
+#ENDIF
+;
+; DEVICE DESCRIPTION
+;
+UF_TYPE_MAP:
+		.DW	UF_STR_NONE
+		.DW	UF_STR_UF
+
+UF_STR_NONE	.DB	"<NOT PRESENT>$"
+UF_STR_UF	.DB	"USB-FIFO$"
+;
+; DEVICE DESCRIPTION TABLE
+;
+UF_CFG:	.DW	DEFSIOACFG		; LINE CONFIGURATION
+;

From 19033c018d638d05e90e9a3c84194b3795db63b8 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 28 Jul 2019 19:56:47 +0800
Subject: [PATCH 05/16] Update usbfifo.asm

Cleanup
---
 Source/HBIOS/usbfifo.asm | 80 +++++++++++++++++-----------------------
 1 file changed, 33 insertions(+), 47 deletions(-)

diff --git a/Source/HBIOS/usbfifo.asm b/Source/HBIOS/usbfifo.asm
index 8b935b8e..7e6ccb55 100644
--- a/Source/HBIOS/usbfifo.asm
+++ b/Source/HBIOS/usbfifo.asm
@@ -1,13 +1,29 @@
+;==================================================================================================
+;	ECB USB-FIFO DRIVER FOR WILL SOWERBUTTS ADAFRUIT BASED FT232H ECB-FIFO BOARD
+;	REFER https://www.retrobrewcomputers.org/doku.php?id=boards:ecb:usb-fifo:start
+;	PHIL SUMMERS (b1ackmai1er)
+;==================================================================================================
+;
+;	BASE PORT IS SET IN PLT_SBC.INC
+;	INTERRUPTS ARE NOT USED.
+;	ONLY ONE BOARD SUPPORTED.
+;
+;	HBIOS CALLS:
+;
+;	UF_PREINIT	SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE	
+;	UF_INIT		ANNOUNCE DEVICE DESCRIPTION AND PORT
+;
 FIFO_DATA       .EQU	(FIFO_BASE+0)
 FIFO_STATUS     .EQU	(FIFO_BASE+1)
 FIFO_SEND_IMM   .EQU	(FIFO_BASE+2)
 ;
-;==================================================================================================
+; DEVICE DESCRIPTION TABLE
 ;
-UF_PREINIT:
+UF_CFG:	.DW	DEFSIOACFG		; DUMMY CONFIGURATION
 ;
-; SETUP THE DISPATCH TABLE ENTRY
+; SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE
 ;
+UF_PREINIT:
 	LD	HL,UF_CFG		; POINT TO START OF CFG TABLE
 	PUSH	HL			; COPY CFG DATA PTR
 	PUSH	HL
@@ -30,19 +46,17 @@ UF_INITUNIT:
 	LD	DE,-1			; LEAVE CONFIG ALONE
 	JR	UF_INITDEV		; IMPLEMENT IT AND RETURN
 ;
-;
+; ANNOUNCE DEVICE DESCRIPTION AND PORT
 ;
 UF_INIT:
-	LD	HL,UF_CFG		; POINT TO START OF CFG TABLE
-	PUSH	HL			; COPY CFG DATA PTR
-	POP	IY			; ... TO IY
-;
-	LD	A,1			; SET TYPE
-	OR	A			; SET FLAGS
-	CALL	NZ,UF_PRTCFG		; PRINT IF NOT ZERO
+	CALL	NEWLINE			; PRINT DEVICE
+	PRTS("USB-FIFO: $")
+	PRTS("IO=0x$")
+	LD	A,FIFO_BASE
+	CALL	PRTHEXBYTE		; PRINT PORT
+	RET
 ;
-	XOR	A			; SIGNAL SUCCESS
-	RET				; DONE
+; INPUT A CHARACTER AND RETURN IT IN E
 ;
 UF_IN:
 	CALL	UF_IST			; CHAR WAITING?
@@ -62,7 +76,7 @@ UF_OUT:
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
-; INPUT STATUS - CAN WE SEND A CHARACTERV
+; INPUT STATUS - CAN WE SEND A CHARACTER
 ;
 UF_IST:
 	IN	A,(FIFO_STATUS)		; IS THE QUEUE EMPTY?
@@ -81,7 +95,7 @@ UF_OST:
 ;
 ; INITIALIZATION THE SETUP PARAMETER WORD AND INITIALIZE DEVICE
 ; SAVE NEW SPW IF NOT A RE-INIT. ALWAYS INITIALIZE DEVICE.
-; SPW IS NOT VAIDATED BUT IT IS USED FOR ANYTHING.
+; SPW IS NOT VAIDATED BUT IT IS NOT USED FOR ANYTHING.
 ;
 UF_INITDEV:
 ;
@@ -91,30 +105,27 @@ UF_INITDEV:
 	INC	A			; ... SO Z SET IF -1
 	JR	NZ,UF_INITDEV1		; IF DE == -1, REINIT CURRENT CONFIG
 ;
-	; GET CURRENT PSW BECAUSE WE ALWAYS RESAVE AT END
+	; GET CURRENT PSW. WE ALWAYS RESAVE AT END
 	LD	E,(IY+0)		; LOW BYTE
 	LD	D,(IY+1)		; HIGH BYTE	
 ;
 UF_INITDEV1:
 	XOR	A			; INTERRUPTS OFF
-	OR	00110000B
 	OUT	(FIFO_STATUS),A
-
+;
 UF_FLUSH:
 	IN	A,(FIFO_STATUS)		; IS THERE ANY DATA
 	RLCA				; IN THE BUFFER ?
 	JR	C,UFBUFEMPTY		; EXIT IF EMPTY
-
+;
 	IN	A,(FIFO_DATA)		; CLEAR BUFFER BY READING
 	JR	UF_FLUSH		; ALL THE DATA
 UFBUFEMPTY:
-
 	LD	(IY + 0),E		; SAVE LOW WORD
 	LD	(IY + 1),D		; SAVE HI WORD
-
 	RET				; NZ STATUS HERE INDICATES FAIL.
 ;
-;	USB-FIFO WILL A SERIAL DEVICE AT DEFAULT SERIAL MODE
+;	USB-FIFO WILL APPEAR AS A SERIAL DEVICE AT DEFAULT SERIAL MODE
 ;
 UF_QUERY:
 	LD	E,(IY+0)		; FIRST CONFIG BYTE TO E
@@ -137,18 +148,6 @@ UF_DETECT:
 	LD	A,1			; 0 = NONE
 	RET
 ;
-; ANNOUNCE DEVICE DESCRIPTION AND PORT
-;
-UF_PRTCFG:
-	CALL	NEWLINE
-	PRTS("USB-FIFO: IO=0x$")	; PRINT DEVICE
-
-	LD	A,FIFO_BASE
-	CALL	PRTHEXBYTE		; PRINT PORT
-;
-	XOR	A
-	RET
-;
 ; DRIVER FUNCTION TABLE
 ;
 UF_FNTBL:
@@ -163,16 +162,3 @@ UF_FNTBL:
 	.ECHO	"*** INVALID SIO FUNCTION TABLE ***\n"
 #ENDIF
 ;
-; DEVICE DESCRIPTION
-;
-UF_TYPE_MAP:
-		.DW	UF_STR_NONE
-		.DW	UF_STR_UF
-
-UF_STR_NONE	.DB	"<NOT PRESENT>$"
-UF_STR_UF	.DB	"USB-FIFO$"
-;
-; DEVICE DESCRIPTION TABLE
-;
-UF_CFG:	.DW	DEFSIOACFG		; LINE CONFIGURATION
-;

From ea4aea46d412f8599e755898532252aade72aa12 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 28 Jul 2019 20:35:03 +0800
Subject: [PATCH 06/16] usb-fifo Update config files for other builds

---
 Source/HBIOS/cfg_ezz80.asm  | 2 ++
 Source/HBIOS/cfg_mk4.asm    | 2 ++
 Source/HBIOS/cfg_n8.asm     | 3 +++
 Source/HBIOS/cfg_rcz180.asm | 2 ++
 Source/HBIOS/cfg_rcz80.asm  | 2 ++
 Source/HBIOS/cfg_zeta.asm   | 2 ++
 6 files changed, 13 insertions(+)

diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 6be302c6..bb188c94 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -89,3 +89,5 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 77e41df4..232143c3 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -110,3 +110,5 @@ Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index a885b13f..cd7ac5bd 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -98,3 +98,6 @@ Z180_IOWAIT	.EQU	3		; IO WAIT STATES TO INSERT (0-3)
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 482435ae..ec367e59 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -94,3 +94,5 @@ Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 62bc40c0..3124456a 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -89,3 +89,5 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 2ac1a983..4484ce46 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -80,3 +80,5 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
+;
+UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT

From 8c49962102472dd6c9cf1af4e033244e61c08945 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 02:32:51 +0800
Subject: [PATCH 07/16] Add capability to change which console is default

---
 Source/HBIOS/hbios.asm   | 126 +++++++++++++++++++++++++++------------
 Source/HBIOS/usbfifo.asm |  22 ++++---
 2 files changed, 101 insertions(+), 47 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index e54da998..d0011714 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1044,9 +1044,6 @@ HB_CPU1:
 	CALL	FILL			; DO IT
 ;
 	DIAG(%00111111)
-;
-; PRE-CONSOLE INITIALIZATION
-;
 #IF 0
 ;
 ; TEST DEBUG ***************************************************************************************
@@ -1058,21 +1055,28 @@ HB_CPU1:
 ;
 #ENDIF
 ;
-#IF (ASCIENABLE)
-	CALL	ASCI_PREINIT
-#ENDIF
-#IF (UARTENABLE)
-	CALL	UART_PREINIT
-#ENDIF
-#IF (SIOENABLE)
-	CALL	SIO_PREINIT
-#ENDIF
-#IF (ACIAENABLE)
-	CALL	ACIA_PREINIT
-#ENDIF
-#IF (PIO_4P | PIO_ZP)
-	CALL	PIO_PREINIT
-#ENDIF
+; PRE-CONSOLE INITIALIZATION
+;
+	LD	A,FORCECON		; CALCULATE PRE-INIT TABLE
+	RLCA				; ENTRY THAT WE WANT TO
+	LD	DE,(PC_INITTBL)		; EXECUTE FIRST
+	LD	HL,PC_INITTBL
+	PUSH	HL
+	PUSH	DE
+	PUSH	HL
+	CALL	ADDHLA
+	POP	DE			; PLACE IT AT THE TOP OF THE
+	PUSH	HL			; TABLE BY SWAPPING IT
+	LDI				; WITH THE FIRST (DUMMY)
+	LDI				; ENTRY
+	POP	HL
+	POP	DE
+	LD	(HL),D
+	INC	HL
+	LD	(HL),E
+	LD	B,PC_INITTBLLEN
+	POP	DE
+	CALL	CALLLIST		; PROCESS THE PRE-INIT CALL TABLE
 ;
 #IF 0
 ;
@@ -1428,19 +1432,7 @@ HB_PCPU:
 	CALL	NEWLINE
 	LD	B,HB_INITTBLLEN
 	LD	DE,HB_INITTBL
-INITSYS1:
-	LD	A,(DE)
-	LD	L,A
-	INC	DE
-	LD	A,(DE)
-	LD	H,A
-	INC	DE
-	PUSH	DE
-	PUSH	BC
-	CALL	JPHL
-	POP	BC
-	POP	DE
-	DJNZ	INITSYS1
+	CALL	CALLLIST
 ;
 ; RECORD HEAP CURB AT THE CURRENT VALUE OF HEAP TOP.  HEAP CURB
 ; MARKS THE POINT IN THE HEAP AFTER WHICH MEMORY IS RELEASED
@@ -1523,6 +1515,50 @@ INITSYS3:
 ;
 	RET
 ;
+;	CALL A LIST OF ROUTINES POINTED TO BY DE OF LENGTH B.
+;
+CALLLIST:
+	LD	A,(DE)
+	LD	L,A
+	INC	DE
+	LD	A,(DE)
+	LD	H,A
+	INC	DE
+	PUSH	DE
+	PUSH	BC
+	CALL	JPHL
+	POP	BC
+	POP	DE
+	DJNZ	CALLLIST
+CALLDUMMY:
+	RET
+;
+;==================================================================================================
+;   TABLE OF PRE-CONSOLE INITIALIZATION ENTRY POINTS
+;==================================================================================================
+
+PC_INITTBL:
+	.DW	CALLDUMMY	; RESERVED FOR FORCING PRIMARY CONSOLE
+#IF (ASCIENABLE)
+	.DW	ASCI_PREINIT
+#ENDIF
+#IF (UARTENABLE)
+	.DW	UART_PREINIT
+#ENDIF
+#IF (SIOENABLE)
+	.DW	SIO_PREINIT
+#ENDIF
+#IF (ACIAENABLE)
+	.DW	ACIA_PREINIT
+#ENDIF
+#IF (PIO_4P | PIO_ZP)
+	.DW	PIO_PREINIT
+#ENDIF
+#IF (UFENABLE)
+	.DW	UF_PREINIT
+#ENDIF
+PC_INITTBLLEN	.EQU	(($ - PC_INITTBL) / 2)
+
 ;==================================================================================================
 ;   TABLE OF INITIALIZATION ENTRY POINTS
 ;==================================================================================================
@@ -1600,6 +1636,9 @@ HB_INITTBL:
 #IF (PIO_4P | PIO_ZP)
 	.DW	PIO_INIT
 #ENDIF
+#IF (UFENABLE)
+	.DW	UF_INIT
+#ENDIF
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
 ;
@@ -2693,7 +2732,7 @@ SIZ_MD		.EQU	$ - ORG_MD
 		.ECHO	SIZ_MD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (FDENABLE)
 ORG_FD		.EQU	$
   #INCLUDE "fd.asm"
@@ -2702,7 +2741,7 @@ SIZ_FD		.EQU	$ - ORG_FD
 		.ECHO	SIZ_FD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (RFENABLE)
 ORG_RF	.EQU	$
   #INCLUDE "rf.asm"
@@ -2711,7 +2750,7 @@ SIZ_RF	.EQU	$ - ORG_RF
 		.ECHO	SIZ_RF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (IDEENABLE)
 ORG_IDE		.EQU	$
   #INCLUDE "ide.asm"
@@ -2720,7 +2759,7 @@ SIZ_IDE		.EQU	$ - ORG_IDE
 		.ECHO	SIZ_IDE
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (PPIDEENABLE)
 ORG_PPIDE	.EQU	$
   #INCLUDE "ppide.asm"
@@ -2729,7 +2768,7 @@ SIZ_PPIDE	.EQU	$ - ORG_PPIDE
 		.ECHO	SIZ_PPIDE
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (SDENABLE)
 ORG_SD		.EQU	$
   #INCLUDE "sd.asm"
@@ -2738,7 +2777,7 @@ SIZ_SD		.EQU	$ - ORG_SD
 		.ECHO	SIZ_SD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (HDSKENABLE)
 ORG_HDSK	.EQU	$
   #INCLUDE "hdsk.asm"
@@ -2747,7 +2786,7 @@ SIZ_HDSK	.EQU	$ - ORG_HDSK
 		.ECHO	SIZ_HDSK
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (TERMENABLE)
 ORG_TERM	.EQU	$
   #INCLUDE "term.asm"
@@ -2774,6 +2813,7 @@ SIZ_AY	.EQU	$ - ORG_AY
 		.ECHO	SIZ_AY
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (PIO_4P | PIO_ZP | PPI_SBC)
 ORG_PIO		.EQU	$
   #INCLUDE "pio.asm"
@@ -2782,7 +2822,15 @@ SIZ_PIO		.EQU	$ - ORG_PIO
 		.ECHO	SIZ_PIO
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
+#IF (UFENABLE)
+ORG_UF	.EQU	$
+  #INCLUDE "usbfifo.asm"
+SIZ_UF	.EQU	$ - ORG_UF
+		.ECHO	"USB-FIFO occupies "
+		.ECHO	SIZ_UF
+		.ECHO	" bytes.\n"
+#ENDIF
 ;
 #DEFINE USEDELAY
 #INCLUDE "util.asm"
diff --git a/Source/HBIOS/usbfifo.asm b/Source/HBIOS/usbfifo.asm
index 7e6ccb55..25bc018f 100644
--- a/Source/HBIOS/usbfifo.asm
+++ b/Source/HBIOS/usbfifo.asm
@@ -19,7 +19,7 @@ FIFO_SEND_IMM   .EQU	(FIFO_BASE+2)
 ;
 ; DEVICE DESCRIPTION TABLE
 ;
-UF_CFG:	.DW	DEFSIOACFG		; DUMMY CONFIGURATION
+UF_CFG:	.DW	SER_9600_8N1		; DUMMY CONFIGURATION
 ;
 ; SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE
 ;
@@ -33,6 +33,7 @@ UF_PREINIT:
 	LD	BC,UF_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY IF FOUND, BC:DE
 	XOR	A			; SIGNAL SUCCESS
+UF_FAIL:
 	RET				; AND RETURN
 ;
 ; INITIALIZATION ROUTINE
@@ -72,7 +73,8 @@ UF_OUT:
 	CALL	UF_OST			; READY FOR CHAR?
 	JR	Z,UF_OUT		; LOOP IF NOT
 	LD	C,FIFO_DATA
-	OUT	(C),E
+	OUT	(C),E			; WRITE TO FIFO
+	OUT	(FIFO_SEND_IMM),A	; SEND IMMEDIATE
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
@@ -95,7 +97,7 @@ UF_OST:
 ;
 ; INITIALIZATION THE SETUP PARAMETER WORD AND INITIALIZE DEVICE
 ; SAVE NEW SPW IF NOT A RE-INIT. ALWAYS INITIALIZE DEVICE.
-; SPW IS NOT VAIDATED BUT IT IS NOT USED FOR ANYTHING.
+; SPW IS NOT VALIDATED BUT IT IS NOT USED FOR ANYTHING.
 ;
 UF_INITDEV:
 ;
@@ -121,8 +123,8 @@ UF_FLUSH:
 	IN	A,(FIFO_DATA)		; CLEAR BUFFER BY READING
 	JR	UF_FLUSH		; ALL THE DATA
 UFBUFEMPTY:
-	LD	(IY + 0),E		; SAVE LOW WORD
-	LD	(IY + 1),D		; SAVE HI WORD
+	LD	(IY+0),E		; SAVE LOW WORD
+	LD	(IY+1),D		; SAVE HI WORD
 	RET				; NZ STATUS HERE INDICATES FAIL.
 ;
 ;	USB-FIFO WILL APPEAR AS A SERIAL DEVICE AT DEFAULT SERIAL MODE
@@ -138,14 +140,18 @@ UF_QUERY:
 UF_DEVICE:
 	LD	D,CIODEV_SIO		; D := DEVICE TYPE
 	XOR	A			; SIGNAL SUCCESS
-	LD	E,A			; E := PHYSICAL UNIT
+	LD	E,A			; E := PHYSICAL UNIT, ALWAYS 0
 	LD	C,A			; C := DEVICE TYPE, 0x00 IS RS-232
 	RET
 ;
 ; USB-FIFO DETECTION ROUTINE
 ;
 UF_DETECT:
-	LD	A,1			; 0 = NONE
+;	IN	A,(FIFO_STATUS)		; DON'T LOAD DRIVER IF	
+;	AND	10000001B		; CABLE DISCONNECTED
+;	SUB	10000001B		; A=0 
+;	RET	Z
+	LD	A,1			; A=1
 	RET
 ;
 ; DRIVER FUNCTION TABLE
@@ -159,6 +165,6 @@ UF_FNTBL:
 	.DW	UF_QUERY
 	.DW	UF_DEVICE
 #IF (($ - UF_FNTBL) != (CIO_FNCNT * 2))
-	.ECHO	"*** INVALID SIO FUNCTION TABLE ***\n"
+	.ECHO	"*** INVALID USB-FIFO FUNCTION TABLE ***\n"
 #ENDIF
 ;

From d89d68e816a530517756325704b953d073a5c231 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 15:29:43 +0800
Subject: [PATCH 08/16] Update usbfifo.asm

Add cable disconnect recognition
---
 Source/HBIOS/usbfifo.asm | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/Source/HBIOS/usbfifo.asm b/Source/HBIOS/usbfifo.asm
index 25bc018f..cf96aa68 100644
--- a/Source/HBIOS/usbfifo.asm
+++ b/Source/HBIOS/usbfifo.asm
@@ -13,9 +13,12 @@
 ;	UF_PREINIT	SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE	
 ;	UF_INIT		ANNOUNCE DEVICE DESCRIPTION AND PORT
 ;
-FIFO_DATA       .EQU	(FIFO_BASE+0)
-FIFO_STATUS     .EQU	(FIFO_BASE+1)
-FIFO_SEND_IMM   .EQU	(FIFO_BASE+2)
+FIFO_DATA       .EQU	(FIFO_BASE+0)	; READ/WRITE DATA
+FIFO_STATUS     .EQU	(FIFO_BASE+1)	; READ/WRITE STATUS
+FIFO_SEND_IMM   .EQU	(FIFO_BASE+2)	; WRITE PORT TO FORCE BUFFER FLUSH
+FIFO_BUFFER	.EQU	FALSE		; OPTION TO BUFFER OUTPUT FOR 17ms
+;
+UF_USB_ACTIVE	.DB	0		; USB CABLE CONNECTED STATUS FLAG
 ;
 ; DEVICE DESCRIPTION TABLE
 ;
@@ -29,7 +32,9 @@ UF_PREINIT:
 	PUSH	HL
 	POP	IY			; ... TO IY
 	CALL	UF_INITUNIT		; HAND OFF TO GENERIC INIT CODE
+	LD	(UF_USB_ACTIVE),A	; SAVE USB CONNECTION STATUS
 	POP	DE			; GET ENTRY ADDRESS BACK, BUT PUT IN DE
+;	JR	Z,UF_FAIL		; EXIT IF NO USB CONNECTION
 	LD	BC,UF_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY IF FOUND, BC:DE
 	XOR	A			; SIGNAL SUCCESS
@@ -53,8 +58,12 @@ UF_INIT:
 	CALL	NEWLINE			; PRINT DEVICE
 	PRTS("USB-FIFO: $")
 	PRTS("IO=0x$")
-	LD	A,FIFO_BASE
-	CALL	PRTHEXBYTE		; PRINT PORT
+	LD	A,FIFO_BASE		; PRINT PORT
+	CALL	PRTHEXBYTE
+	LD	A,(UF_USB_ACTIVE)	; PRINT CABLE STATUS
+	OR	A
+	RET	NZ
+	PRTS(" No Cable$")
 	RET
 ;
 ; INPUT A CHARACTER AND RETURN IT IN E
@@ -74,7 +83,9 @@ UF_OUT:
 	JR	Z,UF_OUT		; LOOP IF NOT
 	LD	C,FIFO_DATA
 	OUT	(C),E			; WRITE TO FIFO
+#IF (FIFO_BUFFER)
 	OUT	(FIFO_SEND_IMM),A	; SEND IMMEDIATE
+#ENDIF
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
@@ -147,11 +158,11 @@ UF_DEVICE:
 ; USB-FIFO DETECTION ROUTINE
 ;
 UF_DETECT:
-;	IN	A,(FIFO_STATUS)		; DON'T LOAD DRIVER IF	
-;	AND	10000001B		; CABLE DISCONNECTED
-;	SUB	10000001B		; A=0 
-;	RET	Z
-	LD	A,1			; A=1
+	IN	A,(FIFO_STATUS)
+	AND	10000001B
+	SUB	10000001B		; A=0 CABLE DISCONNECTED
+	RET	Z
+	LD	A,1			; A=1 CABLE CONNECTED
 	RET
 ;
 ; DRIVER FUNCTION TABLE

From 7c622942e79139de6fa0e799b4d79e843896b18d Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 17:41:01 +0800
Subject: [PATCH 09/16] Update std.asm

Add support for changing default console through config.
---
 Source/HBIOS/std.asm | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index a8de2f26..79030499 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -267,6 +267,13 @@ IVT_PIO1	.EQU	20
 IVT_PIO2	.EQU	22
 IVT_PIO3	.EQU	24
 ;
+; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
+; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
+; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, 
+; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
+;
+FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
+;
 #INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))

From cf9d0770578579d311b41a47e45589e3673217af Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 18:36:06 +0800
Subject: [PATCH 10/16] Resync

---
 Doc/ChangeLog.txt                    |   2 +
 Source/CBIOS/ver.inc                 |   2 +-
 Source/HBIOS/Config/MK4_std.asm      |   4 +-
 Source/HBIOS/Config/N8_std.asm       |   4 +-
 Source/HBIOS/Config/RCZ180_ext.asm   |   5 +-
 Source/HBIOS/Config/RCZ180_nat.asm   |   5 +-
 Source/HBIOS/Config/RCZ180_sc126.asm |  11 +-
 Source/HBIOS/Config/RCZ80_std.asm    |   3 +-
 Source/HBIOS/acia.asm                |  68 ++-
 Source/HBIOS/dsrtc.asm               | 288 +++++------
 Source/HBIOS/sd.asm                  | 138 +++--
 Source/HBIOS/sio.asm                 | 723 ++++++++++++++++-----------
 Source/HBIOS/spk.asm                 |   5 +-
 13 files changed, 702 insertions(+), 556 deletions(-)

diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index d19c3301..175efb5d 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -3,6 +3,8 @@ Version 2.9.2
 - PMS: Fixed DS1210-related issue resulting in "Invalid BIOS" errors
 - SCC: Support for SC126 motherboard
 - WBW: Enable Auto-CTS/DCD in SIO driver for pacing output data
+- WBW: Support missing pull-up resistors in SD driver (a common occurence)
+- WBW: Support two SIO modules w/ auto-detection
 
 Version 2.9.1
 -------------
diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc
index 739e0e98..27042a0c 100644
--- a/Source/CBIOS/ver.inc
+++ b/Source/CBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.0"
+#DEFINE BIOSVER	"2.9.2-pre.1"
diff --git a/Source/HBIOS/Config/MK4_std.asm b/Source/HBIOS/Config/MK4_std.asm
index c2265f33..627b92bc 100644
--- a/Source/HBIOS/Config/MK4_std.asm
+++ b/Source/HBIOS/Config/MK4_std.asm
@@ -6,8 +6,8 @@
 #include "cfg_mk4.asm"
 ;
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY DEVICE SUPPORT
 FDMODE		.SET	FDMODE_DIDE	; FDMODE_DIO, FDMODE_DIDE, FDMODE_DIO3
diff --git a/Source/HBIOS/Config/N8_std.asm b/Source/HBIOS/Config/N8_std.asm
index a5ac243b..72d45ec7 100644
--- a/Source/HBIOS/Config/N8_std.asm
+++ b/Source/HBIOS/Config/N8_std.asm
@@ -6,8 +6,8 @@
 #include "cfg_n8.asm"
 ;
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	1		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.SET	3		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.SET	1		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	3		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 SDMODE		.SET	SDMODE_CSIO	; FOR N8 PROTOTYPE (DATECODE 2511), USE SDMODE_N8
 ;
diff --git a/Source/HBIOS/Config/RCZ180_ext.asm b/Source/HBIOS/Config/RCZ180_ext.asm
index e14ad5e6..90af1e1d 100644
--- a/Source/HBIOS/Config/RCZ180_ext.asm
+++ b/Source/HBIOS/Config/RCZ180_ext.asm
@@ -7,15 +7,14 @@
 ;
 MEMMGR		.SET	MM_Z2		; 512K RAM/ROM MODULE MEM MGR
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ
 DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
 ;
 ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
-SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
 ;
 FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
diff --git a/Source/HBIOS/Config/RCZ180_nat.asm b/Source/HBIOS/Config/RCZ180_nat.asm
index 4897b3e6..49db810b 100644
--- a/Source/HBIOS/Config/RCZ180_nat.asm
+++ b/Source/HBIOS/Config/RCZ180_nat.asm
@@ -6,15 +6,14 @@
 #include "cfg_rcz180.asm"
 ;
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ
 DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
 ;
 ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
-SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
 ;
 FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
diff --git a/Source/HBIOS/Config/RCZ180_sc126.asm b/Source/HBIOS/Config/RCZ180_sc126.asm
index 1b44e8c7..f6fc5cc2 100644
--- a/Source/HBIOS/Config/RCZ180_sc126.asm
+++ b/Source/HBIOS/Config/RCZ180_sc126.asm
@@ -6,15 +6,16 @@
 #include "cfg_rcz180.asm"
 ;
 Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
+;
+DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
 ;
 CPUOSC		.SET	18432000	; CPU OSC FREQ
 DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
 ;
 ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
-SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
-SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2
 ACIAENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
 ;
 FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
@@ -28,5 +29,5 @@ DSRTCENABLE	.SET	TRUE		; DS-1302 CLOCK DRIVER
 ;
 SDENABLE	.SET	TRUE		; TRUE FOR SD SUPPORT
 SDMODE		.SET	SDMODE_SC126	; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
-SDTRACE		.SET	2		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+SDTRACE		.SET	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
 SDCSIOFAST	.SET	TRUE		; TABLE-DRIVEN BIT INVERTER
diff --git a/Source/HBIOS/Config/RCZ80_std.asm b/Source/HBIOS/Config/RCZ80_std.asm
index d44d0af6..7f8ff957 100644
--- a/Source/HBIOS/Config/RCZ80_std.asm
+++ b/Source/HBIOS/Config/RCZ80_std.asm
@@ -8,8 +8,7 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ
 DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 ;
-SIOENABLE	.SET	TRUE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
-SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIOENABLE	.SET	TRUE		; TRUE TO AUTO-DETECT ZILOG SIO/2
 ACIAENABLE	.SET	TRUE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
 ;
 FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index 966474df..48e54a92 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -101,7 +101,7 @@ ACIA_INITUNIT:
 	LD	HL,ACIA_DEV		; POINT TO CURRENT UART DEVICE NUM
 	LD	A,(HL)			; PUT IN ACCUM
 	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
-	LD	(IY),A			; UDPATE UNIT NUM
+	LD	(IY),A			; UPDATE UNIT NUM
 ;
 #IF (INTMODE == 1)
 	; ADD IM1 INT CALL LIST ENTRY
@@ -171,11 +171,10 @@ ACIAA_INT00:
 	LD	E,A			; SAVE BYTE READ
 	LD	A,(ACIAA_BUFCNT)	; GET CURRENT BUFFER USED COUNT
 	CP	ACIAA_BUFSZ		; COMPARE TO BUFFER SIZE
-	;RET	Z			; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	JR	Z,ACIAA_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(ACIAA_BUFCNT),A	; AND SAVE IT
-	CP	ACIAA_BUFSZ - 5		; BUFFER GETTING FULL?
+	CP	ACIAA_BUFSZ / 2		; BUFFER GETTING FULL?
 	JR	NZ,ACIAA_INT0		; IF NOT, BYPASS DEASSERTING RTS
 	LD	A,ACIA_RTSOFF		; VALUE TO DEASSERT RTS
 	OUT	(C),A			; DO IT
@@ -216,11 +215,10 @@ ACIAB_INT00:
 	LD	E,A			; SAVE BYTE READ
 	LD	A,(ACIAB_BUFCNT)	; GET CURRENT BUFFER USED COUNT
 	CP	ACIAB_BUFSZ		; COMPARE TO BUFFER SIZE
-	;RET	Z			; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	JR	Z,ACIAB_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(ACIAB_BUFCNT),A	; AND SAVE IT
-	CP	ACIAB_BUFSZ - 5		; BUFFER GETTING FULL?
+	CP	ACIAB_BUFSZ / 2		; BUFFER GETTING FULL?
 	JR	NZ,ACIAB_INT0		; IF NOT, BYPASS DEASSERTING RTS
 	LD	A,ACIA_RTSOFF		; VALUE TO DEASSERT RTS
 	OUT	(C),A			; DO IT
@@ -291,9 +289,8 @@ ACIAA_IN:
 	LD	A,(ACIAA_BUFCNT)	; GET COUNT
 	DEC	A			; DECREMENT COUNT
 	LD	(ACIAA_BUFCNT),A	; SAVE SAVE IT
-	CP	5			; BUFFER LOW THRESHOLD
+	CP	ACIAA_BUFSZ / 4		; BUFFER LOW THRESHOLD
 	JR	NZ,ACIAA_IN0		; IF NOT, BYPASS SETTING RTS
-	
 	LD	C,(IY+3)		; C := ACIA CMD PORT
 	LD	A,ACIA_RTSON		; ASSERT RTS
 	OUT	(C),A			; DO IT
@@ -318,9 +315,8 @@ ACIAB_IN:
 	LD	A,(ACIAB_BUFCNT)	; GET COUNT
 	DEC	A			; DECREMENT COUNT
 	LD	(ACIAB_BUFCNT),A	; SAVE SAVE IT
-	CP	5			; BUFFER LOW THRESHOLD
+	CP	ACIAB_BUFSZ / 4		; BUFFER LOW THRESHOLD
 	JR	NZ,ACIAB_IN0		; IF NOT, BYPASS SETTING RTS
-	
 	LD	C,(IY+3)		; C := ACIA CMD PORT
 	LD	A,ACIA_RTSON		; ASSERT RTS
 	OUT	(C),A			; DO IT
@@ -458,46 +454,40 @@ ACIA_QUERY:
 ;
 ;
 ACIA_DEVICE:
-	LD	D,CIODEV_ACIA	; D := DEVICE TYPE
-	LD	E,(IY)		; E := PHYSICAL UNIT
-	LD	C,$00		; C := DEVICE TYPE, 0x00 IS RS-232
-	XOR	A		; SIGNAL SUCCESS
+	LD	D,CIODEV_ACIA		; D := DEVICE TYPE
+	LD	E,(IY)			; E := PHYSICAL UNIT
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
 ; ACIA DETECTION ROUTINE
 ;
 ACIA_DETECT:
-	;LD	C,ACIA_BASE	; BASE PORT ADDRESS
-	LD	C,(IY+3)	; BASE PORT ADDRESS
-	CALL	ACIA_DETECT2	; CHECK IT
-	JR	Z,ACIA_DETECT1	; FOUND IT, RECORD IT
-	;LD	C,ACIA_ALTBASE	; ALT BASE PORT ADDRESS
-	;CALL	ACIA_DETECT2	; CHECK IT
-	;JR	Z,ACIA_DETECT1	; FOUND IT, RECORD IT
-	LD	A,ACIA_NONE	; NOTHING FOUND
-	RET			; DONE
-;
-ACIA_DETECT1:
-	; ACIA FOUND, RECORD IT
-	;LD	A,C		; BASE PORT ADDRESS TO A
-	;LD	(IY+3),A	; SAVE ACTIVE BASE PORT
-	LD	A,ACIA_ACIA	; RETURN CHIP TYPE
-	RET			; DONE
+	LD	C,(IY+3)		; BASE PORT ADDRESS
+	CALL	ACIA_DETECT2		; CHECK IT
+	JR	Z,ACIA_DETECT1		; FOUND IT, RECORD IT
+	LD	A,ACIA_NONE		; NOTHING FOUND
+	RET				; DONE
+;	
+ACIA_DETECT1:	
+	; ACIA FOUND, RECORD IT	
+	LD	A,ACIA_ACIA		; RETURN CHIP TYPE
+	RET				; DONE
 ;
 ACIA_DETECT2:
 	; LOOK FOR ACIA AT PORT ADDRESS IN C
-	LD	A,$03		; MASTER RESET
-	OUT	(C),A		; DO IT
-	IN	A,(C)		; GET STATUS
-	OR	A		; CHECK FOR ZERO
-	RET	NZ		; RETURN IF NOT ZERO
-	LD	A,$02		; CLEAR MASTER RESET
-	OUT	(C),A		; DO IT
+	LD	A,$03			; MASTER RESET
+	OUT	(C),A			; DO IT
+	IN	A,(C)			; GET STATUS
+	OR	A			; CHECK FOR ZERO
+	RET	NZ			; RETURN IF NOT ZERO
+	LD	A,$02			; CLEAR MASTER RESET
+	OUT	(C),A			; DO IT
 	; CHECK FOR EXPECTED BITS:
 	;   TDRE=1, DCD & CTS = 0
-	AND	%00001110	; BIT MASK FOR "STABLE" BITS
-	CP	%00000010	; EXPECTED VALUE
-	RET			; RETURN RESULT, Z = CHIP FOUND
+	AND	%00001110		; BIT MASK FOR "STABLE" BITS
+	CP	%00000010		; EXPECTED VALUE
+	RET				; RETURN RESULT, Z = CHIP FOUND
 ;
 ;
 ;
diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm
index 690b7ea1..62471b4b 100644
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -63,16 +63,37 @@
 ;
 ; CONSTANTS
 ;
+; RTC	SBC	SBC-004	MFPIC	N8	N8-CSIO	SC126	
+; -----	-------	-------	-------	-------	-------	-------	
+; D7 WR	RTC_OUT RTC_OUT --	RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
+; D6 WR	RTC_CLK RTC_CLK --	RTC_CLK RTC_CLK RTC_CLK 
+; D5 WR	/RTC_WE /RTC_WE --	/RTC_WE /RTC_WE /RTC_WE  
+; D4 WR	RTC_CE  RTC_CE  --	RTC_CE  RTC_CE  RTC_CE  
+; D3 WR	NC      SPK     /RTC_CE	NC      NC      /SPI_CS2      
+; D2 WR	NC      CLKHI   RTC_CLK	SPI_CS	SPI_CS	/SPI_CS1 
+; D1 WR	--      --	RTC_WE	SPI_CLK	NC	FS 
+; D0 WR	--	--	RTC_OUT	SPI_DI	NC	I2C_SCL    
+;                       
+; D7 RD	--	--	--	--	--	I2C_SDA	 
+; D6 RD	CFG	CFG	--	SPI_DO	CFG	--	 
+; D5 RD	--	--	--	--	--	--	
+; D4 RD	--	--	--	--	--	--	
+; D3 RD	--	--	--	--	--	--	     
+; D2 RD	--	--	--	--	--	--	
+; D1 RD	--      --      --      --      --      --      
+; D0 RD	RTC_IN  RTC_IN  RTC_IN	RTC_IN	RTC_IN  RTC_IN     
+;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
-DSRTC_BASE	.EQU	RTC		; RTC PORT ON ALL SBC SERIES Z80 PLATFORMS
+DSRTC_BASE	.EQU	RTC		; RTC PORT
 ;
-DSRTC_DATA	.EQU	%10000000	; BIT 7 CONTROLS RTC DATA (I/O) LINE
-DSRTC_CLK	.EQU	%01000000	; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
-DSRTC_RD	.EQU	%00100000	; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
-DSRTC_CE	.EQU	%00010000	; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
+DSRTC_DATA	.EQU	%10000000	; BIT 7 IS RTC DATA OUT
+DSRTC_CLK	.EQU	%01000000	; BIT 6 IS RTC CLOCK (CLK)
+DSRTC_RD	.EQU	%00100000	; BIT 5 IS DATA  DIRECTION (/WE)
+DSRTC_CE	.EQU	%00010000	; BIT 4 IS CHIP ENABLE (CE)
 ;
-DSRTC_RESET	.EQU	%00000000	; ALL LOW
+DSRTC_MASK	.EQU	%11110000	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+DSRTC_IDLE	.EQU	%00100000	; QUIESCENT STATE
 ;
 #ENDIF
 ;
@@ -80,12 +101,13 @@ DSRTC_RESET	.EQU	%00000000	; ALL LOW
 ;
 DSRTC_BASE	.EQU	$43		; RTC PORT ON MF/PIC
 ;
-DSRTC_DATA	.EQU	%00000001	; BIT 0 CONTROLS RTC DATA (I/O) LINE
-DSRTC_CLK	.EQU	%00000100	; BIT 2 CONTROLS RTC CLOCK LINE, 1 = HIGH
-DSRTC_WR	.EQU	%00000010	; BIT 1 CONTROLS DATA DIRECTION, 1 = WRITE
-DSRTC_CE	.EQU	%00001000	; BIT 3 CONTROLS RTC CE LINE, 0 = ENABLED
+DSRTC_DATA	.EQU	%00000001	; BIT 0 IS RTC DATA OUT
+DSRTC_CLK	.EQU	%00000100	; BIT 2 IS RTC CLOCK (CLK)
+DSRTC_WR	.EQU	%00000010	; BIT 1 IS DATA DIRECTION (WE)
+DSRTC_CE	.EQU	%00001000	; BIT 3 CHIP ENABLE (/CE)
 ;
-DSRTC_RESET	.EQU	%00001000	; ALL LOW, BUT CE = 1
+DSRTC_MASK	.EQU	%00001111	; MASK FOR BITS WE OWN IN RTC LATCH PORT
+DSRTC_IDLE	.EQU	%00101000	; QUIESCENT STATE
 ;
 #ENDIF
 ;
@@ -103,6 +125,13 @@ DSRTC_INIT:
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
 	PRTS("MFPIC$")
 #ENDIF
+;
+	; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
+	; TO THEIR QUIESENT STATE
+	LD	A,(RTCVAL)
+	AND	DSRTC_MASK
+	OR	DSRTC_IDLE
+	LD	(RTCVAL),A
 ;
 	; CHECK FOR CLOCK HALTED
 	CALL	DSRTC_TSTCLK
@@ -123,22 +152,22 @@ DSRTC_INIT1:
 	LD	HL,DSRTC_TIMBUF
 	CALL	PRTDT
 	
-#IF	DSRTCCHG				; FORCE_RTC_CHARGE_ENABLE
-	LD		C,$8E			; ACCESS WRITE PROT REG
+#IF	DSRTCCHG			; FORCE_RTC_CHARGE_ENABLE
+	LD	E,$8E			; ACCESS WRITE PROT REG
 	CALL	DSRTC_CMD		; 
-	LD		A,$00			; WRITE PROTECT OFF
+	LD	E,$00			; WRITE PROTECT OFF
 	CALL	DSRTC_PUT		; 	
 	CALL	DSRTC_END		; FINISH CMD
 	
-	LD		C,$90			; ACCESS CHARGE REGISTER
+	LD	E,$90			; ACCESS CHARGE REGISTER
 	CALL	DSRTC_CMD		; 
-	LD		A,$A5			; STD CHARGE VALUES
+	LD	E,$A5			; STD CHARGE VALUES
 	CALL	DSRTC_PUT		; 
 	CALL	DSRTC_END		; FINISH REG WRITE
 	
-	LD		C,$8E			; ACCESS WRITE PROT REG
+	LD	E,$8E			; ACCESS WRITE PROT REG
 	CALL	DSRTC_CMD		; 
-	LD		A,$80			; WRITE PROTECT ON
+	LD	E,$80			; WRITE PROTECT ON
 	CALL	DSRTC_PUT		; 	
 	CALL	DSRTC_END		; FINISH CMD
 #ENDIF
@@ -303,12 +332,13 @@ DSRTC_TIM2CLK:
 ; TEST CLOCK FOR CHARGE DATA
 ;
 DSRTC_TSTCHG:
-	LD		C,$91			; CHARGE RESISTOR & DIODE VALUES
+	LD	E,$91			; CHARGE RESISTOR & DIODE VALUES
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
-	AND		%11110000		; CHECK FOR
-	CP		%10100000		; ENABLED FLAG
+	LD	A,E			; VALUE TO A
+	AND	%11110000		; CHECK FOR
+	CP	%10100000		; ENABLED FLAG
 	RET	
 ;
 ; TEST CLOCK FOR VALID DATA
@@ -317,23 +347,24 @@ DSRTC_TSTCHG:
 ;   1 = HALTED
 ;
 DSRTC_TSTCLK:
-	LD	C,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
+	LD	E,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
+	LD	A,E			; VALUE TO A
 	AND	%10000000		; HIGH ORDER BIT IS CLOCK HALT
 	RET
 ;
 ; BURST READ CLOCK DATA INTO BUFFER AT HL
 ;
 DSRTC_RDCLK:
-	LD	C,$BF			; COMMAND = $BF TO BURST READ CLOCK
+	LD	E,$BF			; COMMAND = $BF TO BURST READ CLOCK
 	CALL	DSRTC_CMD		; SEND COMMAND TO RTC
 	LD	B,DSRTC_BUFSIZ		; B IS LOOP COUNTER
 DSRTC_RDCLK1:
 	PUSH	BC			; PRESERVE BC
 	CALL	DSRTC_GET		; GET NEXT BYTE
-	LD	(HL),A			; SAVE IN BUFFER
+	LD	(HL),E			; SAVE IN BUFFER
 	INC	HL			; INC BUF POINTER
 	POP	BC			; RESTORE BC
 	DJNZ	DSRTC_RDCLK1		; LOOP IF NOT DONE
@@ -342,34 +373,35 @@ DSRTC_RDCLK1:
 ; BURST WRITE CLOCK DATA FROM BUFFER AT HL
 ;
 DSRTC_WRCLK:
-	LD	C,$8E			; COMMAND = $8E TO WRITE CONTROL REGISTER
+	LD	E,$8E			; COMMAND = $8E TO WRITE CONTROL REGISTER
 	CALL	DSRTC_CMD		; SEND COMMAND
-	XOR	A			; $00 = UNPROTECT
+	LD	E,$00			; $00 = UNPROTECT
 	CALL	DSRTC_PUT		; SEND VALUE TO CONTROL REGISTER
 	CALL	DSRTC_END		; FINISH IT
 ;
-	LD	C,$BE			; COMMAND = $BE TO BURST WRITE CLOCK
+	LD	E,$BE			; COMMAND = $BE TO BURST WRITE CLOCK
 	CALL	DSRTC_CMD		; SEND COMMAND TO RTC
 	LD	B,DSRTC_BUFSIZ		; B IS LOOP COUNTER
 DSRTC_WRCLK1:
 	PUSH	BC			; PRESERVE BC
-	LD	A,(HL)			; GET NEXT BYTE TO WRITE
+	LD	E,(HL)			; GET NEXT BYTE TO WRITE
 	CALL	DSRTC_PUT		; PUT NEXT BYTE
 	INC	HL			; INC BUF POINTER
 	POP	BC			; RESTORE BC
 	DJNZ	DSRTC_WRCLK1		; LOOP IF NOT DONE
-	LD	A,$80			; ADD CONTROL REG BYTE, $80 = PROTECT ON
+	LD	E,$80			; ADD CONTROL REG BYTE, $80 = PROTECT ON
 	CALL	DSRTC_PUT		; WRITE REQUIRED 8TH BYTE
 	JP	DSRTC_END		; FINISH IT
 ;
-#IF (DSRTCMODE == DSRTCMODE_STD)
-;
-; SEND COMMAND IN C TO RTC
+; SEND COMMAND IN E TO RTC
 ;   ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
-;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT HIGH!  THIS
+;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT ASSERTED!  THIS
 ;   IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
 ;   WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
 ;
+;   N.B. REGISTER A CONTAINS WORKING VALUE OF LATCH PORT AND MUST NOT
+;   BE MODIFIED BETWEEN CALLS TO DSRTC_CMD, DSRTC_PUT, AND DSRTC_GET.
+;
 ;   0) ASSUME ALL LINES UNDEFINED AT ENTRY
 ;   1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
 ;   2) WAIT 1US
@@ -378,19 +410,22 @@ DSRTC_WRCLK1:
 ;   5) PUT COMMAND
 ;
 DSRTC_CMD:
-	XOR	A			; ALL LINES LOW TO RESET
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
+	LD	A,(RTCVAL)		; INIT A WITH QUIESCENT STATE
+	OUT	(DSRTC_BASE),A		; WRITE TO PORT
 	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	XOR	DSRTC_CE		; NOW SET CE HIGH
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
+	AND	~DSRTC_CE		; ASSERT CE (LOW)
+#ELSE
+	OR	DSRTC_CE		; ASSERT CE (HIGH)
+#ENDIF
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
 	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	LD	A,C			; LOAD COMMAND
 	CALL	DSRTC_PUT		; WRITE IT
 	RET
 ;
-; WRITE BYTE IN A TO THE RTC
-;   WRITE BYTE IN A TO THE RTC.  CE IS IMPLICITY ASSERTED AT
-;   THE START.  CE AND CLK ARE LEFT HIGH AT THE END IN CASE
+; WRITE BYTE IN E TO THE RTC
+;   WRITE BYTE IN E TO THE RTC.  CE IS IMPLICITY ASSERTED AT
+;   THE START.  CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
 ;   NEXT ACTION IS A READ.
 ;
 ;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
@@ -404,135 +439,36 @@ DSRTC_CMD:
 ;
 DSRTC_PUT:
 	LD	B,8			; LOOP FOR 8 BITS
-	LD	C,A			; SAVE THE WORKING VALUE
-DSRTC_PUT1:
-	LD	A,DSRTC_CE		; SET CLOCK LOW
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1			; DELAY 27 T-STATES
-	LD	A,C			; RECOVER WORKING VALUE
-	RRCA				; ROTATE NEXT BIT TO SEND INTO BIT 7
-	LD	C,A			; SAVE WORKING VALUE
-	AND	%10000000		; ISOLATE THE DATA BIT
-	OR	DSRTC_CE		; KEEP CE HIGH
-	OUT	(DSRTC_BASE),A		; ASSERT DATA BIT ON BUS
-	OR	DSRTC_CLK		; SET CLOCK HI
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_PUT1		; LOOP IF NOT DONE
-	RET
-;
-; READ BYTE FROM RTC, RETURN VALUE IN A
-;   READ THE NEXT BYTE FROM THE RTC INTO A.  CE IS IMPLICITLY
-;   ASSERTED AT THE START.  CE AND CLK ARE LEFT HIGH AT
-;   THE END.  CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
-;
-;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
-;   1) SET RD HI AND CLOCK LOW
-;   3) WAIT 250NS (CLOCK PUTS DATA BIT ON BUS)
-;   4) READ DATA BIT
-;   5) SET CLOCK HI
-;   6) WAIT 250NS
-;   7) LOOP FOR 8 DATA BITS
-;   8) EXIT WITH CE,CLK,RD HI
-;
-DSRTC_GET:
-	LD	C,0			; INITIALIZE WORKING VALUE TO 0
-	LD	B,8			; LOOP FOR 8 BITS
-DSRTC_GET1:
-	LD	A,DSRTC_CE | DSRTC_RD	; SET CLK LO
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	IN	A,(DSRTC_BASE)		; READ THE RTC PORT
-	AND	%00000001		; ISOLATE THE DATA BIT
-	OR	C			; COMBINE WITH WORKING VALUE
-	RRCA				; ROTATE FOR NEXT BIT
-	LD	C,A			; SAVE WORKING VALUE
-	LD	A,DSRTC_CE | DSRTC_CLK | DSRTC_RD	; CLOCK BACK TO HI
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE (13)
-	LD	A,C			; GET RESULT INTO A
-	RET
-;
-; COMPLETE A COMMAND SEQUENCE
-;   FINISHES UP A COMMAND SEQUENCE.
-;   DOES NOT DESTROY ANY REGISTERS.
-;
-;   1) SET ALL LINES LO
-;
-DSRTC_END:
-	PUSH	AF			; SAVE AF
-	XOR	A			; ALL LINES OFF TO CLEAN UP
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	POP	AF			; RESTORE AF
-	RET
-;
-#ENDIF
-;
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
-;
-;
-; SEND COMMAND IN C TO RTC
-;   ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
-;   THE COMMAND IS SENT VIA A PUT.  CE AND CLK ARE LEFT ACTIVE!  THIS
-;   IS INTENTIONAL BECAUSE WHEN THE CLOCK IS LOWERED, THE FIRST BIT
-;   WILL BE PRESENTED TO READ (IN THE CASE OF A READ CMD).
-;
-;   0) ASSUME ALL LINES UNDEFINED AT ENTRY
-;   1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA)
-;   2) WAIT 1US
-;   3) SET CE HI
-;   4) WAIT 1US
-;   5) PUT COMMAND
-;
-DSRTC_CMD:
-	;XOR	A			; ALL LINES LOW TO RESET
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	XOR	DSRTC_CE		; NOW ASSERT CE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
-	LD	A,C			; LOAD COMMAND
-	CALL	DSRTC_PUT		; WRITE IT
-	RET
-;
-; WRITE BYTE IN A TO THE RTC
-;   WRITE BYTE IN A TO THE RTC.  CE IS IMPLICITY ASSERTED AT
-;   THE START.  CE AND CLK ARE LEFT ASSERTED AT THE END IN CASE
-;   NEXT ACTION IS A READ.
-;
-;   0) ASSUME ENTRY WITH CE ASSERTED, OTHERS UNDEFINED
-;   1) CLOCK -> LOW
-;   2) WAIT 250NS
-;   3) SET DATA ACCORDING TO BIT VALUE
-;   4) CLOCK -> HIGH
-;   5) WAIT 250NS (CLOCK READS DATA BIT FROM BUS)
-;   6) LOOP FOR 8 DATA BITS
-;   7) EXIT WITH CE AND CLOCK ASSERTED
-;
-DSRTC_PUT:
-	LD	B,8			; LOOP FOR 8 BITS
-	LD	C,A			; SAVE THE WORKING VALUE
-	LD	A,DSRTC_WR | DSRTC_CLK	; MODE=WRITE, CLOCK ON, CE ACTIVE (0)
+	OR	DSRTC_WR		; SET WRITE MODE
+#ELSE
+	AND	~DSRTC_RD		; SET WRITE MODE
+#ENDIF
 DSRTC_PUT1:
-	XOR	DSRTC_CLK		; FLIP CLOCK OFF
+	AND	~DSRTC_CLK		; SET CLOCK LOW
 	OUT	(DSRTC_BASE),A		; DO IT
 	CALL	DLY1			; DELAY 27 T-STATES
+	
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
 	RRA				; PREP ACCUM TO GET DATA BIT IN CARRY
-	RR	C			; ROTATE NEXT BIT TO SEND INTO CARRY
+	RR	E			; ROTATE NEXT BIT TO SEND INTO CARRY
 	RLA				; ROTATE BITS BACK TO CORRECT POSTIIONS
+#ELSE
+	RLA				; PREP ACCUM TO GET DATA BIT IN CARRY
+	RR	E			; ROTATE NEXT BIT TO SEND INTO CARRY
+	RRA				; ROTATE BITS BACK TO CORRECT POSTIIONS
+#ENDIF	
 	OUT	(DSRTC_BASE),A		; ASSERT DATA BIT ON BUS
-	XOR	DSRTC_CLK		; FLIP CLOCK ON
-	OUT	(DSRTC_BASE),A		; DO IT, DATA BIT SENT ON RISING EDGE
+	OR	DSRTC_CLK		; SET CLOCK HI
+	OUT	(DSRTC_BASE),A		; DO IT
 	CALL	DLY1			; DELAY 27 T-STATES
 	DJNZ	DSRTC_PUT1		; LOOP IF NOT DONE
 	RET
 ;
-; READ BYTE FROM RTC, RETURN VALUE IN A
-;   READ THE NEXT BYTE FROM THE RTC INTO A.  CE IS IMPLICITLY
-;   ASSERTED AT THE START.  CE AND CLK ARE LEFT HIGH AT
-;   THE END.  CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD!
+; READ BYTE FROM RTC, RETURN VALUE IN E
+;   READ THE NEXT BYTE FROM THE RTC INTO E.  CE IS IMPLICITLY
+;   ASSERTED AT THE START.  CE AND CLK ARE LEFT ASSERTED AT
+;   THE END.  CLOCK *MUST* BE LEFT ASSERTED FROM DSRTC_CMD!
 ;
 ;   0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED
 ;   1) SET RD HI AND CLOCK LOW
@@ -544,38 +480,38 @@ DSRTC_PUT1:
 ;   8) EXIT WITH CE,CLK,RD HI
 ;
 DSRTC_GET:
-	LD	C,0			; INITIALIZE WORKING VALUE TO 0
+	LD	E,0			; INITIALIZE WORKING VALUE TO 0
 	LD	B,8			; LOOP FOR 8 BITS
-	LD	A,DSRTC_CLK		; MODE=READ, CLOCK ON, CE ACTIVE (0)
+#IF (DSRTCMODE == DSRTCMODE_MFPIC)
+	AND	~DSRTC_WR		; SET READ MODE
+#ELSE
+	OR	DSRTC_RD		; SET READ MODE
+#ENDIF
 DSRTC_GET1:
-	XOR	DSRTC_CLK		; FLIP CLOCK OFF
-	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY2			; DELAY 2 * 27 T-STATES
+	AND	~DSRTC_CLK		; SET CLK LO
+	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
+	CALL	DLY1			; DELAY 2 * 27 T-STATES
+	PUSH	AF			; SAVE PORT VALUE
 	IN	A,(DSRTC_BASE)		; READ THE RTC PORT
 	RRA				; DATA BIT TO CARRY
-	RR	C			; SHIFT INTO WORKING VALUE
-	LD	A,DSRTC_CLK		; CLOCK ON
+	RR	E			; SHIFT INTO WORKING VALUE
+	POP	AF			; RESTORE PORT VALUE
+	OR	DSRTC_CLK		; CLOCK BACK TO HI
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
 	CALL	DLY1			; DELAY 27 T-STATES
-	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE
-	LD	A,C			; GET RESULT INTO A
+	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE (13)
 	RET
 ;
 ; COMPLETE A COMMAND SEQUENCE
 ;   FINISHES UP A COMMAND SEQUENCE.
 ;   DOES NOT DESTROY ANY REGISTERS.
 ;
-;   1) BACK TO QUIESCENT STATE
+;   1) SET ALL LINES BACK TO QUIESCENT STATE
 ;
 DSRTC_END:
-	PUSH	AF			; SAVE AF
-	;XOR	A			; ALL LINES OFF TO CLEAN UP
-	LD	A,DSRTC_RESET		; QUIESCENT STATE
-	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	POP	AF			; RESTORE AF
-	RET
-;
-#ENDIF
+	LD	A,(RTCVAL)		; INIT A WITH QUIESCENT STATE
+	OUT	(DSRTC_BASE),A		; WRITE TO PORT
+	RET				; RETURN
 ;
 ; WORKING VARIABLES
 ;
diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm
index 45e7cf75..f9fe2500 100644
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -9,14 +9,14 @@
 ;    - TEST XC CARD TYPE DETECTION
 ;    - TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
 ;
-;------------------------------------------------------------------------------
-; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4
-; ------------	------- ------- ------- ------- ------- ------- ------- -------
-; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	MK4_SD:2
-; CLK		HI ->	RTC:1	RTC:1	N/A	PC:1	~MCR:2	OPR:1	N/A
-; DI (CMD)	HI ->	RTC:0	RTC:0	N/A	PC:0	~MCR:0	OPR:0	N/A
-; DO (DAT0)	HI ->	RTC:7	RTC:6	N/A	PB:7	~MSR:5	OPR:0	N/A
-;------------------------------------------------------------------------------
+;--------------------------------------------------------------------------------------
+; SD Signal	Active	JUHA	N8	CSIO	PPI	UART	DSD	MK4      SC126
+; ------------	------- ------- ------- ------- ------- ------- ------- -------	------- 
+; CS (DAT3)	LO ->	RTC:2	RTC:2	RTC:2	~PC:4	~MCR:3	OPR:2	SD:2	~RTC:2	
+; CLK		HI ->	RTC:1	RTC:1	CSIO	PC:1	~MCR:2	OPR:1	CSIO	CSIO
+; DI (CMD)	HI ->	RTC:0	RTC:0	CSIO	PC:0	~MCR:0	OPR:0	CSIO	CSIO
+; DO (DAT0)	HI ->	RTC:7	RTC:6	CSIO	PB:7	~MSR:5	OPR:0	CSIO	CSIO
+;--------------------------------------------------------------------------------------
 ;
 ; CS = CHIP SELECT (AKA DAT3 FOR NON-SPI MODE)
 ; CLK = CLOCK
@@ -79,10 +79,46 @@
 ;			  |   +----------- CARD ECC FAILED - CARD INTERNAL ECC FAILED TO CORRECT DATA
 ;			  +--------------- OUT OF RANGE - PARAMAETER OUT OF RANGE ALLOWED FOR CARD
 ;
+;------------------------------------------------------------------------------
+;
+; *** HACK FOR MISSING PULLUP RESISTORS ***
+;
+; THERE IS A RECENT TREND FOR SD ADAPTER BOARDS (SUCH AS THOSE USED TO ATTACH AN
+; SD CARD TO AN ARDUINO OR RASPBERRY PI) TO OMIT THE PULLUP RESISTORS THAT ARE SUPPOSED
+; TO BE ON ALL LINES.  DESPITE BEING A CLEAR VIOLATION OF THE SPEC, IT IS SOMETHING THAT
+; WE WILL NOW NEED TO LIVE WITH.  THE CLK, CS, AND MOSI SIGNALS ARE NOT AN ISSUE SINCE
+; WE ARE DRIVING THOSE SIGNALS AS THE HOST.  THE PROBLEM IS WITH THE MISO SIGNAL.
+; FORTUNATELY, MOST OF THE TIME, THE SD CARD WILL BE DRIVING THE SIGNAL.  HOWEVER,
+; THERE ARE TWO SCEANRIOS WE NEED TO ACCOMMODATE IN THE CODE:
+;
+;   1. MISO WILL NOT BE DRIVEN BY THE SD CARD (FLOATING) PRIOR TO RESETING THE
+;      CARD WITH CMD0.  NORMALLY, A COMMAND SEQUENCE INVOLVES WAITING FOR THE
+;      CARD TO BE "READY" BY READING BYTES FROM THE CARD AND LOOKING FOR $FF.
+;      WHEN MISO IS FLOATING THIS WILL NOT BE RELIABLE.  SINCE THE SPEC INDICATES
+;      IT IS NOT NECESSARY TO WAIT FOR READY PRIOR TO CMD0, THE CODE HAS BEEN
+;      MODIFIED TO ISSUE CMD0 WITHOUT WAITING FOR READY.
+;
+;   2. MISO MAY NOT BE DRIVEN IMMEDIATELY AFTER SENDING A COMMAND (POSSIBLY
+;      JUST CMD0, BUT NOT SURE).  NORMALLY, AFTER SENDING A COMMAND, YOU
+;      LOOK FOR "FILL" BYTES OF $FF THAT MAY OCCUR PRIOR TO THE RESULT.  WHEN MISO
+;      IS FLOATING IT IS IMPOSSIBLE TO DETERMINE IF THE BYTE RECEIVED IS A FILL
+;      BYTE OR NOT.  BASED ON WHAT I HAVE READ, THERE WILL ALWAYS BE AT LEAST
+;      ONE FILL BYTE PRIOR TO THE ACTUAL RESULT.  ADDITIONALLY, THE SD CARD WILL
+;      START DRIVING MISO SOMETIME WITHING THAT FIRST FILL BYTE.  SO, WE NOW
+;      JUST DISCARD THE FIRST BYTE RECEIVED AFTER A COMMAND IS SENT WITH THE
+;      ASSUMPTION THAT IT MUST BE A FILL BYTE AND IS NOT RELIABLE DUE TO FLOATING
+;      MISO.
+; 
+; THESE CHANGES ARE CONSISTENT WITH THE POPULAR ARDUINO SDFAT LIBRARY, SO THEY ARE
+; PROBABLY PRETTY SAFE.  HOWEVER, I HAVE BRACKETED THE CHANGES WITH THE EQUATE BELOW.
+; IF YOU WANT TO REVERT THESE HACKS, JUST SET THE EQUATE TO FALSE.
+;
+SD_NOPULLUP	.EQU	TRUE		; ASSUME NO PULLUP
+;
 #IF (SDMODE == SDMODE_JUHA)		; JUHA MINI-BOARD
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE???
+SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_INPREG	.EQU	RTC		; INPUT REGISTER IS RTC
 SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
 SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
@@ -93,7 +129,7 @@ SD_DO		.EQU	%10000000	; RTC:7 IS DATA OUT (CARD -> CPU)
 #IF (SDMODE == SDMODE_N8)		; UNMODIFIED N8-2511
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE???
+SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_INPREG	.EQU	RTC		; INPUT REGISTER IS RTC
 SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
 SD_CLK		.EQU	%00000010	; RTC:1 IS CLOCK
@@ -158,11 +194,11 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
 ;
-#IF (SDMODE == SDMODE_SC126)		; N8-2312
+#IF (SDMODE == SDMODE_SC126)		; SC126
 SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
-SD_OPRDEF	.EQU	%00001101	; QUIESCENT STATE
-SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
+SD_OPRDEF	.EQU	%00001100	; QUIESCENT STATE (DEASSERT /CS1 & /CS2)
+SD_CS		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
 SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
@@ -257,6 +293,10 @@ SD_INIT:
 	PRTS(" IO=0x$")
 	LD	A,SD_OPRREG
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_N8)
@@ -264,6 +304,10 @@ SD_INIT:
 	PRTS(" IO=0x$")
 	LD	A,SD_OPRREG
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_CSIO)
@@ -280,6 +324,10 @@ SD_INIT:
 	PRTS(" TRDR=0x$")
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_PPI)
@@ -339,6 +387,10 @@ SD_INIT:
 	PRTS(" TRDR=0x$")
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
+;
+	LD	A,(RTCVAL)		; GET RTC PORT SHADOW VALUE
+	OR	SD_OPRDEF		; SET OUR BIT DEFAULTS
+	LD	(RTCVAL),A		; SAVE IT
 #ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
@@ -704,12 +756,6 @@ SD_GEOM:
 ; (RE)INITIALIZE CARD
 ;
 SD_INITCARD:
-;
-	;; CLEAR OUT UNIT SPECIFIC DATA
-	;SD_DPTR(0)			; SET HL TO START OF UNIT DATA
-	;LD	BC,SD_UNITDATALEN
-	;XOR	A
-	;CALL	FILL
 ;
 	CALL	SD_CHKCD		; CHECK CARD DETECT
 	JP	Z,SD_NOMEDIA		; Z=NO MEDIA, HANDLE IF SO
@@ -725,7 +771,7 @@ SD_INITCARD1:
 ;
 	; PUT CARD IN IDLE STATE
 	CALL	SD_GOIDLE		; GO TO IDLE
-	RET	NZ			; ABORT IF FAILED
+	JP	NZ,SD_NOMEDIA		; CONVERT ERROR TO NO MEDIA
 ;
 SD_INITCARD2:
 	LD	(IY+SD_TYPE),SD_TYPESDSC	; ASSUME SDSC CARD TYPE
@@ -1106,9 +1152,8 @@ SD_GOIDLE1:
 	RET	NZ			; ABORT ON ERROR
 	LD	A,(SD_RC)		; GET CARD RESULT
 	DEC	A			; MAP EXPECTED $01 -> $00
-	RET	Z			; ALL IS GOOD, RETURN WITH Z=0 AND Z SET
-	LD	A,SD_STCMDERR		; SET COMMAND ERROR VALUE, NZ ALREADY SET
-	RET				; AND RETURN
+	RET	Z			; ALL IS GOOD, RETURN WITH A=0 AND Z SET
+	JP	SD_ERRCMD		; SET COMMAND ERROR VALUE
 ;
 ; INITIALIZE COMMAND BUFFER
 ; COMMAND BYTE IN ACCUM
@@ -1155,10 +1200,23 @@ SD_EXECCMD:
 	CALL	WRITESTR
 	POP	AF
 #ENDIF
-
+;
+	CALL	SD_SELECT
+;	
+#IF (SD_NOPULLUP)
+	; DO NOT WAIT FOR READY PRIOR TO CMD0!  THIS HACK IS REQUIRED BY
+	; STUPID SD CARD ADAPTERS THAT NOW OMIT THE MISO PULL-UP.  SEE
+	; COMMENTS AT TOP OF THIS FILE.
+	LD	A,(SD_CMDBUF)
+	CP	SD_CMD_GO_IDLE_STATE
+	JR	Z,SD_EXECCMD0
+#ENDIF
+;	
 	; WAIT FOR CARD TO BE READY
 	CALL	SD_WAITRDY		; WAIT FOR CARD TO BE READY FOR A COMMAND
 	JP	NZ,SD_ERRRDYTO		; HANDLE TIMEOUT ERROR
+;	
+SD_EXECCMD0:
 	; SEND THE COMMAND
 	LD	HL,SD_CMDBUF		; POINT TO COMMAND BUFFER
 	LD	E,6			; COMMANDS ARE 6 BYTES
@@ -1168,6 +1226,13 @@ SD_EXECCMD1:
 	INC	HL			; POINT TO NEXT BYTE
 	DEC	E			; DEC LOOP COUNTER
 	JR	NZ,SD_EXECCMD1		; LOOP TILL DONE W/ ALL 6 BYTES
+;
+#IF (SD_NOPULLUP)
+	; THE FIRST FILL BYTE IS DISCARDED!  THIS HACK IS REQUIRED BY
+	; STUPID SD CARD ADAPTERS THAT NOW OMIT THE MISO PULL-UP.  SEE
+	; COMMENTS AT TOP OF THIS FILE.
+	CALL	SD_GET			; GET A BYTE AND DISCARD IT
+#ENDIF
 ;
 	; GET RESULT
 	LD	E,0			; INIT TIMEOUT LOOP COUNTER
@@ -1277,10 +1342,9 @@ SD_PUTDATA3:
 	XOR	A
 	RET
 ;
-; SELECT CARD AND WAIT FOR IT TO BE READY ($FF)
+; WAIT FOR CARD TO BE READY ($FF).  MUST ALREADY BE SELECTED.
 ;
 SD_WAITRDY:
-	CALL	SD_SELECT		; SELECT CARD
 	LD	DE,$FFFF		; LOOP MAX (TIMEOUT)
 SD_WAITRDY1:
 	CALL	SD_GET
@@ -1320,27 +1384,27 @@ SD_DONE:
 ;
 SD_SETUP:
 ;
-#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_DSD))
-	LD	A,SD_OPRDEF
-	LD	(SD_OPRVAL),A
-	OUT	(SD_OPRREG),A
+#IF (SDMODE == SDMODE_PPI)
+	; PPISD IS DESIGNED TO CORESIDE ON THE SAME PARALLEL PORT
+	; AS A DSKY.  SEE DSKY.ASM FOR DETAILS.
+	LD	A,82H			; PPI PORT A=OUT, B=IN, C=OUT
+	OUT	(SD_PPIX),A
 #ENDIF
 ;
 #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
-	; CSIO SETUP
+	; CSIO SETUP FOR Z180 CSIO
 ;	LD	A,2			; 18MHz/20 <= 400kHz
 	LD	A,6			; ???
 	OUT0	(SD_CNTR),A
-	LD	A,SD_OPRDEF
+#ENDIF
+;
+#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC126))
+	LD	A,(RTCVAL)
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
 #ENDIF
 ;
-#IF (SDMODE == SDMODE_PPI)
-	; PPISD IS DESIGNED TO CORESIDE ON THE SAME PARALLEL PORT
-	; AS A DSKY.  SEE DSKY.ASM FOR DETAILS.
-	LD	A,82H			; PPI PORT A=OUT, B=IN, C=OUT
-	OUT	(SD_PPIX),A
+#IF ((SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_PPI))
 	LD	A,SD_OPRDEF
 	LD	(SD_OPRVAL),A
 	OUT	(SD_OPRREG),A
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 1dfacc13..a2fe6d13 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -15,38 +15,91 @@
 ; https://www.retrobrewcomputers.org/doku.php?id=boards:ecb:zilog-peripherals:clock-divider
 ; 
 ; SIO PORT A (COM1:) and SIO PORT B (COM2:) ARE MAPPED TO DEVICE UC1: AND UL1: IN CP/M.
-;             
+;
+SIO_BUFSZ	.EQU	32			; RECEIVE RING BUFFER SIZE
+;
 SIO_NONE	.EQU	0
 SIO_SIO		.EQU	1
-;               
-#IF (SIOMODE == SIOMODE_RC)
-SIOA_CMD	.EQU	SIOBASE + $00	
-SIOA_DAT	.EQU	SIOBASE + $01
-SIOB_CMD	.EQU	SIOBASE + $02
-SIOB_DAT	.EQU	SIOBASE + $03
+;
+SIO_RTSON	.EQU	$EA
+SIO_RTSOFF	.EQU	$E8
+;
+#IF (INTMODE == 2)
+;
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+SIO0_IVT	.EQU	HB_IVT0D
+SIO1_IVT	.EQU	HB_IVT0E
+SIO0_VEC	.EQU	IVT_SER2
+SIO1_VEC	.EQU	IVT_SER3
+#ELSE
+SIO0_IVT	.EQU	HB_IVT07
+SIO1_IVT	.EQU	HB_IVT08
+SIO0_VEC	.EQU	IVT_SER0
+SIO1_VEC	.EQU	IVT_SER1
+#ENDIF
+;
+#ENDIF
+;
+#IF (SIO0MODE == SIOMODE_RC)
+SIO0A_CMD	.EQU	SIO0BASE + $00	
+SIO0A_DAT	.EQU	SIO0BASE + $01
+SIO0B_CMD	.EQU	SIO0BASE + $02
+SIO0B_DAT	.EQU	SIO0BASE + $03
 #ENDIF	
 ;	
-#IF (SIOMODE == SIOMODE_SMB)	
-SIOA_CMD	.EQU	SIOBASE + $02
-SIOA_DAT	.EQU	SIOBASE + $00
-SIOB_CMD	.EQU	SIOBASE + $03
-SIOB_DAT	.EQU	SIOBASE + $01
+#IF (SIO0MODE == SIOMODE_SMB)
+SIO0A_CMD	.EQU	SIO0BASE + $02
+SIO0A_DAT	.EQU	SIO0BASE + $00
+SIO0B_CMD	.EQU	SIO0BASE + $03
+SIO0B_DAT	.EQU	SIO0BASE + $01
+#ENDIF
+;
+#IF (SIO0MODE == SIOMODE_ZP)		
+SIO0A_CMD	.EQU	SIO0BASE + $06
+SIO0A_DAT	.EQU	SIO0BASE + $04 
+SIO0B_CMD	.EQU	SIO0BASE + $07
+SIO0B_DAT	.EQU	SIO0BASE + $05
 #ENDIF
 ;
-#IF (SIOMODE == SIOMODE_ZP)		
-SIOA_CMD	.EQU	SIOBASE + $06
-SIOA_DAT	.EQU	SIOBASE + $04 
-SIOB_CMD	.EQU	SIOBASE + $07
-SIOB_DAT	.EQU	SIOBASE + $05
+#IF (SIO0MODE == SIOMODE_EZZ80)
+SIO0A_CMD	.EQU	SIO0BASE + $01	
+SIO0A_DAT	.EQU	SIO0BASE + $00
+SIO0B_CMD	.EQU	SIO0BASE + $03
+SIO0B_DAT	.EQU	SIO0BASE + $02
 #ENDIF
 ;
-#IF (SIOMODE == SIOMODE_EZZ80)
-SIOA_CMD	.EQU	SIOBASE + $01	
-SIOA_DAT	.EQU	SIOBASE + $00
-SIOB_CMD	.EQU	SIOBASE + $03
-SIOB_DAT	.EQU	SIOBASE + $02
+#IF (SIOCNT >= 2)
+;
+#IF (SIO1MODE == SIOMODE_RC)
+SIO1A_CMD	.EQU	SIO1BASE + $00	
+SIO1A_DAT	.EQU	SIO1BASE + $01
+SIO1B_CMD	.EQU	SIO1BASE + $02
+SIO1B_DAT	.EQU	SIO1BASE + $03
 #ENDIF	
 ;	
+#IF (SIO1MODE == SIOMODE_SMB)
+SIO1A_CMD	.EQU	SIO1BASE + $02
+SIO1A_DAT	.EQU	SIO1BASE + $00
+SIO1B_CMD	.EQU	SIO1BASE + $03
+SIO1B_DAT	.EQU	SIO1BASE + $01
+#ENDIF
+;
+#IF (SIO1MODE == SIOMODE_ZP)		
+SIO1A_CMD	.EQU	SIO1BASE + $06
+SIO1A_DAT	.EQU	SIO1BASE + $04 
+SIO1B_CMD	.EQU	SIO1BASE + $07
+SIO1B_DAT	.EQU	SIO1BASE + $05
+#ENDIF
+;
+#IF (SIO1MODE == SIOMODE_EZZ80)
+SIO1A_CMD	.EQU	SIO1BASE + $01	
+SIO1A_DAT	.EQU	SIO1BASE + $00
+SIO1B_CMD	.EQU	SIO1BASE + $03
+SIO1B_DAT	.EQU	SIO1BASE + $02
+#ENDIF
+;
+#ENDIF
+;
 ; CONDITIONALS THAT DETERMINE THE ENCODED VALUE OF THE BAUD RATE
 ;
 #INCLUDE "siobaud.inc"	
@@ -57,23 +110,15 @@ SIO_PREINIT:
 ; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
 ; DISABLED.
 ;
-	LD	B,SIO_CNT		; LOOP CONTROL
-	LD	C,0			; PHYSICAL UNIT INDEX
+	CALL	SIO_PROBE		; PROBE FOR CHIPS
+;
+	LD	B,SIO_CFGCNT		; LOOP CONTROL
 	XOR	A			; ZERO TO ACCUM
 	LD	(SIO_DEV),A		; CURRENT DEVICE NUMBER
+	LD	IY,SIO_CFG		; POINT TO START OF CFG TABLE
 SIO_PREINIT0:	
 	PUSH	BC			; SAVE LOOP CONTROL
-	LD	A,C			; PHYSICAL UNIT TO A
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
-	RLCA				; ...
-	RLCA				; ... TO GET OFFSET INTO CFG TABLE
-	LD	HL,SIO_CFG		; POINT TO START OF CFG TABLE
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	PUSH	HL			; SAVE IT
-	PUSH	HL			; COPY CFG DATA PTR
-	POP	IY			; ... TO IY
 	CALL	SIO_INITUNIT		; HAND OFF TO GENERIC INIT CODE
-	POP	DE			; GET ENTRY ADDRESS BACK, BUT PUT IN DE
 	POP	BC			; RESTORE LOOP CONTROL
 ;
 	LD	A,(IY+1)		; GET THE SIO TYPE DETECTED
@@ -81,16 +126,25 @@ SIO_PREINIT0:
 	JR	Z,SIO_PREINIT2		; SKIP IT IF NOTHING FOUND
 ;	
 	PUSH	BC			; SAVE LOOP CONTROL
+	PUSH	IY			; CFG ENTRY ADDRESS
+	POP	DE			; ... TO DE
 	LD	BC,SIO_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF SIO FOUND, BC:DE
 	POP	BC			; RESTORE LOOP CONTROL
 ;
 SIO_PREINIT2:	
-	INC	C			; NEXT PHYSICAL UNIT
+	LD	DE,SIO_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	SIO_PREINIT0		; LOOP UNTIL DONE
 ;
+#IF (INTMODE >= 1)
+	; SETUP INT VECTORS AS APPROPRIATE
+	LD	A,(SIO_DEV)		; GET NEXT DEVICE NUM
+	OR	A			; SET FLAGS
+	JR	Z,SIO_PREINIT3		; IF ZERO, NO SIO DEVICES, ABORT
+;
 #IF (INTMODE == 1)
-	; ADD IM1 INT CALL LIST ENTRY IF APPROPRIATE
+	; ADD IM1 INT CALL LIST ENTRY
 	LD	A,(SIO_DEV)		; GET NEXT DEVICE NUM
 	OR	A			; SET FLAGS
 	JR	Z,SIO_PREINIT3		; IF ZERO, NO SIO DEVICES
@@ -99,9 +153,17 @@ SIO_PREINIT2:
 #ENDIF
 ;
 #IF (INTMODE == 2)
-	; SETUP SIO INTERRUPT VECTOR IN IVT
-	LD	HL,SIO_INT
-	LD	(HB_IVT07 + 1),HL	; IVT INDEX 7
+	; SETUP IM2 VECTORS
+	LD	HL,SIO_INT0
+	LD	(SIO0_IVT + 1),HL	; IVT INDEX
+;
+#IF (SIOCNT >= 2)
+	LD	HL,SIO_INT1
+	LD	(SIO1_IVT + 1),HL	; IVT INDEX
+#ENDIF
+;
+#ENDIF
+;
 #ENDIF
 ;
 SIO_PREINIT3:
@@ -131,26 +193,16 @@ SIO_INITUNIT:
 ;
 ;
 SIO_INIT:
-	LD	B,SIO_CNT		; COUNT OF POSSIBLE SIO UNITS
-	LD	C,0			; INDEX INTO SIO CONFIG TABLE
+	LD	B,SIO_CFGCNT		; COUNT OF POSSIBLE SIO UNITS
+	LD	IY,SIO_CFG		; POINT TO START OF CFG TABLE
 SIO_INIT1:
 	PUSH	BC			; SAVE LOOP CONTROL
-	
-	LD	A,C			; PHYSICAL UNIT TO A
-	RLCA				; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES)
-	RLCA				; ...
-	RLCA				; ... TO GET OFFSET INTO CFG TABLE
-	LD	HL,SIO_CFG		; POINT TO START OF CFG TABLE
-	CALL	ADDHLA			; HL := ENTRY ADDRESS
-	PUSH	HL			; COPY CFG DATA PTR
-	POP	IY			; ... TO IY
-	
 	LD	A,(IY+1)		; GET SIO TYPE
 	OR	A			; SET FLAGS
 	CALL	NZ,SIO_PRTCFG		; PRINT IF NOT ZERO
-	
 	POP	BC			; RESTORE LOOP CONTROL
-	INC	C			; NEXT UNIT
+	LD	DE,SIO_CFGSIZ		; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	SIO_INIT1		; LOOP TILL DONE
 ;
 	XOR	A			; SIGNAL SUCCESS
@@ -160,96 +212,110 @@ SIO_INIT1:
 ;
 #IF (INTMODE > 0)
 ;
+; IM0 ENTRY POINT
+;
 SIO_INT:
-SIOA_INT:
-	; CHECK FOR RECEIVE PENDING ON CHANNEL A
-	XOR	A			; A := 0
-	OUT	(SIOA_CMD),A		; ADDRESS RD0
-	IN	A,(SIOA_CMD)		; GET RD0
-	AND	$01			; ISOLATE RECEIVE READY BIT
-	JR	Z,SIOB_INT		; CHECK CHANNEL B
-;
-SIOA_INT00:
-	; HANDLE CHANNEL A
-	IN	A,(SIOA_DAT)		; READ PORT
-	LD	E,A			; SAVE BYTE READ
-	LD	A,(SIOA_CNT)		; GET CURRENT BUFFER USED COUNT
-	CP	SIOA_BUFSZ		; COMPARE TO BUFFER SIZE
-	;RET	Z			; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
-	JR	Z,SIOA_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
-	INC	A			; INCREMENT THE COUNT
-	LD	(SIOA_CNT),A		; AND SAVE IT
-	CP	SIOA_BUFSZ / 2		; BUFFER GETTING FULL?
-	JR	NZ,SIOA_INT0		; IF NOT, BYPASS CLEARING RTS
-	LD	A,5			; RTS IS IN WR5
-	OUT	(SIOA_CMD),A		; ADDRESS WR5
-	LD	A,$E8			; VALUE TO CLEAR RTS
-	OUT	(SIOA_CMD),A		; DO IT
-SIOA_INT0:
-	LD	HL,(SIOA_HD)		; GET HEAD POINTER
-	LD	A,L			; GET LOW BYTE
-	CP	SIOA_BUFEND & $FF	; PAST END?
-	JR	NZ,SIOA_INT1		; IF NOT, BYPASS POINTER RESET
-	LD	HL,SIOA_BUF		; ... OTHERWISE, RESET TO START OF BUFFER
-SIOA_INT1:
-	LD	A,E			; RECOVER BYTE READ
-	LD	(HL),A			; SAVE RECEIVED BYTE TO HEAD POSITION
-	INC	HL			; INCREMENT HEAD POINTER
-	LD	(SIOA_HD),HL		; SAVE IT
-;
-SIOA_INT2:
-	; CHECK FOR MORE PENDING...
-	XOR	A			; A := 0
-	OUT	(SIOA_CMD),A		; ADDRESS RD0
-	IN	A,(SIOA_CMD)		; GET RD0
-	RRA				; READY BIT TO CF
-	JR	C,SIOA_INT00		; IF SET, DO SOME MORE
-	OR	$FF			; NZ SET TO INDICATE INT HANDLED
-	RET				; AND RETURN
+	; CHECK/HANDLE FIRST CARD (SIO0) IF IT EXISTS
+	LD	A,(SIO0A_CFG + 1)	; GET SIO TYPE FOR FIRST CHANNEL OF FIRST SIO
+	OR	A			; SET FLAGS
+	CALL	NZ,SIO_INT0		; CALL IF CARD EXISTS
+	RET	NZ			; DONE IF INT HANDLED
+;
+#IF (SIOCNT >= 2)
+	; CHECK/HANDLE SECOND CARD (SIO1) IF IT EXISTS
+	LD	A,(SIO1A_CFG + 1)	; GET SIO TYPE FOR FIRST CHANNEL OF SECOND SIO
+	OR	A			; SET FLAGS
+	CALL	NZ,SIO_INT1		; CALL IF CARD EXISTS
+#ENDIF
 ;
-SIOB_INT:
-	; CHECK FOR RECEIVE PENDING ON CHANNEL B
+	RET				; DONE
+;
+; IM1 ENTRY POINTS
+;
+SIO_INT0:
+	; INTERRUPT HANDLER FOR FIRST SIO (SIO0)
+	LD	IY,SIO0A_CFG		; POINT TO SIO0A CFG
+	CALL	SIO_INTRCV		; TRY TO RECEIVE FROM IT
+	RET	NZ			; DONE IF INT HANDLED
+	LD	IY,SIO0B_CFG		; POINT TO SIO0B CFG
+	JR	SIO_INTRCV		; TRY TO RECEIVE FROM IT AND RETURN
+;
+#IF (SIOCNT >= 2)
+;
+SIO_INT1:
+	; INTERRUPT HANDLER FOR SECOND SIO (SIO1)
+	LD	IY,SIO1A_CFG		; POINT TO SIO1A CFG
+	CALL	SIO_INTRCV              ; TRY TO RECEIVE FROM IT
+	RET	NZ                      ; DONE IF INT HANDLED
+	LD	IY,SIO1B_CFG            ; POINT TO SIO1B CFG
+	JR	SIO_INTRCV              ; TRY TO RECEIVE FROM IT AND RETURN
+;
+#ENDIF
+;
+; HANDLE INT FOR A SPECIFIC CHANNEL
+; BASED ON UNIT CFG POINTED TO BY IY
+;
+SIO_INTRCV:
+	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
+	LD	C,(IY+3)		; CMD/STAT PORT TO C
 	XOR	A			; A := 0
-	OUT	(SIOB_CMD),A		; ADDRESS RD0
-	IN	A,(SIOB_CMD)		; GET RD0
+	OUT	(C),A			; ADDRESS RD0
+	IN	A,(C)			; GET RD0
 	AND	$01			; ISOLATE RECEIVE READY BIT
-	RET	Z			; IF NOT, RETURN WITH Z SET
-;
-SIOB_INT00:
-	; HANDLE CHANNEL B
-	IN	A,(SIOB_DAT)		; READ PORT
-	LD	E,A			; SAVE BYTE READ
-	LD	A,(SIOB_CNT)		; GET CURRENT BUFFER USED COUNT
-	CP	SIOB_BUFSZ		; COMPARE TO BUFFER SIZE
-	;RET	Z			; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
-	JR	Z,SIOB_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
+	RET	Z			; NOTHING AVAILABLE ON CURRENT CHANNEL
+;
+SIO_INTRCV1:
+	; RECEIVE CHARACTER INTO BUFFER
+	LD	C,(IY+4)		; DATA PORT TO C
+	IN	A,(C)			; READ PORT
+	LD	B,A			; SAVE BYTE READ
+	LD	L,(IY+7)		; SET HL TO
+	LD	H,(IY+8)		; ... START OF BUFFER STRUCT
+	LD	A,(HL)			; GET COUNT
+	CP	SIO_BUFSZ		; COMPARE TO BUFFER SIZE
+	JR	Z,SIO_INTRCV4		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
-	LD	(SIOB_CNT),A		; AND SAVE IT
-	CP	SIOB_BUFSZ / 2		; BUFFER GETTING FULL?
-	JR	NZ,SIOB_INT0		; IF NOT, BYPASS CLEARING RTS
+	LD	(HL),A			; AND SAVE IT
+	CP	SIO_BUFSZ / 2		; BUFFER GETTING FULL?
+	JR	NZ,SIO_INTRCV2		; IF NOT, BYPASS CLEARING RTS
+	LD	C,(IY+3)		; CMD/STAT PORT TO C
 	LD	A,5			; RTS IS IN WR5
-	OUT	(SIOB_CMD),A		; ADDRESS WR5
-	LD	A,$E8			; VALUE TO CLEAR RTS
-	OUT	(SIOB_CMD),A		; DO IT
-SIOB_INT0:
-	LD	HL,(SIOB_HD)		; GET HEAD POINTER
-	LD	A,L			; GET LOW BYTE
-	CP	SIOB_BUFEND & $FF	; PAST END?
-	JR	NZ,SIOB_INT1		; IF NOT, BYPASS POINTER RESET
-	LD	HL,SIOB_BUF		; ... OTHERWISE, RESET TO START OF BUFFER
-SIOB_INT1:
-	LD	A,E			; RECOVER BYTE READ
-	LD	(HL),A			; SAVE RECEIVED BYTE TO HEAD POSITION
-	INC	HL			; INCREMENT HEAD POINTER
-	LD	(SIOB_HD),HL		; SAVE IT
-;
-SIOB_INT2:
+	OUT	(C),A			; ADDRESS WR5
+	LD	A,SIO_RTSOFF		; VALUE TO CLEAR RTS
+	OUT	(C),A			; DO IT
+SIO_INTRCV2:
+	INC	HL			; HL NOW HAS ADR OF HEAD PTR
+	PUSH	HL			; SAVE ADR OF HEAD PTR
+	LD	A,(HL)			; DEREFERENCE HL
+	INC	HL
+	LD	H,(HL)
+	LD	L,A			; HL IS NOW ACTUAL HEAD PTR
+	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
+	INC	HL			; BUMP HEAD POINTER
+	POP	DE			; RECOVER ADR OF HEAD PTR
+	LD	A,L			; GET LOW BYTE OF HEAD PTR
+	ADD	A,-SIO_BUFSZ-4		; SUBTRACT SIZE OF BUFFER AND POINTER
+	CP	E			; IF EQUAL TO START, HEAD PTR IS PAST BUF END
+	JR	NZ,SIO_INTRCV3		; IF NOT, BYPASS
+	LD	H,D			; SET HL TO
+	LD	L,E			; ... HEAD PTR ADR
+	INC	HL			; BUMP PAST HEAD PTR
+	INC	HL
+	INC	HL
+	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+SIO_INTRCV3:
+	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
+	LD	(HL),E			; SAVE UPDATED HEAD PTR
+	INC	HL
+	LD	(HL),D
 	; CHECK FOR MORE PENDING...
+	LD	C,(IY+3)		; CMD/STAT PORT TO C
 	XOR	A			; A := 0
-	OUT	(SIOB_CMD),A		; ADDRESS RD0
-	IN	A,(SIOB_CMD)		; GET RD0
+	OUT	(C),A			; ADDRESS RD0
+	IN	A,(C)			; GET RD0
 	RRA				; READY BIT TO CF
-	JR	C,SIOB_INT00		; IF SET, DO SOME MORE
+	JR	C,SIO_INTRCV1		; IF SET, DO SOME MORE
+SIO_INTRCV4:
 	OR	$FF			; NZ SET TO INDICATE INT HANDLED
 	RET				; AND RETURN
 ;
@@ -276,17 +342,7 @@ SIO_FNTBL:
 SIO_IN:
 	CALL	SIO_IST			; CHAR WAITING?
 	JR	Z,SIO_IN		; LOOP IF NOT
-	LD	C,(IY+3)		; C := SIO CMD PORT
-#IF (SIOMODE == SIOMODE_RC)
-	INC	C			; BUMP TO DATA PORT
-#ENDIF
-#IF ((SIOMODE == SIOMODE_SMB) | (SIOMODE == SIOMODE_ZP))
-	DEC	C			; DECREMENT CMD PORT TWICE TO GET DATA PORT
-	DEC	C
-#ENDIF
-#IF (SIOMODE == SIOMODE_EZZ80)
-	DEC	C			; DECREMENT CMD PORT TO GET DATA PORT
-#ENDIF
+	LD	C,(IY+4)		; DATA PORT
 	IN	E,(C)			; GET CHAR
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -294,68 +350,50 @@ SIO_IN:
 #ELSE
 ;
 SIO_IN:
-	LD	A,(IY+2)		; GET CHANNEL
-	OR	A			; SET FLAGS
-	JR	Z,SIOA_IN		; HANDLE CHANNEL A
-	DEC	A			; TEST FOR NEXT DEVICE
-	JR	Z,SIOB_IN		; HANDLE CHANNEL B
-	CALL 	PANIC			; ELSE FATAL ERROR
-	RET				; ... AND RETURN
-;
-SIOA_IN:
-	CALL	SIOA_IST		; RECEIVED CHAR READY?
-	JR	Z,SIOA_IN		; LOOP TILL WE HAVE SOMETHING IN BUFFER
-	HB_DI				; AVOID COLLISION WITH INT HANDLER
-	LD	A,(SIOA_CNT)		; GET COUNT
-	DEC	A			; DECREMENT COUNT
-	LD	(SIOA_CNT),A		; SAVE SAVE IT
-	CP	5			; BUFFER LOW THRESHOLD
-	JR	NZ,SIOA_IN0		; IF NOT, BYPASS SETTING RTS
-	LD	A,5			; RTS IS IN WR5
-	OUT	(SIOA_CMD),A		; ADDRESS WR5
-	LD	A,$EA			; VALUE TO SET RTS
-	OUT	(SIOA_CMD),A		; DO IT
-SIOA_IN0:
-	LD	HL,(SIOA_TL)		; GET BUFFER TAIL POINTER
-	LD	E,(HL)			; GET BYTE
-	INC	HL			; BUMP TAIL POINTER
-	LD	A,L			; GET LOW BYTE
-	CP	SIOA_BUFEND & $FF	; PAST END?
-	JR	NZ,SIOA_IN1		; IF NOT, BYPASS POINTER RESET
-	LD	HL,SIOA_BUF		; ... OTHERWISE, RESET TO START OF BUFFER
-SIOA_IN1:
-	LD	(SIOA_TL),HL		; SAVE UPDATED TAIL POINTER
-	HB_EI				; INTERRUPTS OK AGAIN
-	XOR	A			; SIGNAL SUCCESS
-	RET				; AND DONE
-;
-SIOB_IN:
-	CALL	SIOB_IST		; RECEIVED CHAR READY?
-	JR	Z,SIOB_IN		; LOOP TILL WE HAVE SOMETHING IN BUFFER
+	CALL	SIO_IST			; SEE IF CHAR AVAILABLE
+	JR	Z,SIO_IN		; LOOP UNTIL SO
 	HB_DI				; AVOID COLLISION WITH INT HANDLER
-	LD	A,(SIOB_CNT)		; GET COUNT
+	LD	L,(IY+7)		; SET HL TO
+	LD	H,(IY+8)		; ... START OF BUFFER STRUCT
+	LD	A,(HL)			; GET COUNT
 	DEC	A			; DECREMENT COUNT
-	LD	(SIOB_CNT),A		; SAVE SAVE IT
-	CP	5			; BUFFER LOW THRESHOLD
-	JR	NZ,SIOB_IN0		; IF NOT, BYPASS SETTING RTS
+	LD	(HL),A			; SAVE UPDATED COUNT
+	CP	SIO_BUFSZ / 4		; BUFFER LOW THRESHOLD
+	JR	NZ,SIO_IN1		; IF NOT, BYPASS SETTING RTS
+	LD	C,(IY+3)		; C IS CMD/STATUS PORT ADR
 	LD	A,5			; RTS IS IN WR5
-	OUT	(SIOB_CMD),A		; ADDRESS WR5
-	LD	A,$EA			; VALUE TO SET RTS
-	OUT	(SIOB_CMD),A		; DO IT
-SIOB_IN0:
-	LD	HL,(SIOB_TL)		; GET BUFFER TAIL POINTER
-	LD	E,(HL)			; GET BYTE
-	INC	HL			; BUMP TAIL POINTER
-	LD	A,L			; GET LOW BYTE
-	CP	SIOB_BUFEND & $FF	; PAST END?
-	JR	NZ,SIOB_IN1		; IF NOT, BYPASS POINTER RESET
-	LD	HL,SIOB_BUF		; ... OTHERWISE, RESET TO START OF BUFFER
-SIOB_IN1:
-	LD	(SIOB_TL),HL		; SAVE UPDATED TAIL POINTER
+	OUT	(C),A			; ADDRESS WR5
+	LD	A,SIO_RTSON		; VALUE TO SET RTS
+	OUT	(C),A			; DO IT
+SIO_IN1:
+	INC	HL
+	INC	HL
+	INC	HL			; HL NOW HAS ADR OF TAIL PTR
+	PUSH	HL			; SAVE ADR OF TAIL PTR
+	LD	A,(HL)			; DEREFERENCE HL
+	INC	HL
+	LD	H,(HL)
+	LD	L,A			; HL IS NOW ACTUAL TAIL PTR
+	LD	C,(HL)			; C := CHAR TO BE RETURNED
+	INC	HL			; BUMP TAIL PTR
+	POP	DE			; RECOVER ADR OF TAIL PTR
+	LD	A,L			; GET LOW BYTE OF TAIL PTR
+	ADD	A,-SIO_BUFSZ-2		; SUBTRACT SIZE OF BUFFER AND POINTER
+	CP	E			; IF EQUAL TO START, TAIL PTR IS PAST BUF END
+	JR	NZ,SIO_IN2		; IF NOT, BYPASS
+	LD	H,D			; SET HL TO
+	LD	L,E			; ... TAIL PTR ADR
+	INC	HL			; BUMP PAST TAIL PTR
+	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+SIO_IN2:
+	EX	DE,HL			; DE := TAIL PTR VAL, HL := ADR OF TAIL PTR
+	LD	(HL),E			; SAVE UPDATED TAIL PTR
+	INC	HL
+	LD	(HL),D
+	LD	E,C			; MOVE CHAR TO RETURN TO E
 	HB_EI				; INTERRUPTS OK AGAIN
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND DONE
-;
 #ENDIF
 ;
 ;
@@ -363,17 +401,7 @@ SIOB_IN1:
 SIO_OUT:
 	CALL	SIO_OST			; READY FOR CHAR?
 	JR	Z,SIO_OUT		; LOOP IF NOT
-	LD	C,(IY+3)		; C := SIO CMD PORT
-#IF (SIOMODE == SIOMODE_RC)
-	INC	C			; BUMP TO DATA PORT
-#ENDIF
-#IF ((SIOMODE == SIOMODE_SMB) | (SIOMODE == SIOMODE_ZP))
-	DEC	C			; DECREMENT CMD PORT TWICE TO GET DATA PORT
-	DEC	C
-#ENDIF
-#IF (SIOMODE == SIOMODE_EZZ80)
-	DEC	C			; DECREMENT CMD PORT TO GET DATA PORT
-#ENDIF
+	LD	C,(IY+4)		; DATA PORT
 	OUT	(C),E			; SEND CHAR FROM E
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -396,25 +424,12 @@ SIO_IST:
 #ELSE
 ;
 SIO_IST:
-	LD	A,(IY+2)		; GET CHANNEL
-	OR	A			; SET FLAGS
-	JR	Z,SIOA_IST		; HANDLE CHANNEL A
-	DEC	A			; TEST FOR NEXT DEVICE
-	JR	Z,SIOB_IST		; HANDLE CHANNEL B
-	CALL 	PANIC			; ELSE FATAL ERROR
-	RET				; ... AND RETURN
-;
-SIOA_IST:
-	LD	A,(SIOA_CNT)		; GET BUFFER UTILIZATION COUNT
-	OR	A			; SET FLAGS
-	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	RET				; AND DONE
-;
-SIOB_IST:
-	LD	A,(SIOB_CNT)		; GET BUFFER UTILIZATION COUNT
+	LD	L,(IY+7)		; GET ADDRESS
+	LD	H,(IY+8)		; ... OF RECEIVE BUFFER
+	LD	A,(HL)			; BUFFER UTILIZATION COUNT
 	OR	A			; SET FLAGS
 	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	RET				; DONE
+	RET
 ;
 #ENDIF
 ;
@@ -461,8 +476,8 @@ SIO_INITDEVX:
 	JR	NZ,SIO_INITDEV1	; IF DE == -1, REINIT CURRENT CONFIG
 ;
 	; LOAD EXISTING CONFIG TO REINIT
-	LD	E,(IY+4)		; LOW BYTE
-	LD	D,(IY+5)		; HIGH BYTE	
+	LD	E,(IY+5)		; LOW BYTE
+	LD	D,(IY+6)		; HIGH BYTE	
 ;
 SIO_INITDEV1:
 	PUSH	DE			; SAVE CONFIG
@@ -575,12 +590,37 @@ BROK:
 	CALL	PRTHEXBYTE
 	PRTC(']')
 	POP	AF
-#ENDIF	
-	
+#ENDIF
+;
+; SET INTERRUPT VECTOR OFFSET WR2
+;
+#IF (INTMODE == 2)
+	LD	A,(IY+2)		; CHIP / CHANNEL
+	SRL	A			; SHIFT AWAY CHANNEL BIT
+	LD	E,SIO0_VEC		; ASSUME CHIP 0
+	JR	Z,SIO_IVT1		; IF SO, DO IT
+	LD	E,SIO1_VEC		; ASSUME CHIP 1
+	DEC	A			; CHIP 1?
+	JR	Z,SIO_IVT1		; IF SO, TO IT
+	CALL 	PANIC			; IMPOSSIBLE SITUATION
+SIO_IVT1:
+	LD	A,E			; VALUE TO A
+	LD	(SIO_INITVALS+7),A	; SAVE IT
+
+#IF (SIODEBUG)
+	PUSH	AF
+	PRTS(" WR2[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP	AF
+#ENDIF
+
+#ENDIF
+
 	POP	DE			; RESTORE CONFIG
 
-	LD	(IY+4),E		; SAVE LOW WORD
-	LD	(IY+5),D		; SAVE HI WORD
+	LD	(IY+5),E		; SAVE LOW WORD
+	LD	(IY+6),D		; SAVE HI WORD
 ;
 	; PROGRAM THE SIO CHIP CHANNEL
 	LD	C,(IY+3)		; COMMAND PORT
@@ -591,8 +631,8 @@ BROK:
 #IF (INTMODE > 0)
 ;
 	; RESET THE RECEIVE BUFFER
-	LD	E,(IY+6)
-	LD	D,(IY+7)		; DE := _CNT
+	LD	E,(IY+7)
+	LD	D,(IY+8)		; DE := _CNT
 	XOR	A			; A := 0
 	LD	(DE),A			; _CNT = 0
 	INC	DE			; DE := ADR OF _HD
@@ -624,16 +664,16 @@ SIO_INITVALS:
 #ELSE
 	.DB	$01, $18		; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS
 #ENDIF
-	.DB	$02, IVT_SER0		; WR2: INTERRUPT VECTOR OFFSET
+	.DB	$02, IVT_SER0		; WR2: IM2 INTERRUPT VECTOR OFFSET
 	.DB	$03, $E1		; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE
-	.DB	$05, $EA		; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
+	.DB	$05, SIO_RTSON		; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
 SIO_INITLEN	.EQU	$ - SIO_INITVALS
 ;
 ;
 ;
 SIO_QUERY:
-	LD	E,(IY+4)		; FIRST CONFIG BYTE TO E
-	LD	D,(IY+5)		; SECOND CONFIG BYTE TO D
+	LD	E,(IY+5)		; FIRST CONFIG BYTE TO E
+	LD	D,(IY+6)		; SECOND CONFIG BYTE TO D
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
 ;
@@ -646,21 +686,86 @@ SIO_DEVICE:
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
+; SIO CHIP PROBE
+; CHECK FOR PRESENCE OF SIO CHIPS AND POPULATE THE
+; SIO_MAP BITMAP (ONE BIT PER CHIP).  THIS DETECTS
+; CHIPS, NOT CHANNELS.  EACH CHIP HAS 2 CHANNELS.
+; MAX OF TWO CHIPS CURRENTLY.  INT VEC VALUE IS TRASHED!
+;
+SIO_PROBE:
+	; CLEAR THE PRESENCE BITMAP
+	LD	HL,SIO_MAP		; HL POINTS TO BITMAP
+	XOR	A			; ZERO
+	LD	(SIO_MAP),A		; CLEAR CHIP PRESENT BITMAP
+	; INIT THE INT VEC REGISTER OF ALL POSSIBLE CHIPS
+	; TO ZERO.  A IS STILL ZERO.
+	LD	B,2			; WR2 REGISTER (INT VEC)
+	LD	C,SIO0B_CMD		; FIRST CHIP
+	CALL	SIO_WR			; WRITE ZERO TO CHIP REG
+#IF (SIOCNT >= 2)
+	LD	C,SIO1B_CMD		; SECOND CHIP
+	CALL	SIO_WR			; WRITE ZERO TO CHIP REG
+#ENDIF
+	; FIRST POSSIBLE CHIP
+	LD	C,SIO0B_CMD		; FIRST CHIP CMD/STAT PORT
+	CALL	SIO_PROBECHIP		; PROBE IT
+	JR	NZ,SIO_PROBE1		; IF NOT ZERO, NOT FOUND
+	SET	0,(HL)			; SET BIT FOR FIRST CARD
+SIO_PROBE1:
+;
+#IF (SIOCNT >= 2)
+	LD	C,SIO1B_CMD		; SECOND CHIP CMD/STAT PORT
+	CALL	SIO_PROBECHIP		; PROBE IT
+	JR	NZ,SIO_PROBE2		; IF NOT ZERO, NOT FOUND
+	SET	1,(HL)			; SET BIT FOR SECOND CARD
+SIO_PROBE2:
+#ENDIF
+;
+	RET
+;
+SIO_PROBECHIP:
+	; READ WR2 TO ENSURE IT IS ZERO (AVOID PHANTOM PORTS)
+	CALL	SIO_RD			; GET VALUE
+	AND	$F0			; ONLY TOP NIBBLE
+	RET	NZ			; ABORT IF NOT ZERO
+	; WRITE INT VEC VALUE TO WR2
+	LD	A,$FF			; TEST VALUE
+	CALL	SIO_WR			; WRITE IT
+	; READ WR2 TO CONFIRM VALUE WRITTEN
+	CALL	SIO_RD			; REREAD VALUE
+	AND	$F0			; ONLY TOP NIBBLE
+	CP	$F0			; COMPARE
+	RET				; DONE, Z IF FOUND, NZ IF MISCOMPARE
+;
+; READ/WRITE CHIP REGISTER.  ENTER CHIP CMD/STAT PORT ADR IN C
+; AND CHIP REGISTER NUMBER IN B.  VALUE TO WRITE IN A OR VALUE
+; RETURNED IN A.
+;
+SIO_WR:
+	OUT	(C),B			; SELECT CHIP REGISTER
+	OUT	(C),A			; WRITE VALUE
+	RET
+;
+SIO_RD:
+	OUT	(C),B			; SELECT CHIP REGISTER
+	IN	A,(C)			; GET VALUE
+	RET
+;
 ; SIO DETECTION ROUTINE
 ;
 SIO_DETECT:
-	LD	C,(IY+3)		; COMMAND PORT
-	XOR	A	
-	OUT	(C),A			; ACCESS RD0
-	IN	A,(C)			; GET RD0 VALUE
-	LD	B,A			; SAVE IT
-	LD	A,1	
-	OUT	(C),A			; ACCESS RD1
-	IN	A,(C)			; GET RD1 VALUE
-	CP	B			; COMPARE
-	LD	A,SIO_NONE		; ASSUME NOTHING THERE
-	RET	Z			; RD0=RD1 MEANS NOTHING THERE
-	LD	A,SIO_SIO		; GUESS WE HAVE A VALID SIO HERE
+	LD	B,(IY+2)		; GET  CHIP/CHANNEL
+	SRL	B			; SHIFT AWAY THE CHANNEL BIT
+	INC	B			; NUMBER OF TIMES TO ROTATE BITS
+	LD	A,(SIO_MAP)		; BIT MAP IN A
+SIO_DETECT1:
+	; ROTATE DESIRED CHIP BIT INTO CF
+	RRA				; ROTATE NEXT BIT INTO CF
+	DJNZ	SIO_DETECT1		; DO THIS UNTIL WE HAVE DESIRED BIT
+	; RETURN CHIP TYPE
+	LD	A,SIO_NONE		; ASSUME NOTHING HERE
+	RET	NC			; IF CF NOT SET, RETURN
+	LD	A,SIO_SIO		; CHIP TYPE IS SIO
 	RET				; DONE
 ;
 ;
@@ -692,8 +797,8 @@ SIO_PRTCFG:
 	RET	Z			; IF ZERO, NOT PRESENT
 ;
 	PRTS(" MODE=$")			; FORMATTING
-	LD	E,(IY+4)		; LOAD CONFIG
-	LD	D,(IY+5)		; ... WORD TO DE
+	LD	E,(IY+5)		; LOAD CONFIG
+	LD	D,(IY+6)		; ... WORD TO DE
 	CALL	PS_PRTSC0		; PRINT CONFIG
 ;
 	XOR	A
@@ -711,51 +816,101 @@ SIO_STR_SIO	.DB	"SIO$"
 ; WORKING VARIABLES
 ;
 SIO_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+SIO_MAP		.DB	0		; CHIP PRESENCE BITMAP
 ;
 #IF (INTMODE == 0)
 ;
-SIOA_RCVBUF	.EQU	0
-SIOB_RCVBUF	.EQU	0
+SIO0A_RCVBUF	.EQU	0
+SIO0B_RCVBUF	.EQU	0
+;
+#IF (SIOCNT >= 2)
+SIO1A_RCVBUF	.EQU	0
+SIO1B_RCVBUF	.EQU	0
+#ENDIF
 ;
 #ELSE
 ;
-; CHANNEL A RECEIVE BUFFER
-SIOA_RCVBUF:
-SIOA_CNT	.DB	0		; CHARACTERS IN RING BUFFER
-SIOA_HD		.DW	SIOA_BUF	; BUFFER HEAD POINTER
-SIOA_TL		.DW	SIOA_BUF	; BUFFER TAIL POINTER
-SIOA_BUF	.FILL	32,0		; RECEIVE RING BUFFER
-SIOA_BUFEND	.EQU	$		; END OF BUFFER
-SIOA_BUFSZ	.EQU	$ - SIOA_BUF	; SIZE OF RING BUFFER
+; SIO0 CHANNEL A RECEIVE BUFFER
+SIO0A_RCVBUF:
+SIO0A_CNT	.DB	0		; CHARACTERS IN RING BUFFER
+SIO0A_HD	.DW	SIO0A_BUF	; BUFFER HEAD POINTER
+SIO0A_TL	.DW	SIO0A_BUF	; BUFFER TAIL POINTER
+SIO0A_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
+;
+; SIO0 CHANNEL B RECEIVE BUFFER
+SIO0B_RCVBUF:
+SIO0B_CNT	.DB	0		; CHARACTERS IN RING BUFFER
+SIO0B_HD	.DW	SIO0B_BUF	; BUFFER HEAD POINTER
+SIO0B_TL	.DW	SIO0B_BUF	; BUFFER TAIL POINTER
+SIO0B_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
+;
+#IF (SIOCNT >= 2)
+;
+; SIO1 CHANNEL A RECEIVE BUFFER
+SIO1A_RCVBUF:
+SIO1A_CNT	.DB	0		; CHARACTERS IN RING BUFFER
+SIO1A_HD	.DW	SIO1A_BUF	; BUFFER HEAD POINTER
+SIO1A_TL	.DW	SIO1A_BUF	; BUFFER TAIL POINTER
+SIO1A_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
+;
+; SIO1 CHANNEL B RECEIVE BUFFER
+SIO1B_RCVBUF:
+SIO1B_CNT	.DB	0		; CHARACTERS IN RING BUFFER
+SIO1B_HD	.DW	SIO1B_BUF	; BUFFER HEAD POINTER
+SIO1B_TL	.DW	SIO1B_BUF	; BUFFER TAIL POINTER
+SIO1B_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
 ;
-; CHANNEL B RECEIVE BUFFER
-SIOB_RCVBUF:
-SIOB_CNT	.DB	0		; CHARACTERS IN RING BUFFER
-SIOB_HD		.DW	SIOB_BUF	; BUFFER HEAD POINTER
-SIOB_TL		.DW	SIOB_BUF	; BUFFER TAIL POINTER
-SIOB_BUF	.FILL	32,0		; RECEIVE RING BUFFER
-SIOB_BUFEND	.EQU	$		; END OF BUFFER
-SIOB_BUFSZ	.EQU	$ - SIOB_BUF	; SIZE OF RING BUFFER
+#ENDIF
 ;
 #ENDIF
 ;
 ; SIO PORT TABLE
 ;
 SIO_CFG:
-	; SIO CHANNEL A
+	; SIO0 CHANNEL A
+SIO0A_CFG:
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
 	.DB	0			; SIO TYPE (SET DURING INIT)
-	.DB	0			; SIO CHANNEL (A)
-	.DB	SIOA_CMD		; BASE PORT (CMD PORT)
-	.DW	DEFSIOACFG		; LINE CONFIGURATION
-	.DW	SIOA_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DB	$00			; CHIP 0 / CHANNEL A (LOW BIT IS CHANNEL)
+	.DB	SIO0A_CMD		; CMD/STATUS PORT
+	.DB	SIO0A_DAT		; DATA PORT
+	.DW	DEFSIO0ACFG		; LINE CONFIGURATION
+	.DW	SIO0A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	; SIO CHANNEL B
+SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
+;
+	; SIO0 CHANNEL B
+SIO0B_CFG:
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
 	.DB	0			; SIO TYPE (SET DURING INIT)
-	.DB	1			; SIO CHANNEL (B)
-	.DB	SIOB_CMD		; BASE PORT (CMD PORT)
-	.DW	DEFSIOBCFG		; LINE CONFIGURATION
-	.DW	SIOB_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+	.DB	$01			; CHIP 0 / CHANNEL B (LOW BIT IS CHANNEL)
+	.DB	SIO0B_CMD		; CMD/STATUS PORT
+	.DB	SIO0B_DAT		; DATA PORT
+	.DW	DEFSIO0BCFG		; LINE CONFIGURATION
+	.DW	SIO0B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+#IF (SIOCNT >= 2)
+;
+	; SIO1 CHANNEL A
+SIO1A_CFG:
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; SIO TYPE (SET DURING INIT)
+	.DB	$02			; CHIP 1 / CHANNEL A (LOW BIT IS CHANNEL)
+	.DB	SIO1A_CMD		; CMD/STATUS PORT
+	.DB	SIO1A_DAT		; DATA PORT
+	.DW	DEFSIO1ACFG		; LINE CONFIGURATION
+	.DW	SIO1A_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+	; SIO1 CHANNEL B
+SIO1B_CFG:
+	.DB	0			; DEVICE NUMBER (SET DURING INIT)
+	.DB	0			; SIO TYPE (SET DURING INIT)
+	.DB	$03			; CHIP 1 / CHANNEL B (LOW BIT IS CHANNEL)
+	.DB	SIO1B_CMD		; CMD/STATUS PORT
+	.DB	SIO1B_DAT		; DATA PORT
+	.DW	DEFSIO1BCFG		; LINE CONFIGURATION
+	.DW	SIO1B_RCVBUF		; POINTER TO RCV BUFFER STRUCT
+;
+#ENDIF
 ;
-SIO_CNT	.EQU	($ - SIO_CFG) / 8
+SIO_CFGCNT	.EQU	($ - SIO_CFG) / SIO_CFGSIZ
diff --git a/Source/HBIOS/spk.asm b/Source/HBIOS/spk.asm
index fea556c7..ffa1c42e 100644
--- a/Source/HBIOS/spk.asm
+++ b/Source/HBIOS/spk.asm
@@ -9,7 +9,7 @@ SPK_INIT:
 	LD	A,DSRTC_BASE
 	CALL	PRTHEXBYTE
 	CALL	SPK_BEEP
-	XOR		A
+	XOR	A
 	RET
 ;
 SPK_BEEP:
@@ -17,7 +17,8 @@ SPK_BEEP:
 	PUSH	HL
 	LD	HL,400			; CYCLES OF TONE
 	;LD	B,%00000100		; D2 MAPPED TO Q0
-	LD	A,DSRTC_RESET
+	;LD	A,DSRTC_RESET
+	LD	A,(RTCVAL)		; GET RTC PORT VALUE FROM SHADOW
 	OR	%00000100		; D2 MAPPED TO Q0
 	LD	B,A
 SPK_BEEP1:

From a3844a0149875bf454e40a5b0196910e39b9a34a Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 19:03:16 +0800
Subject: [PATCH 11/16] Resync

---
 Doc/ReadMe.txt              | 52 -------------------------------------
 ReadMe.txt                  |  2 +-
 Source/HBIOS/cfg_ezz80.asm  | 17 +++++++++---
 Source/HBIOS/cfg_mk4.asm    | 13 +++++-----
 Source/HBIOS/cfg_n8.asm     |  7 ++---
 Source/HBIOS/cfg_rcz180.asm | 26 +++++++++++++------
 Source/HBIOS/cfg_rcz80.asm  | 17 +++++++++---
 Source/HBIOS/cfg_sbc.asm    | 19 ++++++++++----
 Source/HBIOS/cfg_zeta.asm   |  3 +++
 Source/HBIOS/plt_ezz80.inc  |  1 -
 Source/HBIOS/plt_rcz180.inc |  1 -
 Source/HBIOS/plt_rcz80.inc  |  1 -
 Source/HBIOS/plt_sbc.inc    |  6 ++---
 Source/HBIOS/plt_zeta.inc   |  3 ---
 Source/HBIOS/plt_zeta2.inc  |  3 ---
 Source/HBIOS/std.asm        |  3 +++
 16 files changed, 79 insertions(+), 95 deletions(-)
 delete mode 100644 Doc/ReadMe.txt

diff --git a/Doc/ReadMe.txt b/Doc/ReadMe.txt
deleted file mode 100644
index 9f596272..00000000
--- a/Doc/ReadMe.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-***********************************************************************
-***                                                                 ***
-***                          R o m W B W                            ***
-***                                                                 ***
-***                    Z80/Z180 System Software                     ***
-***                                                                 ***
-***********************************************************************
-
-This directory ("Doc") is part of the RomWBW System Software 
-distribution archive.  It contains documentation for components of 
-the system.
-
-CPM Manual ("CPM Manual.pdf")
------------------------------
-
-The original DRI CP/M 2.x Operating System Manual.  This should be 
-considered the primary reference for system operation.  The section 
-on CP/M 2 Alteration can be ignored since this work has already been 
-completed as part of the RomWBW distribution.
-
-DDTZ Manual ("DDTZ.doc")
-------------------------
-
-Manual for the DDTZ v2.7 debug tool included on the ROM drive.
-
-FDisk Manual ("FDisk Manual.pdf")
----------------------------------
-
-The operational manual for John Coffman's hard disk partitioning 
-program.  This program is included in RomWBW as FDISK80.
-
-RomWBW Architecture ("RomWBW Architecture.pdf")
------------------------------------------------
-
-Document describing the architecture of the RomWBW HBIOS.  It 
-includes reference information for the HBIOS calls.
-
-ZCPR Manual ("ZCPR Manual.pdf")
--------------------------------
-
-ZCPR is the command proccessor portion of Z-System.  This is the 
-manual for ZCPR 1.x as included in RomWBW.  The installation 
-instructions can be ignored since that work has already been 
-completed as part of the RomWBW distribution.
-
-ZSDOS Manual ("ZSDOS Manual.pdf")
----------------------------------
-
-ZSDOS is the DOS portion of Z-System.  This is the manual fo ZSDOS 
-1.x as included in RomWBW.  The installation instructions can be 
-ignored since that work has already been completed as part of the 
-RomWBW distribution.
\ No newline at end of file
diff --git a/ReadMe.txt b/ReadMe.txt
index 094352a0..a1875a4c 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre, 2019-06-21
+Version 2.9.2-pre.1, 2019-07-22
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index bb188c94..93785db4 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_Z2		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	FALSE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -28,12 +30,18 @@ UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
-SIOMODE		.EQU	SIOMODE_EZZ80	; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP
-DEFSIOACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIOBCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIODEBUG	.EQU	FALSE		; PS
 DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
 DEFSIOCLK	.EQU	1843200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-SIODEBUG	.EQU	FALSE		;PS
+SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIO0MODE	.EQU	SIOMODE_EZZ80	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
+DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
@@ -91,3 +99,4 @@ PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 232143c3..933c17e6 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_Z180		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	FALSE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -26,7 +28,6 @@ ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
@@ -70,7 +71,6 @@ SDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE
 SDCSIOFAST	.EQU	TRUE		; TABLE-DRIVEN BIT INVERTER
 ;
 PRPENABLE	.EQU	FALSE		; TRUE FOR PROPIO SUPPORT
-PRPIOB		.EQU	$A8		; PORT IO ADDRESS BASE
 PRPSDENABLE	.EQU	TRUE		; TRUE FOR PROPIO SD SUPPORT
 PRPSDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
 PRPCONENABLE	.EQU	TRUE		; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
@@ -98,17 +98,18 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ; 18.432MHz OSC @ FULL SPEED
 ;
 Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 ; 18.432MHz OSC @ DOUBLE SPEED
 ;
 ;Z180_CLKDIV	.EQU	2		; 0=OSC/2, 1=OSC, 2=OSC*2
-;Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
-;Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
+;Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES (0-3)
+;Z180_IOWAIT	.EQU	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index cd7ac5bd..8dc7498d 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_N8		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	FALSE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -26,7 +28,6 @@ ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
@@ -92,8 +93,8 @@ BOOT_TIMEOUT	.EQU	20		; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
 BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.EQU	3		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	3		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index ec367e59..fa6dabf3 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_Z180		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	TRUE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -25,14 +27,21 @@ DSRTCCHG	.EQU	FALSE		; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
 ASCIENABLE	.EQU	TRUE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
-SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
-SIODEBUG	.EQU	FALSE		;PS
-DEFSIOACFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
-DEFSIOBCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
+;
+SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO SUPPORT
+SIODEBUG	.EQU	FALSE		; PS
 DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
 DEFSIOCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
+SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIO0MODE	.EQU	SIOMODE_RC	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
+DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
@@ -88,11 +97,12 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ; 18.432MHz OSC @ FULL SPEED
 ;
 Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES TO INSERT (0-3)
-Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
+Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
 ;
 PIO_4P		.EQU	FALSE		; TRUE FOR ECB-4PIO PIO SUPPORT
 PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 3124456a..6beed599 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_Z2		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	1		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	TRUE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -28,12 +30,18 @@ UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 ACIAENABLE	.EQU	TRUE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP
-DEFSIOACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
-DEFSIOBCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+SIODEBUG	.EQU	FALSE		; PS
 DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
 DEFSIOCLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-SIODEBUG	.EQU	FALSE		;PS
+SIOCNT		.EQU	2		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIO0MODE	.EQU	SIOMODE_RC	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
+SIO1MODE	.EQU	SIOMODE_RC	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIO0BASE	.EQU	$80		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
+DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
@@ -91,3 +99,4 @@ PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 63f3a32f..1b9079bb 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_SBC		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	FALSE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -28,12 +30,18 @@ UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO SUPPORT
-SIOMODE		.EQU	SIOMODE_ZP	; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP
-DEFSIOACFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG
-DEFSIOBCFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG
-DEFSIODIV	.EQU	8		; 1=RC2014, SMB, 2/4/8/16/32/64/128/256 for ZP depending on jumper X5
+SIODEBUG	.EQU	FALSE		; PS
+DEFSIODIV	.EQU	8		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
 DEFSIOCLK	.EQU	4915200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
-SIODEBUG	.EQU	FALSE		;
+SIOCNT		.EQU	1		; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS)
+SIO0MODE	.EQU	SIOMODE_ZP	; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80
+;SIO1MODE	.EQU	SIOMODE_ZP	; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB
+SIO0BASE	.EQU	$B0		; IO PORT ADDRESS BASE FOR FIRST SIO CHIP
+;SIO1BASE	.EQU	$84		; IO PORT ADDRESS BASE FOR SECOND SIO CHIP
+DEFSIO0ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+DEFSIO0BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+;DEFSIO1ACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
+;DEFSIO1BCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
@@ -103,3 +111,4 @@ PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 4484ce46..3279cbd0 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -10,6 +10,8 @@ MEMMGR		.EQU	MM_SBC		; MM_NONE, MM_SBC, MM_Z2, MM_N8, MM_Z180
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
 INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+DIAGENABLE	.EQU	FALSE		; TRUE FOR DIAGNOSTIC CODE PORT OUTPUT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -82,3 +84,4 @@ PIO_ZP		.EQU	FALSE		; TRUE FOR ECB-ZILOG PERIPHERALS BOARD
 PPI_SBC		.EQU	FALSE		; TRUE FOR SBC V2 8255 (IF NOT BEING USED FOR PPIDE)
 ;
 UFENABLE	.EQU	FALSE		; TRUE FOR ECB USB-FIFO SUPPORT
+
diff --git a/Source/HBIOS/plt_ezz80.inc b/Source/HBIOS/plt_ezz80.inc
index 03bbd3ab..34ca83ce 100644
--- a/Source/HBIOS/plt_ezz80.inc
+++ b/Source/HBIOS/plt_ezz80.inc
@@ -8,7 +8,6 @@ MPGSEL_3	.EQU	$7B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
 MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
-SIOBASE 	.EQU 	$80	; RC OR SMB SIO DEFAULT
 ;
 WDOG		.EQU	$6F	; WATCHDOG
 ;
diff --git a/Source/HBIOS/plt_rcz180.inc b/Source/HBIOS/plt_rcz180.inc
index 5a046964..03ba4bfd 100644
--- a/Source/HBIOS/plt_rcz180.inc
+++ b/Source/HBIOS/plt_rcz180.inc
@@ -12,6 +12,5 @@ MPGENA		.EQU	$7C		; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	$0C		; ADDRESS OF RTC LATCH AND INPUT PORT
 ;
 Z180_BASE	.EQU	$C0		; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
-SIOBASE 	.EQU 	$80 		; RC OR SMB SIO DEFAULT
 ;
 #INCLUDE "z180.inc"
diff --git a/Source/HBIOS/plt_rcz80.inc b/Source/HBIOS/plt_rcz80.inc
index 0b86af0e..b9b1764e 100644
--- a/Source/HBIOS/plt_rcz80.inc
+++ b/Source/HBIOS/plt_rcz80.inc
@@ -8,4 +8,3 @@ MPGSEL_3	.EQU	$7B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
 MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
-SIOBASE 	.EQU 	$80 	; RC OR SMB SIO DEFAULT
diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index 7ca70514..ed472aae 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -19,8 +19,8 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
-SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
-PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO DEFAULT PIO DEFAULT
+PIOZBASE	.EQU	$88		; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
+;
 ;
 FIFO_BASE       .EQU	$0C		; ECB USB-FIFO DEFAULT PORT
diff --git a/Source/HBIOS/plt_zeta.inc b/Source/HBIOS/plt_zeta.inc
index bb9210bd..5ba12e42 100644
--- a/Source/HBIOS/plt_zeta.inc
+++ b/Source/HBIOS/plt_zeta.inc
@@ -9,6 +9,3 @@ MPCL_ROM	.EQU 	SBC_BASE + $1C	; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
 ;
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
-SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
-PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
diff --git a/Source/HBIOS/plt_zeta2.inc b/Source/HBIOS/plt_zeta2.inc
index 1613a456..c3603ee5 100644
--- a/Source/HBIOS/plt_zeta2.inc
+++ b/Source/HBIOS/plt_zeta2.inc
@@ -11,9 +11,6 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
-SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
-PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
 ;
 CTCBASE		.EQU	$20	; CTC BASE I/O ADDRESS
 CTCA		.EQU	CTCBASE + 0	; CTC CHANNEL A
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 79030499..bf4a9323 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -266,6 +266,9 @@ IVT_PIO0	.EQU	18
 IVT_PIO1	.EQU	20
 IVT_PIO2	.EQU	22
 IVT_PIO3	.EQU	24
+IVT_SER2	.EQU	26
+IVT_SER3	.EQU	28
+;
 ;
 ; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
 ; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.

From 12c99e914418a4da90d0369c51f693182d1f3535 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 19:30:52 +0800
Subject: [PATCH 12/16] Resync

---
 Source/HBIOS/hbios.asm | 138 ++++++++++++++++++-----------------------
 1 file changed, 62 insertions(+), 76 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index d0011714..75c6c0e2 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -67,14 +67,14 @@ MODCNT	.SET	MODCNT + 1
 ;
 ;
 ;
-#IF ((PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180))
-#DEFINE	DIAGP	$00
-#ENDIF
+;#IF ((PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180))
+;#DEFINE	DIAGPORT	$00
+;#ENDIF
 ;
-#IFDEF DIAGP
+#IF (DIAGENABLE)
 #DEFINE	DIAG(N)	PUSH AF
   #DEFCONT \	LD A,N
-  #DEFCONT \	OUT (DIAGP),A
+  #DEFCONT \	OUT (DIAGPORT),A
   #DEFCONT \	POP AF
 #ELSE
 #DEFINE	DIAG(N)	\;
@@ -301,7 +301,7 @@ HBX_ROM:
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
 	OUT	(MPGSEL_0),A		; BANK_0: 0K - 16K
-	;OUT	(DIAGP),A		; *DEBUG*
+	;OUT	(DIAGPORT),A		; *DEBUG*
 	INC	A			;
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
 	RET				; DONE
@@ -774,9 +774,9 @@ HB_START:
 	DI				; NO INTERRUPTS
 	IM	1			; INTERRUPT MODE 1
 ;
-#IFDEF DIAGP
+#IF (DIAGENABLE)
 	LD	A,%00000001
-	OUT	(DIAGP),A
+	OUT	(DIAGPORT),A
 #ENDIF
 ;
 	LD	SP,HBX_LOC		; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
@@ -1347,6 +1347,15 @@ PSCNX	.EQU	$ + 1
   #ENDIF
 ;
 #ENDIF
+;
+#IF 0
+HB_SPDTST:
+	CALL	HB_CPUSPD		; CPU SPEED DETECTION
+	CALL	NEWLINE
+	LD	HL,(CB_CPUKHZ)
+	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
+	JR	HB_SPDTST
+#ENDIF
 ;
 	HB_EI				; INTERRUPTS SHOULD BE OK NOW
 ;
@@ -2405,7 +2414,7 @@ HB_BADINT:
 	LD	HL,HB_BADINTCNT
 	INC	(HL)
 	LD	A,(HL)
-	OUT	(DIAGP),A
+	OUT	(DIAGPORT),A
 	OR	$FF
 	RET
 HB_BADINTCNT	.DB	0
@@ -2732,7 +2741,7 @@ SIZ_MD		.EQU	$ - ORG_MD
 		.ECHO	SIZ_MD
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (FDENABLE)
 ORG_FD		.EQU	$
   #INCLUDE "fd.asm"
@@ -2741,7 +2750,7 @@ SIZ_FD		.EQU	$ - ORG_FD
 		.ECHO	SIZ_FD
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (RFENABLE)
 ORG_RF	.EQU	$
   #INCLUDE "rf.asm"
@@ -2750,7 +2759,7 @@ SIZ_RF	.EQU	$ - ORG_RF
 		.ECHO	SIZ_RF
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (IDEENABLE)
 ORG_IDE		.EQU	$
   #INCLUDE "ide.asm"
@@ -2759,7 +2768,7 @@ SIZ_IDE		.EQU	$ - ORG_IDE
 		.ECHO	SIZ_IDE
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (PPIDEENABLE)
 ORG_PPIDE	.EQU	$
   #INCLUDE "ppide.asm"
@@ -2768,7 +2777,7 @@ SIZ_PPIDE	.EQU	$ - ORG_PPIDE
 		.ECHO	SIZ_PPIDE
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (SDENABLE)
 ORG_SD		.EQU	$
   #INCLUDE "sd.asm"
@@ -2777,7 +2786,7 @@ SIZ_SD		.EQU	$ - ORG_SD
 		.ECHO	SIZ_SD
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (HDSKENABLE)
 ORG_HDSK	.EQU	$
   #INCLUDE "hdsk.asm"
@@ -2786,7 +2795,7 @@ SIZ_HDSK	.EQU	$ - ORG_HDSK
 		.ECHO	SIZ_HDSK
 		.ECHO	" bytes.\n"
 #ENDIF
-;
+
 #IF (TERMENABLE)
 ORG_TERM	.EQU	$
   #INCLUDE "term.asm"
@@ -2813,7 +2822,6 @@ SIZ_AY	.EQU	$ - ORG_AY
 		.ECHO	SIZ_AY
 		.ECHO	" bytes.\n"
 #ENDIF
-;
 #IF (PIO_4P | PIO_ZP | PPI_SBC)
 ORG_PIO		.EQU	$
   #INCLUDE "pio.asm"
@@ -2822,15 +2830,7 @@ SIZ_PIO		.EQU	$ - ORG_PIO
 		.ECHO	SIZ_PIO
 		.ECHO	" bytes.\n"
 #ENDIF
-;
-#IF (UFENABLE)
-ORG_UF	.EQU	$
-  #INCLUDE "usbfifo.asm"
-SIZ_UF	.EQU	$ - ORG_UF
-		.ECHO	"USB-FIFO occupies "
-		.ECHO	SIZ_UF
-		.ECHO	" bytes.\n"
-#ENDIF
+
 ;
 #DEFINE USEDELAY
 #INCLUDE "util.asm"
@@ -2867,42 +2867,39 @@ HB_CPUSPD:
 	RET	NZ
 ;
 HB_CPUSPD1:
-;	LD	B,8
-;HB_CPUSPDX:
-;	PUSH	BC
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+	; USE MEM W/S = 2 AND I/O W/S = 3 FOR TEST
+	IN0	A,(Z180_DCNTL)
+	PUSH	AF
+	LD	A,$B0
+	;LD	A,$F0
+	OUT0	(Z180_DCNTL),A
+#ENDIF
 
 	; WAIT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
 	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
-
 	CALL	HB_RDSEC		; GET SECONDS
 	LD	(HB_CURSEC),A		; AND INIT CURSEC
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
 	LD	(HB_CURSEC),A		; SAVE NEW VALUE
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
-
-;	PUSH	DE
-;	POP	BC
-;	CALL	NEWLINE
-;	CALL	PRTHEXWORD
-
-;	POP	BC
-;	DJNZ	HB_CPUSPDX
+;
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
+	; RESTORE W/S SETTINGS FROM BEFORE TEST
+	POP	AF
+	OUT0	(Z180_DCNTL),A
+#ENDIF
 ;
 	LD	A,H
 	OR	L
 	RET	Z			; FAILURE, USE DEFAULT CPU SPEED
-
 ;
 	; MOVE LOOP COUNT TO HL
 	PUSH	DE
 	POP	HL
 ;
 	; TIMES 4 FOR CPU SPEED IN KHZ
-	RES	0,L			; GRANULARITY
-#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-	SLA	L
-	RL	H
-#ENDIF
+;	RES	0,L			; GRANULARITY
 	SLA	L
 	RL	H
 	SLA	L
@@ -2921,60 +2918,47 @@ HB_WAITSEC:
 	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
+;
 #IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_EZZ80))
 	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY32
-	CALL	DLY8
-	CALL	DLY2
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	JP	$ + 3			; 10 TSTATES
-	;LD	A,R			; 9 TSTATES
-	INC	BC			; 6 TSTATES
-	;LD	A,(BC)			; 7 TSTATES
-	;NOP				; 4 TSTATES
-	NOP				; 4 TSTATES
+	CALL	DLY16
+	CALL	DLY1			; 27 TSTATES
+	SBC	HL,HL			; 15 TSTATES
+	SBC	HL,HL			; 15 TSTATES
+	INC	HL			; 6 TSTATES
+	INC	HL			; 6 TSTATES
 #ENDIF
-
+;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
-	; LOOP TARGET IS 8000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 8
-	;CALL	DLY64
-	CALL	DLY32
-	CALL	DLY16
-	CALL	DLY8
-	CALL	DLY4
+	; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
 	CALL	DLY2
-	CALL	DLY1			; CALL (25TS) & RET (18TS) = 43TS
-	OR	A			; 7 TSTATES
-	OR	A			; 7 TSTATES
-	;OR	A			; 7 TSTATES
-	;OR	A			; 7 TSTATES
-	NOP				; 6 TSTATES
-	;NOP				; 6 TSTATES
-	;NOP				; 6 TSTATES
-	;NOP				; 6 TSTATES
-	;NOP				; 6 TSTATES
+	ADD	IX,BC			; 10 + 4 = 14 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
+	NOP				; 5 TSTATES
 #ENDIF
 ;
-	PUSH	DE
+	PUSH	DE			; SAVE COUNTER
 	CALL	HB_RDSEC		; GET SECONDS
-	POP	DE
+	POP	DE			; RESTORE COUNTER
 	INC	DE			; BUMP COUNTER
 	LD	HL,HB_CURSEC		; POINT TO COMP VALUE
 	CP	(HL)			; TEST FOR CHANGE
 	RET	NZ			; DONE IF TICK OCCURRED
-	LD	A,D			; CHECK HL
+	LD	A,D			; CHECK DE
 	OR	E			; ... FOR OVERFLOW
 	RET	Z			; TIMEOUT, SOMETHING IS WRONG
 	JR	HB_WAITSEC1		; LOOP
 ;
 HB_RDSEC:
 	; READ SECONDS BYTE INTO A
-	LD	C,$81			; SECONDS REGISTER
+	LD	E,$81			; SECONDS REGISTER
 	CALL	DSRTC_CMD		; SEND THE COMMAND
 	CALL	DSRTC_GET		; READ THE REGISTER
 	CALL	DSRTC_END		; FINISH IT
+	LD	A,E			; VALUE TO A
 	RET
 ;
 #ELSE
@@ -3776,6 +3760,8 @@ HB_TICKS	.FILL	4,0		; 32 BIT TICK COUNTER
 ;
 HB_CPUTYPE	.DB	0		; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
 ;
+RTCVAL		.DB	0		; SHADOW VALUE FOR RTC LATCH PORT
+;
 STR_BANNER	.DB	"RetroBrew HBIOS v", BIOSVER, ", ", TIMESTAMP, "$"
 STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 STR_SWITCH	.DB	"*** Activating CRT Console ***$"

From d22d83f2c8600d4feaab53233e5a6a9ab74531bd Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 19:48:26 +0800
Subject: [PATCH 13/16] Update hbios.asm

Fixup misisng driver
---
 Source/HBIOS/hbios.asm | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 75c6c0e2..619d6bdc 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2741,7 +2741,7 @@ SIZ_MD		.EQU	$ - ORG_MD
 		.ECHO	SIZ_MD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (FDENABLE)
 ORG_FD		.EQU	$
   #INCLUDE "fd.asm"
@@ -2750,7 +2750,7 @@ SIZ_FD		.EQU	$ - ORG_FD
 		.ECHO	SIZ_FD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (RFENABLE)
 ORG_RF	.EQU	$
   #INCLUDE "rf.asm"
@@ -2759,7 +2759,7 @@ SIZ_RF	.EQU	$ - ORG_RF
 		.ECHO	SIZ_RF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (IDEENABLE)
 ORG_IDE		.EQU	$
   #INCLUDE "ide.asm"
@@ -2768,7 +2768,7 @@ SIZ_IDE		.EQU	$ - ORG_IDE
 		.ECHO	SIZ_IDE
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (PPIDEENABLE)
 ORG_PPIDE	.EQU	$
   #INCLUDE "ppide.asm"
@@ -2777,7 +2777,7 @@ SIZ_PPIDE	.EQU	$ - ORG_PPIDE
 		.ECHO	SIZ_PPIDE
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (SDENABLE)
 ORG_SD		.EQU	$
   #INCLUDE "sd.asm"
@@ -2786,7 +2786,7 @@ SIZ_SD		.EQU	$ - ORG_SD
 		.ECHO	SIZ_SD
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (HDSKENABLE)
 ORG_HDSK	.EQU	$
   #INCLUDE "hdsk.asm"
@@ -2795,7 +2795,7 @@ SIZ_HDSK	.EQU	$ - ORG_HDSK
 		.ECHO	SIZ_HDSK
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (TERMENABLE)
 ORG_TERM	.EQU	$
   #INCLUDE "term.asm"
@@ -2822,6 +2822,7 @@ SIZ_AY	.EQU	$ - ORG_AY
 		.ECHO	SIZ_AY
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (PIO_4P | PIO_ZP | PPI_SBC)
 ORG_PIO		.EQU	$
   #INCLUDE "pio.asm"
@@ -2830,7 +2831,15 @@ SIZ_PIO		.EQU	$ - ORG_PIO
 		.ECHO	SIZ_PIO
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
+#IF (UFENABLE)
+ORG_UF	.EQU	$
+  #INCLUDE "usbfifo.asm"
+SIZ_UF	.EQU	$ - ORG_UF
+		.ECHO	"USB-FIFO occupies "
+		.ECHO	SIZ_UF
+		.ECHO	" bytes.\n"
+#ENDIF
 ;
 #DEFINE USEDELAY
 #INCLUDE "util.asm"

From 65bce62b261c7d4019d34977a8a44fd513436c09 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 20:22:12 +0800
Subject: [PATCH 14/16] Resync

---
 Source/HBIOS/plt_sbc.inc | 5 +----
 Source/HBIOS/std.asm     | 8 --------
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index ed472aae..008eac4e 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -20,7 +20,4 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
 PIOZBASE	.EQU	$88		; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
-;
-;
-FIFO_BASE       .EQU	$0C		; ECB USB-FIFO DEFAULT PORT
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
\ No newline at end of file
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index bf4a9323..35dad128 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -269,14 +269,6 @@ IVT_PIO3	.EQU	24
 IVT_SER2	.EQU	26
 IVT_SER3	.EQU	28
 ;
-;
-; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
-; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
-; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, 
-; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
-;
-FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
-;
 #INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))

From 8a560bfbbbfeea58cda464328a595859b7b9dc60 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 20:29:29 +0800
Subject: [PATCH 15/16] Resync

---
 Source/HBIOS/plt_sbc.inc | 5 ++++-
 Source/HBIOS/std.asm     | 8 ++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index 008eac4e..ed472aae 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -20,4 +20,7 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
 PIOZBASE	.EQU	$88		; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
\ No newline at end of file
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
+;
+;
+FIFO_BASE       .EQU	$0C		; ECB USB-FIFO DEFAULT PORT
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 35dad128..bf4a9323 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -269,6 +269,14 @@ IVT_PIO3	.EQU	24
 IVT_SER2	.EQU	26
 IVT_SER3	.EQU	28
 ;
+;
+; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
+; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
+; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, 
+; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
+;
+FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
+;
 #INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))

From a8b0e9848b03706f4c4dd304d31193ce48c883fa Mon Sep 17 00:00:00 2001
From: b1ackmai1er <difficultylevelhigh@gmail.com>
Date: Sun, 4 Aug 2019 20:40:44 +0800
Subject: [PATCH 16/16] Create ReadMe.txt

---
 Doc/ReadMe.txt | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Doc/ReadMe.txt

diff --git a/Doc/ReadMe.txt b/Doc/ReadMe.txt
new file mode 100644
index 00000000..9f596272
--- /dev/null
+++ b/Doc/ReadMe.txt
@@ -0,0 +1,52 @@
+***********************************************************************
+***                                                                 ***
+***                          R o m W B W                            ***
+***                                                                 ***
+***                    Z80/Z180 System Software                     ***
+***                                                                 ***
+***********************************************************************
+
+This directory ("Doc") is part of the RomWBW System Software 
+distribution archive.  It contains documentation for components of 
+the system.
+
+CPM Manual ("CPM Manual.pdf")
+-----------------------------
+
+The original DRI CP/M 2.x Operating System Manual.  This should be 
+considered the primary reference for system operation.  The section 
+on CP/M 2 Alteration can be ignored since this work has already been 
+completed as part of the RomWBW distribution.
+
+DDTZ Manual ("DDTZ.doc")
+------------------------
+
+Manual for the DDTZ v2.7 debug tool included on the ROM drive.
+
+FDisk Manual ("FDisk Manual.pdf")
+---------------------------------
+
+The operational manual for John Coffman's hard disk partitioning 
+program.  This program is included in RomWBW as FDISK80.
+
+RomWBW Architecture ("RomWBW Architecture.pdf")
+-----------------------------------------------
+
+Document describing the architecture of the RomWBW HBIOS.  It 
+includes reference information for the HBIOS calls.
+
+ZCPR Manual ("ZCPR Manual.pdf")
+-------------------------------
+
+ZCPR is the command proccessor portion of Z-System.  This is the 
+manual for ZCPR 1.x as included in RomWBW.  The installation 
+instructions can be ignored since that work has already been 
+completed as part of the RomWBW distribution.
+
+ZSDOS Manual ("ZSDOS Manual.pdf")
+---------------------------------
+
+ZSDOS is the DOS portion of Z-System.  This is the manual fo ZSDOS 
+1.x as included in RomWBW.  The installation instructions can be 
+ignored since that work has already been completed as part of the 
+RomWBW distribution.
\ No newline at end of file