mirror of https://github.com/wwarthen/RomWBW.git
committed by
GitHub
77 changed files with 1593 additions and 605 deletions
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@ -0,0 +1,4 @@ |
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@echo off |
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setlocal |
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|
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setlocal & cd ZRC && call Build || exit /b 1 & endlocal |
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@ -0,0 +1,41 @@ |
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; |
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;================================================================================================== |
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; EASY Z80 STANDARD CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#DEFINE PLATFORM_NAME "TINYZ80" |
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; |
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#include "cfg_ezz80.asm" |
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; |
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CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ |
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; |
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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; |
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EIPCENABLE .SET TRUE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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CTCBASE .SET $10 ; CTC BASE I/O ADDRESS |
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LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) |
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LEDPORT .SET $6E ; STATUS LED PORT ADDRESS |
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SIO0BASE .SET $18 ; SIO 0: REGISTERS BASE ADR |
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IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS |
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@ -0,0 +1,43 @@ |
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; |
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;================================================================================================== |
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; RC2014 Z280 STANDARD CONFIGURATION (EXTERNAL 512K RAM/ROM BANKED MEMORY MODULE) |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#define BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT |
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; |
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#include "cfg_rcz280.asm" |
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; |
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CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ |
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; |
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INTMODE .SET 1 |
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; |
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Z280_MEMWAIT .SET 0 ; Z280: MEMORY WAIT STATES (0-3) |
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Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) |
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; |
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UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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; |
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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@ -0,0 +1,45 @@ |
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; |
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;================================================================================================== |
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; RC2014 Z80 ZRC CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
|||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
|||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#define BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT |
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; |
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#include "cfg_rcz80.asm" |
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; |
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CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ |
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; |
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MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] |
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; |
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UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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; |
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TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
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; |
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FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] |
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; |
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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@ -0,0 +1,220 @@ |
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; |
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;================================================================================================== |
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; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 Z280 (512K RAM/ROM CARD) |
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;================================================================================================== |
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; |
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD |
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY |
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; UNDER THIS DIRECTORY. |
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; |
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS |
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; FOR THE PLATFORM. |
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; |
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#DEFINE PLATFORM_NAME "RC2014" |
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; |
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PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] |
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CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] |
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION |
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) |
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; |
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE |
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; |
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CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ |
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INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 |
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DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
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; |
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
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MEMMGR .EQU MM_Z2 ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER |
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
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; |
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Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3) |
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3) |
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; |
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RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR |
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; |
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT |
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS |
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; |
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT |
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT |
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CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS |
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CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER |
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CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] |
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) |
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CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) |
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CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) |
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CTCOSC .EQU 7372800 ; CTC CLOCK FREQUENCY |
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; |
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EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT |
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DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS |
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DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS |
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; |
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LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) |
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LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS |
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LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
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; |
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DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) |
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; |
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CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
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VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
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ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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; |
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DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
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DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] |
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DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
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; |
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BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
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BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS |
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; |
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INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) |
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; |
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HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT |
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SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
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; |
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DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
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DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) |
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DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP |
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DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG |
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DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG |
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DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP |
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DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG |
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DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG |
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; |
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UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
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UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ |
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UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS |
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UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART |
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UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART |
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UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART |
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UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART |
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UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART |
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; |
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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; |
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ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
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ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT |
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ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) |
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ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR |
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ACIA0CLK .EQU 7372800 ; ACIA 0: OSC FREQ IN HZ |
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ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER |
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ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) |
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ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR |
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ACIA1CLK .EQU 7372800 ; ACIA 1: OSC FREQ IN HZ |
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ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER |
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ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) |
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; |
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SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT |
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] |
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR |
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SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG |
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG |
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] |
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SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR |
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SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG |
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SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG |
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SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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; |
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG |
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; |
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VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
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CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
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NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM) |
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TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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TMSMODE .EQU TMSMODE_RC ; TMS: DRIVER MODE: TMSMODE_[SCG/N8] |
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TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
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VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
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; |
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MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
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MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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; |
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FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] |
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FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) |
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FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
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FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111] |
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FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111] |
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FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
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; |
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RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
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; |
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IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
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IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
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IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS |
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IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O |
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IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O |
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IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER |
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IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER |
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IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
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IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS |
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IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O |
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IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O |
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IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER |
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IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER |
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IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] |
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IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS |
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IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O |
|||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O |
|||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER |
|||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER |
|||
; |
|||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP |
|||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR |
|||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER |
|||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR |
|||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER |
|||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR |
|||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER |
|||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER |
|||
; |
|||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] |
|||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY |
|||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
|||
; |
|||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
; |
|||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
|||
; |
|||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
|||
; |
|||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
|||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
|||
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
|||
; |
|||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
|||
; |
|||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER |
|||
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER |
|||
SN7CLK .EQU 7372800 / 4 ; DEFAULT TO CPUOSC / 4 |
|||
|
|||
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER |
|||
AY_CLK .EQU 7372800 / 4 ; DEFAULT TO CPUOSC / 4 |
|||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] |
|||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
|||
@ -0,0 +1,75 @@ |
|||
; |
|||
; Z80 EIPC (Z84C15) REGISTERS |
|||
; |
|||
EIPC_SCRP .EQU $EE ; SYSTEM CONTROL REGISTER POINTER |
|||
EIPC_SCDP .EQU $EF ; SYSTEM CONTROL DATA PORT |
|||
EIPC_WDTMR .EQU $F0 ; WATCHDOG TIMER MASTER REGISTER |
|||
EIPC_WDTCR .EQU $F1 ; WATCHDOG TIMER COMMAND REGISTER |
|||
EIPC_INTPR .EQU $F4 ; INTERRUPT PRIORITY REGISTER |
|||
; |
|||
; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP) |
|||
; |
|||
EIPC_WCR .EQU $00 ; WAIT STATE CONTROL REGISTER |
|||
EIPC_MWBR .EQU $01 ; MEMORY WAIT BOUNDARY REGISTER |
|||
EIPC_CSBR .EQU $02 ; CHIP SELECT BOUNDARY REGISTER |
|||
EIPC_MCR .EQU $03 ; MISCELLANEOUS CONTROL REGISTER |
|||
; |
|||
; WAIT STATE VALUES (FOR EIPC_WCR) |
|||
; |
|||
EIPC_IO_0WS .EQU $00 ; NO (ZERO) I/O WAIT STATES |
|||
EIPC_IO_2WS .EQU $01 ; 2 I/O WAIT STATES |
|||
EIPC_IO_4WS .EQU $02 ; 4 I/O WAIT STATES |
|||
EIPC_IO_6WS .EQU $03 ; 6 I/O WAIT STATES |
|||
EIPC_MEM_OWS .EQU $00 ; NO (ZERO) MEMORY WAIT STATES |
|||
EIPC_MEM_1WS .EQU $04 ; 1 MEMORY WAIT STATE |
|||
EIPC_MEM_2WS .EQU $08 ; 2 MEMORY WAIT STATES |
|||
EIPC_MEM_3WS .EQU $0C ; 3 MEMORY WAIT STATES |
|||
EIPC_OCF_0WS .EQU $00 ; NO ADDITIONAL WAIT ON OP-CODE FETCH |
|||
EIPC_OCF_1WS .EQU $10 ; +1 WAIT STATE ON OP-CODE FETCH |
|||
EIPC_INT_0WS .EQU $00 ; NO WAIT ON INTERRUPT VECTOR READ |
|||
EIPC_INT_1WS .EQU $20 ; 1 WAIT STATE ON INT. VECTOR READ |
|||
EIPC_CHAIN_0WS .EQU $00 ; 0 WAIT ON INT ACK. / 0 WAIT ON RETI |
|||
EIPC_CHAIN_2WS .EQU $40 ; 2 WAIT ON INT ACK. / 0 WAIT ON RETI |
|||
EIPC_CHAIN_4WS .EQU $80 ; 4 WAIT ON INT ACK. / 2 WAIT ON RETI |
|||
EIPC_CHAIN_6WS .EQU $C0 ; 6 WAIT ON INT ACK. / 4 WAIT ON RETI |
|||
; |
|||
; MISCELLANEOUS CONTROL REGISTER VALUES |
|||
; |
|||
EIPC_CS0_DIS .EQU $00 ; DISABLE /CS0 |
|||
EIPC_CS0_ENA .EQU $01 ; ENABLE /CS0 |
|||
EIPC_CS1_DIS .EQU $00 ; DISABLE /CS1 |
|||
EIPC_CS1_ENA .EQU $02 ; ENABLE /CS1 |
|||
EIPC_32CRC_DIS .EQU $00 ; DISABLE 32-BIT CRC FOR SIO CHANNEL A |
|||
EIPC_32CRC_ENA .EQU $04 ; ENABLE 32-BIT CRC FOR SIO CHANNEL A |
|||
EIPC_RSTOUT_DIS .EQU $08 ; DISABLE RESET OUTPUT |
|||
EIPC_RSTOUT_ENA .EQU $00 ; ENABLE RESET OUTPUT |
|||
EIPC_CLKDIV1 .EQU $10 ; DIVIDE XTAL/CGC CLOCK BY ONE |
|||
EIPC_CLKDIV2 .EQU $00 ; DIVIDE XTAL/CGC CLOCK BY TWO |
|||
; |
|||
; WATCHDOG TIMER MASTER REGISTER VALUES |
|||
; |
|||
EIPC_WDT_CONST .EQU $03 ; MUST SET LOWER THREE BITS TO 011 |
|||
EIPC_HALT_IDLE1 .EQU $00 ; HALT / POWER DOWN MODE - IDLE 1 MODE |
|||
EIPC_HALT_IDLE2 .EQU $08 ; HALT / POWER DOWN MODE - IDLE 2 MODE |
|||
EIPC_HALT_STOP .EQU $10 ; HALT / POWER DOWN MODE - STOP MODE |
|||
EIPC_HALT_RUN .EQU $18 ; HALT / POWER DOWN MODE - RUN MODE |
|||
EIPC_WDT_P2_16 .EQU $00 ; SET WATCHDOG PERIOD TO TOC * 2^16 |
|||
EIPC_WDT_P2_18 .EQU $20 ; SET WATCHDOG PERIOD TO TOC * 2^18 |
|||
EIPC_WDT_P2_20 .EQU $40 ; SET WATCHDOG PERIOD TO TOC * 2^20 |
|||
EIPC_WDT_P2_22 .EQU $60 ; SET WATCHDOG PERIOD TO TOC * 2^22 |
|||
EIPC_WDTE .EQU $80 ; ENABLE WATCHDOG TIMER |
|||
; |
|||
; WATCHDOG TIMER COMMAND REGISTER VALUES |
|||
; |
|||
EIPC_DIS_WDT .EQU $B1 ; DISABLE WATCHDOG TIMER |
|||
EIPC_CLR_WDT .EQU $4E ; CLEAR WATCHDOG TIMER |
|||
EIPC_HLT_MODE .EQU $DB ; CHANGE HALT MODE |
|||
; |
|||
; INTERRUPT PRIORITY REGISTER VALUES |
|||
; |
|||
EIPC_CTC_SIO_PIO .EQU $00 ; PRIORITY HIGH TO LOW: CTC, SIO, PIO |
|||
EIPC_SIO_CTC_PIO .EQU $01 ; PRIORITY HIGH TO LOW: SIO, CTC, PIO |
|||
EIPC_CTC_PIO_SIO .EQU $02 ; PRIORITY HIGH TO LOW: CTC, PIO, SIO |
|||
EIPC_PIO_SIO_CTC .EQU $03 ; PRIORITY HIGH TO LOW: PIO, SIO, CTC |
|||
EIPC_PIC_CTC_SIO .EQU $04 ; PRIORITY HIGH TO LOW: PIO, CTC, SIO |
|||
EIPC_SIO_PIO_CTC .EQU $05 ; PRIORITY HIGH TO LOW: SIO, PIO, CTC |
|||
@ -0,0 +1,13 @@ |
|||
; |
|||
; Z280 REGISTERS |
|||
; |
|||
Z280_MSR .EQU $00 ; MASTER STATUS REG |
|||
Z280_ISR .EQU $16 ; INTERRUPT STATUS REG |
|||
Z280_VPR .EQU $06 ; INT/TRAP VECT PTR REG |
|||
Z280_IOPR .EQU $08 ; I/O PAGE REG |
|||
Z280_BTIR .EQU $FF ; BUS TIMING & INIT REG |
|||
Z280_BTCR .EQU $02 ; BUS TIMING & CONTROL REG |
|||
Z280_SLR .EQU $04 ; STACK LIMIT REG |
|||
Z280_TCR .EQU $10 ; TRAP CONTROL REG |
|||
Z280_CCR .EQU $12 ; CACHE CONTROL REG |
|||
Z280_LAR .EQU $14 ; LOCAL ADDRESS REG |
|||
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@ -0,0 +1,13 @@ |
|||
@echo off |
|||
setlocal |
|||
|
|||
if not exist ..\..\Binary\RCZ80_zrc.rom goto :err |
|||
|
|||
copy /b zrc_cfldr.bin + zrc_ptbl.bin + zrc_fill_1.bin + zrc_mon.bin + zrc_fill_2.bin + ..\..\Binary\RCZ80_zrc.rom + zrc_fill_3.bin ..\..\Binary\hd1024_zrc_prefix.dat |
|||
|
|||
goto :eof |
|||
|
|||
:err |
|||
|
|||
echo *** Can't build ZRC prefix file -- missing "..\..\Binary\RCZ80_zrc.rom" |
|||
exit /b 1 |
|||
@ -0,0 +1,3 @@ |
|||
@echo off |
|||
setlocal |
|||
|
|||
@ -0,0 +1,19 @@ |
|||
HD1024ZRCPREFIX = hd1024_zrc_prefix.dat |
|||
ZRCROM = ../../Binary/RCZ80_zrc.rom |
|||
|
|||
OBJECTS := |
|||
|
|||
ifneq ($(wildcard $(ZRCROM)),) |
|||
OBJECTS += $(HD1024ZRCPREFIX) |
|||
endif |
|||
|
|||
DEST=../../Binary |
|||
|
|||
TOOLS = ../../Tools |
|||
|
|||
include $(TOOLS)/Makefile.inc |
|||
|
|||
DIFFPATH = $(DIFFTO)/Binary |
|||
|
|||
$(HD1024ZRCPREFIX): |
|||
cat zrc_cfldr.bin zrc_ptbl.bin zrc_fill_1.bin zrc_mon.bin zrc_fill_2.bin $(ZRCROM) zrc_fill_3.bin >$@ |
|||
@ -0,0 +1,16 @@ |
|||
CF Boot Loader: Sector 0 (bytes 0-255) |
|||
RomWBW Partition Table: Sector 0 (bytes 256-511) |
|||
ZRC Monitor: Sectors 0xF8-0xFF (bytes 0x1F000-0x1FFFF) |
|||
RomWBW: Sectors 0x120-0x51F (bytes 0x24000-0xA3FFF) |
|||
Start of Slices (0x1E partition): Sector 0x800 (byte 0x100000) |
|||
|
|||
Start Length Description |
|||
------- ------- --------------------------- |
|||
0x00000 0x00100 CF Boot Loader |
|||
0x00100 0x00100 RomWBW Partition Table |
|||
0x00200 0x1EE00 Filler |
|||
0x1F000 0x01000 ZRC Monitor |
|||
0x20000 0x04000 Filler |
|||
0x24000 0x80000 RomWBW |
|||
0xA4000 0x5C000 Filler |
|||
0x100000: Start of slices (partition 0x1E) |
|||
Binary file not shown.
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Binary file not shown.
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Loading…
Reference in new issue