diff --git a/Source/HBIOS/ez80uart.asm b/Source/HBIOS/ez80uart.asm
index bcc72965..28af82f7 100644
--- a/Source/HBIOS/ez80uart.asm
+++ b/Source/HBIOS/ez80uart.asm
@@ -27,24 +27,16 @@ LSR_DR		.EQU	$01
 #DEFINE OUT0_H(p)	.DB	$ED,$21,p
 #DEFINE OUT0_L(p)	.DB	$ED,$29,p
 
-; call.IL $01FFxx WHERE xx IS r*4
-#DEFINE FIRMWARE_FN(r)	.DB	$5B,$CD \	.DW	($FF00+(r*4))	\ .DB $01
-
 EZUART_PREINIT:
-	FIRMWARE_FN(0)
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
 	CALL	CIO_ADDENT
 	LD	(EZUART_ID), A
 
-	FIRMWARE_FN(0)
-
 	XOR	A
 	RET
 
 EZUART_INIT:
-	FIRMWARE_FN(1)
-
 	XOR	A
 	RET
 
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 83fe6cd3..9983e7d1 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -354,7 +354,9 @@ RTCDEF	.SET	RTCDEF | %00001000	; INITIAL SPEED LOW
 ; EMIT PREFIX REQUIRED BY EZ80 TO ENSURE CORRECT 16 BIT IO OPERATION
 ;
 #IF (CPUFAM == CPU_EZ80)
-  #DEFINE EZ80_IO	.DB $49 $CF
+  #DEFINE EZ80_IO	.DB 	$49, $CF	; RST.L $08
+  #DEFINE EZ80_FN 	.DB	$49, $D7	; RST.L $10
+  #DEFINE EZ80_BNKSEL 	.DB	$49, $DF	; RST.L $18
 #ELSE
   #DEFINE EZ80_IO
 #ENDIF
@@ -620,6 +622,12 @@ HBX_ROM:
 #ENDIF
 ;
 #IF (MEMMGR == MM_Z2)
+
+#IF (CPUFAM == CPU_EZ80)
+	EZ80_BNKSEL
+	RET
+#ELSE
+
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
@@ -641,6 +649,7 @@ HBX_ROM:
   #ENDIF
 	RET				; DONE
 #ENDIF
+#ENDIF
 ;
 #IF (MEMMGR == MM_N8)
 	BIT	7,A			; TEST BIT 7 FOR RAM VS. ROM
@@ -1368,7 +1377,9 @@ HB_START:
 HB_RESTART:
 ;
 	DI				; NO INTERRUPTS
+#IF (CPUFAM != CPU_EZ80)
 	IM	1			; INTERRUPT MODE 1
+#ENDIF
 ;
 #IFDEF APPBOOT
 ;
@@ -1419,6 +1430,33 @@ BOOTWAIT:
 	LD	A,RPH_DEFACR		; ENSURE RPH ACR
 	OUT0	(RPH_ACR),A		; ... REGISTER IS INITIALIZED
 #ENDIF
+
+
+#IF (CPUFAM == CPU_EZ80)
+
+; PROVIDE THE EZ80 FIRMWARE WITH PLATFORM CONFIGUATIONS
+
+	XOR	A			; FUNCTION CODE TO INIT FIRMWARE
+	LD	HL, PLT_DESCR
+
+	EZ80_FN				; PROVIDE FIRMWARE DETAILS OF BUILD CONFIGURATION
+	JR	PLT_DESCR_END
+
+PLT_DESCR:
+	.DB	PLT_RCZ80
+	.DB	MEMMGR
+	.DW	RAMSIZE
+	.DW	ROMSIZE
+	.DB	MPGSEL_0
+	.DB	MPGSEL_1
+	.DB	MPGSEL_2
+	.DB	MPGSEL_3
+	.DB	MPGENA
+
+PLT_DESCR_END:
+
+#ENDIF
+
 ;
 ; INITIALIZE DIAGNOSTIC AND/OR FRONT PANEL LED(S) TO INDICATE THE
 ; SYSTEM IS ALIVE. WE HAVE NO RAM AT THIS TIME, SO WE CANNOT USE
@@ -1432,7 +1470,7 @@ BOOTWAIT:
 	LD	A,DIAG_01
   #ENDIF
 ;
-	EZ80_IO
+	EZ80_IO()
 	OUT	(FPLED_IO),A
 
 #ENDIF
@@ -2420,6 +2458,7 @@ HB_CPU3:
 ; OPERATING INTERRUPT MODE.  NOTE THAT INTERRUPTS REMAIN
 ; DISABLED AT THIS POINT.
 ;
+#IF (CPUFAM != CPU_EZ80)
 #IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180)))
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
@@ -2435,6 +2474,7 @@ HB_CPU3:
 	IM	2			; SWITCH TO INT MODE 2
   #ENDIF
 #ENDIF
+#ENDIF
 ;
 #IF (MEMMGR == MM_Z280)
 	; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE
@@ -2445,6 +2485,7 @@ HB_CPU3:
 	LDCTL	(C),HL
 #ENDIF
 ;
+#IF (CPUFAM != CPU_EZ80)
 #IF (INTMODE == 3)
 ;
 	; SETUP Z280 INT A FOR VECTORED INTERRUPTS
@@ -2456,6 +2497,7 @@ HB_CPU3:
 	IM	3
 ;
 #ENDIF
+#ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
 ; SYSTEM TIMER INITIALIZATION