diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index eb4deab6..af1b474c 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -8,7 +8,7 @@
 CPUOSC		.EQU	10000000	; CPU OSC FREQ
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
-INTMODE		.EQU	1		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+INTMODE		.EQU	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 753f6755..f44195ca 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -7,4 +7,6 @@
 ;
 #INCLUDE "cfg_zeta.asm"			; USE ZETA CONFIG TO START
 ;
+INTMODE		.SET	2		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+;
 FDMODE		.SET	FDMODE_ZETA2	; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 85244ce9..015fe5c4 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -983,6 +983,84 @@ PSCNX	.EQU	$ + 1
   #ENDIF
 ;
 #ENDIF
+;
+#IF (PLATFORM == PLT_ZETA2)
+;
+; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
+; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
+; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
+; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
+;
+  #IF (INTMODE == 2)
+	LD	HL,INT_TIMER
+	LD	(HBX_IVT),HL
+;
+	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
+	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
+	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
+	; IVT CORRESPOND TO CTC CHANNELS A-D
+	LD	A,0
+	OUT	(CTCBASE),A		; SETUP CTC BASE INT VECTOR
+;
+	; CONFIGURE CHANNEL A FOR 50HZ PERIODIC INTERRUPTS
+	; INT FREQ IS CTC CLK / PRESCALER / TIME CONSTANT
+	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
+	LD	A,%10110111		; CTC CONTROL WORD VALUE
+		;  |||||||+-- 0=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 256
+		;  |+-------- 0=TIMER MODE
+		;  +--------- 1=ENABLE INTERRUPTS
+	OUT	(CTCA),A		; SETUP CTC CHANNEL A
+	LD	A,72			; TIMER CONSTANT FOR 50HZ
+	OUT	(CTCA),A		; SETUP CTC CHANNEL A TIMER CONSTANT
+  #ENDIF
+;
+#ENDIF
+;
+#IF (PLATFORM == PLT_EZZ80)
+;
+; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
+; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
+; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
+; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
+;
+  #IF (INTMODE == 2)
+	LD	HL,INT_TIMER
+	LD	(HBX_IVT + IVT_TIM0),HL
+;
+	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
+	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
+	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
+	; IVT CORRESPOND TO CTC CHANNELS A-D
+	LD	A,0
+	OUT	(CTCBASE),A		; SETUP CTC BASE INT VECTOR
+;
+	; CONFIGURE CHANNEL C FOR 50HZ PERIODIC INTERRUPTS
+	; INT FREQ IS CTC CLK / PRESCALER / TIME CONSTANT
+	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
+	LD	A,%10110111		; CTC CONTROL WORD VALUE
+		;  |||||||+-- 0=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 256
+		;  |+-------- 0=TIMER MODE
+		;  +--------- 1=ENABLE INTERRUPTS
+	OUT	(CTCC),A		; SETUP CTC CHANNEL C
+	LD	A,72			; TIMER CONSTANT FOR 50HZ
+	OUT	(CTCC),A		; SETUP CTC CHANNEL C TIMER CONSTANT
+  #ENDIF
+;
+#ENDIF
+
+
+
+
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
 ;
@@ -2028,6 +2106,11 @@ HB_TIMINT2:
 	IN0	A,(Z180_TCR)
 	IN0	A,(Z180_TMDR0L)
 #ENDIF
+;
+#IF (PLATFORM == PLT_EZZ80)
+	; PULSE WATCHDOG
+	OUT	(WDOG),A		; VALUE IS IRRELEVANT
+#ENDIF
 ;
 	OR	$FF			; NZ SET TO INDICATE INT HANDLED
 	RET
diff --git a/Source/HBIOS/plt_ezz80.inc b/Source/HBIOS/plt_ezz80.inc
index f848803a..03bbd3ab 100644
--- a/Source/HBIOS/plt_ezz80.inc
+++ b/Source/HBIOS/plt_ezz80.inc
@@ -9,3 +9,11 @@ MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
 SIOBASE 	.EQU 	$80	; RC OR SMB SIO DEFAULT
+;
+WDOG		.EQU	$6F	; WATCHDOG
+;
+CTCBASE		.EQU	$88	; CTC BASE I/O ADDRESS
+CTCA		.EQU	CTCBASE + 0	; CTC CHANNEL A
+CTCB		.EQU	CTCBASE + 1	; CTC CHANNEL B
+CTCC		.EQU	CTCBASE + 2	; CTC CHANNEL C
+CTCD		.EQU	CTCBASE + 3	; CTC CHANNEL D
diff --git a/Source/HBIOS/plt_zeta.inc b/Source/HBIOS/plt_zeta.inc
new file mode 100644
index 00000000..bb9210bd
--- /dev/null
+++ b/Source/HBIOS/plt_zeta.inc
@@ -0,0 +1,14 @@
+;
+; ZETA HARDWARE DEFINITIONS
+;
+SBC_BASE	.EQU	$60		; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
+;
+; BIT 7 OF MPCL_ROM SELECTS ROM/RAM (0=ROM, 1=RAM)
+MPCL_RAM	.EQU 	SBC_BASE + $18	; MEMORY PAGER CONFIG LATCH - RAM (WRITE ONLY)
+MPCL_ROM	.EQU 	SBC_BASE + $1C	; MEMORY PAGER CONFIG LATCH - ROM (WRITE ONLY)
+;
+RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
+PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
+SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
+PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
diff --git a/Source/HBIOS/plt_zeta2.inc b/Source/HBIOS/plt_zeta2.inc
new file mode 100644
index 00000000..1613a456
--- /dev/null
+++ b/Source/HBIOS/plt_zeta2.inc
@@ -0,0 +1,22 @@
+;
+; ZETA 2 HARDWARE DEFINITIONS
+;
+SBC_BASE	.EQU	$60		; I/O BASE ADDRESS FOR ONBOARD PERIPHERALS
+;
+MPGSEL_0	.EQU	SBC_BASE + $18	; BANK_0 PAGE SELECT REGISTER (WRITE ONLY)
+MPGSEL_1	.EQU	SBC_BASE + $19	; BANK_1 PAGE SELECT REGISTER (WRITE ONLY)
+MPGSEL_2	.EQU	SBC_BASE + $1A	; BANK_2 PAGE SELECT REGISTER (WRITE ONLY)
+MPGSEL_3	.EQU	SBC_BASE + $1B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
+MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
+;
+RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
+PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
+SIOBASE		.EQU	$B0		; ZILOG PERIPHERALS DEFAULT
+PIOZBASE	.EQU	SIOBASE+8	; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
+;
+CTCBASE		.EQU	$20	; CTC BASE I/O ADDRESS
+CTCA		.EQU	CTCBASE + 0	; CTC CHANNEL A
+CTCB		.EQU	CTCBASE + 1	; CTC CHANNEL B
+CTCC		.EQU	CTCBASE + 2	; CTC CHANNEL C
+CTCD		.EQU	CTCBASE + 3	; CTC CHANNEL D
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 2f0ef922..ca998c8f 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -179,7 +179,7 @@ SIOA_INT00:
 	JR	Z,SIOA_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(SIOA_CNT),A		; AND SAVE IT
-	CP	SIOA_BUFSZ - 5		; BUFFER GETTING FULL?
+	CP	SIOA_BUFSZ / 2		; BUFFER GETTING FULL?
 	JR	NZ,SIOA_INT0		; IF NOT, BYPASS CLEARING RTS
 	LD	A,5			; RTS IS IN WR5
 	OUT	(SIOA_CMD),A		; ADDRESS WR5
@@ -225,7 +225,7 @@ SIOB_INT00:
 	JR	Z,SIOB_INT2		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(SIOB_CNT),A		; AND SAVE IT
-	CP	SIOB_BUFSZ - 5		; BUFFER GETTING FULL?
+	CP	SIOB_BUFSZ / 2		; BUFFER GETTING FULL?
 	JR	NZ,SIOB_INT0		; IF NOT, BYPASS CLEARING RTS
 	LD	A,5			; RTS IS IN WR5
 	OUT	(SIOB_CMD),A		; ADDRESS WR5
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index a26c0893..389c2b06 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -283,10 +283,18 @@ IVT_PIO3	.EQU	24
 ;
 ; INCLUDE PLATFORM SPECIFIC HARDWARE DEFINITIONS
 ;
-#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
+#IF (PLATFORM == PLT_SBC)
 #INCLUDE "plt_sbc.inc"
 #ENDIF
 ;
+#IF (PLATFORM == PLT_ZETA)
+#INCLUDE "plt_zeta.inc"
+#ENDIF
+;
+#IF (PLATFORM == PLT_ZETA2)
+#INCLUDE "plt_zeta2.inc"
+#ENDIF
+;
 #IF (PLATFORM == PLT_N8)
 #INCLUDE "plt_n8.inc"
 #ENDIF