Merge branch 'master' of https://github.com/b1ackmai1er/RomWBW

Doc/ChangeLog.txt

@@ -1,3 +1,9 @@
+Version 2.9.2
+-------------
+- PMS: Fixed DS1210-related issue resulting in "Invalid BIOS" errors
+- SCC: Support for SC126 motherboard
+- WBW: Enable Auto-CTS/DCD in SIO driver for pacing output data
+
 Version 2.9.1
 -------------
 - E?B: Added support for RC2014 RTC

ReadMe.txt

@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.1-pre.16, 2019-05-25
+Version 2.9.2-pre, 2019-06-21
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
@@ -145,7 +145,7 @@ few things that UNA does not support:
 
     - Floppy Drives
     - Video/Keyboard/Terminal Emulation
-    - Zeta 1 and N8 systems
+    - Zeta 1, N8, and RC2014 systems
     - Some older support boards
     - RC2014 systems
     - Easy Z80 systems
@@ -216,7 +216,7 @@ Current inclusions are:
 	Monitor     - Z80 debug monitor with hexload capability.
 	Forth       - Brad Rodriguez's ANS compatible Forth.
 	Basic	    - Nascom 8K BASIC.
-	Tasty BASIC	- Dimitri Theulings Tiny BASIC implementation.
+	Tasty BASIC - Dimitri Theulings Tiny BASIC implementation.
 	
 	Note: To exit type B in Monitor and BYE in other applications.
 	

Source/Apps/RTC.asm

@@ -19,6 +19,8 @@
 ;
 ;[2018/11/8] v1.2 PMS Add boot option. Code optimization.
 ;
+;[2019/06/21] v1.3 Finalized RC2014 Z180 support.
+;
 ;
 ; Constants
 ;
@@ -30,7 +32,9 @@ mask_rst	.EQU	%00010000	; De-activate RTC reset line
 PORT_SBC	.EQU	$70		; RTC port for SBC/ZETA
 PORT_N8		.EQU	$88		; RTC port for N8
 PORT_MK4	.EQU	$8A		; RTC port for MK4
-PORT_RC		.EQU	$C0		; RTC port for RC2014
+PORT_RCZ80	.EQU	$C0		; RTC port for RC2014
+PORT_RCZ180	.EQU	$0C		; RTC port for RC2014
+PORT_EZZ80	.EQU	$C0		; RTC port for EZZ80 (actually does not have one!!!)
 
 BDOS		.EQU	5		; BDOS invocation vector
 
@@ -1066,14 +1070,18 @@ HINIT:
 	LD	DE,PLT_MK4
 	CP	$05		; Mark IV
 	JR	Z,RTC_INIT2
-	LD	C,PORT_RC
-	LD	DE,PLT_RC
-	CP	$07		; RC2014
+	LD	C,PORT_RCZ80
+	LD	DE,PLT_RCZ80
+	CP	$07		; RC2014 w/ Z80
 	JR	Z,RTC_INIT2
+	LD	C,PORT_RCZ180
+	LD	DE,PLT_RCZ180
 	CP	$08		; RC2014 w/ Z180
 	JR	Z,RTC_INIT2
-	CP	$09		; Easy Z80
-	JR	Z,RTC_INIT2
+	;LD	C,PORT_EZZ80
+	;LD	DE,PLT_EZZ80
+	;CP	$09		; Easy Z80
+	;JR	Z,RTC_INIT2
 ;
 	; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
@@ -1288,8 +1296,8 @@ RTC_TOP_LOOP_DELAY:
 	JP	RTC_TOP_LOOP_1
 	
 RTC_TOP_LOOP_BOOT:
-	LD		A,BID_BOOT		; BOOT BANK
-	LD		HL,0			; ADDRESS ZERO
+	LD	A,BID_BOOT		; BOOT BANK
+	LD	HL,0			; ADDRESS ZERO
 	CALL	HB_BNKCALL		; DOES NOT RETURN
 
 RTC_TOP_LOOP_CHARGE:
@@ -1537,7 +1545,7 @@ TESTING_BIT_DELAY_OVER:
 
 RTC_HELP_MSG:
 	.DB	0Ah, 0Dh		; line feed and carriage return
-	.TEXT	"RTC: Version 1.2"
+	.TEXT	"RTC: Version 1.3"
 	.DB	0Ah, 0Dh		; line feed and carriage return
 	.TEXT	"Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot H)elp"
 	.DB	0Ah, 0Dh		; line feed and carriage return
@@ -1650,15 +1658,17 @@ RTC_GET_BUFFER:
 	.DB	0Ah, 0Dh		; line feed and carriage return
 	.DB	"$"			; line terminator
 
-BIOERR	.TEXT	"\r\nUnknown BIOS, aborting...\r\n$"
-PLTERR	.TEXT	"\r\n\r\nUnknown hardware platform, aborting...\r\n$"
-UBERR	.TEXT	"\r\nUNA UBIOS is not currently supported, aborting...\r\n$"
-HBTAG	.TEXT	"RomWBW HBIOS$"
-UBTAG	.TEXT	"UNA UBIOS"
-PLT_SBC	.TEXT	", SBC/Zeta RTC Latch Port 0x70\r\n$"
-PLT_N8	.TEXT	", N8 RTC Latch Port 0x88\r\n$"
-PLT_MK4	.TEXT	", Mark 4 RTC Latch Port 0x8A\r\n$"
-PLT_RC	.TEXT	", RC2014 RTC Module Latch Port 0xC0\r\n$"
+BIOERR		.TEXT	"\r\nUnknown BIOS, aborting...\r\n$"
+PLTERR		.TEXT	"\r\n\r\nUnknown/unsupported hardware platform, aborting...\r\n$"
+UBERR		.TEXT	"\r\nUNA UBIOS is not currently supported, aborting...\r\n$"
+HBTAG		.TEXT	"RomWBW HBIOS$"
+UBTAG		.TEXT	"UNA UBIOS"
+PLT_SBC		.TEXT	", SBC/Zeta RTC Latch Port 0x70\r\n$"
+PLT_N8		.TEXT	", N8 RTC Latch Port 0x88\r\n$"
+PLT_MK4		.TEXT	", Mark 4 RTC Latch Port 0x8A\r\n$"
+PLT_RCZ80	.TEXT	", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
+PLT_RCZ180	.TEXT	", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
+PLT_EZZ80	.TEXT	", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm

Source/CBIOS/ver.inc

@@ -1,5 +1,5 @@
 #DEFINE	RMJ	2
 #DEFINE	RMN	9
-#DEFINE	RUP	1
+#DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.16"
+#DEFINE BIOSVER	"2.9.2-pre.0"

Source/HBIOS/Config/RCZ180_sc126.asm

@@ -0,0 +1,32 @@
+;
+;==================================================================================================
+;   RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER
+;==================================================================================================
+;
+#include "cfg_rcz180.asm"
+;
+Z180_CLKDIV	.SET	1		; 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; MEMORY WAIT STATES TO INSERT (0-3)
+Z180_IOWAIT	.SET	1		; IO WAIT STATES TO INSERT (0-3)
+;
+CPUOSC		.SET	18432000	; CPU OSC FREQ
+DEFSERCFG	.SET	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	TRUE		; TRUE FOR Z180 ASCI SUPPORT
+SIOENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT ZILOG SIO/2 
+SIOMODE		.SET	SIOMODE_RC	; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
+ACIAENABLE	.SET	FALSE		; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
+;
+FDENABLE	.SET	FALSE		; TRUE FOR FLOPPY SUPPORT
+FDMODE		.SET	FDMODE_RCWDC	; FDMODE_RCSMC, FDMODE_RCWDC
+;
+IDEENABLE	.SET	TRUE		; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
+IDEMODE		.SET	IDEMODE_RC	; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
+PPIDEENABLE	.SET	FALSE		; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
+;
+DSRTCENABLE	.SET	TRUE		; DS-1302 CLOCK DRIVER
+;
+SDENABLE	.SET	TRUE		; TRUE FOR SD SUPPORT
+SDMODE		.SET	SDMODE_SC126	; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
+SDTRACE		.SET	2		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+SDCSIOFAST	.SET	TRUE		; TABLE-DRIVEN BIT INVERTER

Source/HBIOS/cfg_rcz180.asm

@@ -27,6 +27,11 @@ UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TR
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
 SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
+SIODEBUG	.EQU	FALSE		;PS
+DEFSIOACFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+DEFSIOBCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+DEFSIOCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT

Source/HBIOS/dsky.asm

@@ -262,11 +262,11 @@ DSKY_HEXOUT1:
 DSKY_SHOWHEX:
 	LD	A,$D0			; 7218 -> (DATA COMING, HEXA DECODE)
 	JR	DSKY_SHOW
-
+;
 DSKY_SHOWSEG:
 	LD	A,$F0			; 7218 -> (DATA COMING, NO DECODE)
 	JR	DSKY_SHOW
-
+;
 DSKY_SHOW:
 	PUSH	AF			; SAVE 7218 CONTROL BITS
 	LD	A,82H			; SETUP PPI
@@ -290,15 +290,37 @@ DSKY_STROBE:	; DATA STROBE
 DSKY_STROBE0:
 	OUT	(PPIC),A		; OUT TO PORTC
 	CALL	DLY2			; DELAY
-DSKY_COFF
+DSKY_COFF:
 	LD	A,40H | 30H		; QUIESCE
 	OUT	(PPIC),A		; OUT TO PORTC
 ;	CALL	DSKY_DELAY		; WAIT
 	RET
 ;
+; CODES FOR NUMERICS
+; HIGH BIT ALWAYS SET TO SUPPRESS DECIMAL POINT
+; CLEAR HIGH BIT TO SHOW DECIMAL POINT
+;
+DSKY_NUMS:
+	.DB	$FB	; 0
+	.DB	$B0	; 1
+	.DB	$ED	; 2
+	.DB	$F5	; 3
+	.DB	$B6	; 4
+	.DB	$D7	; 5
+	.DB	$DF	; 6
+	.DB	$F0	; 7
+	.DB	$FF	; 8
+	.DB	$F7	; 9
+	.DB	$FE	; A
+	.DB	$9F	; B
+	.DB	$CB	; C
+	.DB	$BD	; D
+	.DB	$CF	; E
+	.DB	$CE	; F
+;
 ; SEG DISPLAY WORKING STORAGE
 ;
-DSKY_BUF:	.FILL	8,0
+DSKY_BUF	.FILL	8,0
 DSKY_BUFLEN	.EQU	$ - DSKY_BUF
 DSKY_HEXBUF	.FILL	4,0
 DSKY_HEXBUFLEN	.EQU	$ - DSKY_HEXBUF

Source/HBIOS/hbios.asm

@@ -144,7 +144,7 @@ ROM_SIG:
 ;
 NAME	.DB	"ROMWBW v", BIOSVER, ", ", TIMESTAMP, 0
 AUTH	.DB	"WBW",0
-DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright (C) 2015, Wayne Warthen, GNU GPL v3", 0
+DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright (C) 2019, Wayne Warthen, GNU GPL v3", 0
 ;
 	.FILL	($100 - $),$FF		; PAD REMAINDER OF PAGE ZERO
 ;
@@ -866,9 +866,11 @@ HB_START:
 ;	LD	HL,(HBX_IMG)
 ;	LD	(X2),HL
 
-	LD	HL,HBX_IMG
-	LD	DE,HBX_LOC
-	LD	BC,HBX_SIZ
+	LD	DE,HBX_LOC		; IF A DS1210 POWER CONTROLLER IS INSTALLED AND BATTERY BACKUP IS NOT
+	LD	A,(DE)			; INSTALLED OR IS LESS THAN 2V THEN THE DS1210 WILL BLOCK THE SECOND RAM
+	LD	A,(DE)			; ACCESS. PERFORM TWO DUMMY READS TO RAM TO ENSURE WE BYPASS THIS FEATURE
+	LD	HL,HBX_IMG		; SO THAT THE ROM ID BYTES ARE COPIED CORRECTLY AND CP/M APPLICATIONS 
+	LD	BC,HBX_SIZ		; START CORRECTLY WHEN THEY CHECK THE ROM ID VERSION BYTES.
 	LDIR
 
 ;	LD	HL,(HBX_IMG)
@@ -942,6 +944,17 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	DIAG(%00001111)
 ;
 #IF (DSKYENABLE)
+	LD	HL,MSG_HBVER +  5
+	LD	A,(DSKY_NUMS + RMJ)
+	AND	$7F
+	LD	(HL),A
+	INC	HL
+	LD	A,(DSKY_NUMS + RMN)
+	AND	$7F
+	LD	(HL),A
+	INC	HL
+	LD	A,(DSKY_NUMS + RUP)
+	LD	(HL),A
 	LD	HL,MSG_HBVER
 	CALL	DSKY_SHOWSEG
 #ENDIF
@@ -3720,8 +3733,9 @@ STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 STR_SWITCH	.DB	"*** Activating CRT Console ***$"
 STR_BADINT	.DB	"\r\n*** BAD INT ***\r\n$"
 ;
-#IF (DSKYENABLE)
-MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$D7,$6D,$77,$B0	; "HBIOS291"
+#IF (DSKYENABLE)	;	'H','B','I','O',' ','2','9','1'
+;MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$6D,$77,$B0	; "HBIO 291"
+MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$80,$80,$80	; "HBIO    "
 #ENDIF
 ;
 HB_CURSEC	.DB	0		; CURRENT SECOND (TEMP)

Source/HBIOS/plt_rcz180.inc

@@ -12,4 +12,6 @@ MPGENA		.EQU	$7C		; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	$0C		; ADDRESS OF RTC LATCH AND INPUT PORT
 ;
 Z180_BASE	.EQU	$C0		; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
+SIOBASE 	.EQU 	$80 		; RC OR SMB SIO DEFAULT
+;
 #INCLUDE "z180.inc"

Source/HBIOS/plt_rcz80.inc

@@ -8,4 +8,4 @@ MPGSEL_3	.EQU	$7B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
 MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
-SIOBASE 	.EQU 	$80 ; RC OR SMB SIO DEFAULT
+SIOBASE 	.EQU 	$80 	; RC OR SMB SIO DEFAULT

Source/HBIOS/sd.asm

@@ -158,6 +158,15 @@ SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_SC126)		; N8-2312
+SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRREG	.EQU	RTC		; USES RTC LATCHES FOR OPERATION
+SD_OPRDEF	.EQU	%00001101	; QUIESCENT STATE
+SD_CS		.EQU	%00000100	; RTC:2 IS SELECT
+SD_CNTR		.EQU	Z180_CNTR
+SD_TRDR		.EQU	Z180_TRDR
+#ENDIF
+;
 ; SD CARD COMMANDS
 ;
 SD_CMD_GO_IDLE_STATE	.EQU	$40 + 0		; $40, CMD0 -> R1
@@ -315,6 +324,22 @@ SD_INIT:
 	LD	A,SD_TRDR
 	CALL	PRTHEXBYTE
 #ENDIF
+;
+#IF (SDMODE == SDMODE_SC126)
+	PRTS(" MODE=SC126$")
+  #IF (SDCSIOFAST)
+	PRTS(" FAST$")
+  #ENDIF
+	PRTS(" OPR=0x$")
+	LD	A,SD_OPRREG
+	CALL	PRTHEXBYTE
+	PRTS(" CNTR=0x$")
+	LD	A,SD_CNTR
+	CALL	PRTHEXBYTE
+	PRTS(" TRDR=0x$")
+	LD	A,SD_TRDR
+	CALL	PRTHEXBYTE
+#ENDIF
 ;
 	CALL	SD_PROBE		; CHECK FOR HARDWARE
 	JR	Z,SD_INIT00		; CONTINUE IF PRESENT
@@ -847,7 +872,7 @@ SD_INITCARD5:
 	CALL	SD_EXECCMDND		; EXEC COMMAND W/ NO DATA
 	RET	NZ			; ABORT ON ERROR
 
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
 	; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION
 	; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
@@ -1301,7 +1326,7 @@ SD_SETUP:
 	OUT	(SD_OPRREG),A
 #ENDIF
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
 	; CSIO SETUP
 ;	LD	A,2			; 18MHz/20 <= 400kHz
 	LD	A,6			; ???
@@ -1372,7 +1397,7 @@ SD_CHKWP:
 ;
 SD_SELECT:
 	LD	A,(SD_OPRVAL)
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART))
+#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
 	AND	~SD_CS			; SET SD_CS (CHIP SELECT)
 #ELSE
 	OR	SD_CS			; SET SD_CS (CHIP SELECT)
@@ -1385,7 +1410,7 @@ SD_SELECT:
 ;
 SD_DESELECT:
 	LD	A,(SD_OPRVAL)
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART))
+#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
 	OR	SD_CS			; RESET SD_CS (CHIP SELECT)
 #ELSE
 	AND	~SD_CS			; RESET SD_CS (CHIP SELECT)
@@ -1394,7 +1419,7 @@ SD_DESELECT:
 	OUT	(SD_OPRREG),A
 	RET
 ;
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
 ;
 ; CSIO WAIT FOR TRANSMIT READY (TX REGSITER EMPTY)
 ;
@@ -1417,7 +1442,7 @@ SD_WAITRX:
 ; SEND ONE BYTE
 ;
 SD_PUT:
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS, RESULT IN C
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	OUT0	(SD_TRDR),C		; PUT BYTE IN BUFFER
@@ -1449,7 +1474,7 @@ SD_PUT1:
 ; RECEIVE ONE BYTE
 ;
 SD_GET:
-#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
+#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
 	CALL	SD_WAITTX		; MAKE SURE WE ARE DONE SENDING
 	IN0	A,(Z180_CNTR)		; GET CSIO STATUS
 	SET	5,A			; START RECEIVER
@@ -1748,7 +1773,7 @@ SD_DSKBUF	.DW	0		; ADR OF ACTIVE DISK BUFFER
 ; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
 ;
 MIRROR:
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
 	LD	BC,MIRTAB		; 256 BYTE MIRROR TABLE
 	ADD	A,C			; ADD OFFSET
 	LD	C,A
@@ -1769,7 +1794,7 @@ MIRROR1:
 ;
 ; LOOKUP TABLE TO MIRROR BITS IN A BYTE
 ;
-#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4)) & SDCSIOFAST)
+#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
 
 MIRTAB	.DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
 	.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H

Source/HBIOS/sio.asm

@@ -562,9 +562,9 @@ BROK:
 ;
 ; SET RECEIVE DATA BITS WR3 
 ;	
-	LD	A,D
-	AND	$C0
-	OR	$01
+	LD	A,D			; DATA BITS
+	AND	$C0			; CLEAR OTHER BITS
+	OR	$21			; CTS/DCD AUTO, RX ENABLE
 	
 	LD	BC,SIO_INITVALS+9
 	LD	(BC),A	
@@ -625,7 +625,7 @@ SIO_INITVALS:
 	.DB	$01, $18		; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS
 #ENDIF
 	.DB	$02, IVT_SER0		; WR2: INTERRUPT VECTOR OFFSET
-	.DB	$03, $C1		; WR3: 8 BIT RCV, RX ENABLE
+	.DB	$03, $E1		; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE
 	.DB	$05, $EA		; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
 SIO_INITLEN	.EQU	$ - SIO_INITVALS
 ;

Source/HBIOS/std.asm

@@ -1,4 +1,5 @@
 ; The purpose of this file is to define generic symbols and to include
+; The purpose of this file is to define generic symbols and to include
 ; the appropriate std-*.inc file to bring in platform specifics.
 
 ; There are several classes of systems supported by SBC.
@@ -145,6 +146,7 @@ SDMODE_PPI	.EQU	4		; PPISD MINI BOARD
 SDMODE_UART	.EQU	5		; SD INTERFACE VIA UART
 SDMODE_DSD	.EQU	6		; DUAL SD
 SDMODE_MK4	.EQU	7		; MARK IV
+SDMODE_SC126	.EQU	8		; SC126
 ;
 ; SERIAL DEVICE CONFIGURATION CONSTANTS
 ;

Source/HBIOS/ver.inc

@@ -1,5 +1,5 @@
 #DEFINE	RMJ	2
 #DEFINE	RMN	9
-#DEFINE	RUP	1
+#DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.16"
+#DEFINE BIOSVER	"2.9.2-pre.0"