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Merge pull request #180 from wwarthen/dev 

Dev
pull/198/head
b1ackmai1er 5 years ago
committed by GitHub
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5903ed606b 41061179b5
commit
e18c2bb4fc
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
41 changed files with 591 additions and 233 deletions
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  1. 1
      .gitignore
  2. 8
      Binary/RomList.txt
  3. 1
      Doc/ChangeLog.txt
  4. 5
      Doc/FDU.txt
  5. 2
      Readme.unix
  6. 149
      Source/Apps/FDU/FDU.asm
  7. 5
      Source/Apps/FDU/FDU.txt
  8. 47
      Source/CBIOS/cbios.asm
  9. 11
      Source/CPM3/boot.z80
  10. 49
      Source/CPM3/diskio.z80
  11. 2
      Source/HBIOS/Build.sh
  12. 3
      Source/HBIOS/Config/RCZ280_nat_zzr.asm
  13. 9
      Source/HBIOS/Makefile
  14. 1
      Source/HBIOS/cfg_dyno.asm
  15. 2
      Source/HBIOS/cfg_master.asm
  16. 1
      Source/HBIOS/cfg_mk4.asm
  17. 1
      Source/HBIOS/cfg_n8.asm
  18. 1
      Source/HBIOS/cfg_rcz180.asm
  19. 1
      Source/HBIOS/cfg_rcz280.asm
  20. 1
      Source/HBIOS/cfg_scz180.asm
  21. 33
      Source/HBIOS/hbios.asm
  22. 22
      Source/HBIOS/md.asm
  23. 2
      Source/HBIOS/romldr.asm
  24. 4
      Source/HBIOS/std.asm
  25. 2
      Source/HBIOS/z2u.asm
  26. BIN
      Source/Images/d_zpm3/u15/tcap.z3t
  27. BIN
      Source/Images/d_zpm3/u15/tcselect.com
  28. BIN
      Source/Images/d_zpm3/u15/z3tcap.lbr
  29. BIN
      Source/RomDsk/ROM_256KB/FLASH.COM
  30. 19
      Source/ZZR/Bank Layout.txt
  31. 6
      Source/ZZR/Build.cmd
  32. 10
      Source/ZZR/Makefile
  33. 48
      Source/ZZR/ZZR Disk Layout.txt
  34. BIN
      Source/ZZR/zzr_mon.bin
  35. 99
      Source/ZZR/zzr_romldr.hex
  36. 2
      Source/ver.inc
  37. 2
      Source/ver.lib
  38. 2
      Tools/Makefile.inc
  39. 1
      Tools/tasm32/TASM280.TAB
  40. 2
      Tools/unix/uz80as/targets.c
  41. 270
      Tools/unix/uz80as/z80.c

1
.gitignore
View File

@ -92,6 +92,7 @@ Tools/unix/zx/zx
!Source/ZSDOS/*.[Cc][Oo][Mm]
!Source/ZRC/*.bin
!Source/ZZR/*.bin
!Source/ZZR/*.hex
!Tools/cpm/bin
!Tools/unix/zx
!Tools/zx

8
Binary/RomList.txt
View File

@ -198,7 +198,7 @@ RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
- Built-in Z280 UART (Z2U) is buffered and interrupt driven only
on _nat and _nat_zz variants. It uses polling I/O on _ext.
- Console on whichever serial module is installed,
order of priority is UART, SIO, DUART, ACIA, Z2U
order of priority is Z2U, UART, SIO, DUART, ACIA
- Baud rate is determined by hardware, but normally 115200.
- Auto support for RC2014 Compact Flash Module
- Auto support for RC2014 PPIDE Module
@ -221,9 +221,9 @@ RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
SCZ180 (SCZ180_126.rom, SCZ180_130.rom, SCZ180_131.rom, SCZ140.rom):
- Same as RCZ180
- Adds auto support for SPI SD Card
- The 3 different variants of SCZ180 are provided to match the
3 corresponding systems (SC126, SC130, SC131, and SC140)
- Adds auto support for onboard SPI SD Card
- The 4 different variants of SCZ180 are provided to match the
4 corresponding systems (SC126, SC130, SC131, and SC140)
designed by Stephen Cousins.
- Support for PropIO V2 may be enabled in config (PRPENABLE). If
enabled, will auto-detect and install associated

1
Doc/ChangeLog.txt
View File

@ -22,6 +22,7 @@ Version 3.1.1
- WBW: Add support for ZZRCC
- WBW: Allow selection of RAM/ROM disk individually in build
- WBW: Support 256KB ROM size
- WBW: CP/M 3 RTC support is now complete (reads and writes RTC date/time)
Version 3.1
-----------

5
Doc/FDU.txt
View File

@ -517,4 +517,7 @@ WW 4/29/2020: v5.5
- Added support for Etched Pixels FDC
WW 12/12/2020: v5.6
- Updated SmallZ80 support for new I/O map
- Updated SmallZ80 support for new I/O map
WW 3/24/2021: v5.7
- Added support for a few single-sided formats

2
Readme.unix
View File

@ -17,7 +17,7 @@ with respect to the .DS directive. it's usually a bad idea to mix
output point. It works a lot more like M80, SLR* .PHASE
It assumes that you have some standard system tools and libraries
installed specifically: gcc, gnu make, libncurses
installed specifically: gcc, gnu make, libncurses, srecord
To build:
cd to the top directory and type "make".

149
Source/Apps/FDU/FDU.asm
View File

@ -47,6 +47,7 @@
; 2020-01-05: V5.4 ADDED SUPPORT FOR DYNO FDC
; 2020-04-29: v5.5 ADDED SUPPORT FOR ETCHED PIXELS FDC
; 2020-12-12: v5.6 UPDATED SMALLZ80 TO NEW I/O ADDRESSES
; 2021-03-24: v5.7 ADDED SOME SINGLE-SIDED FORMATS
;
;_______________________________________________________________________________
;
@ -216,8 +217,8 @@ INIT5:
XOR A
RET
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.6, 12-Dec-2020$"
STR_BANNER2 .DB "Copyright (C) 2020, Wayne Warthen, GNU GPL v3","$"
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.7, 24-Mar-2021$"
STR_BANNER2 .DB "Copyright (C) 2021, Wayne Warthen, GNU GPL v3","$"
STR_HBIOS .DB " [HBIOS]$"
STR_UBIOS .DB " [UBIOS]$"
;
@ -483,16 +484,16 @@ MM_INFO: .DW MM_DRAW
;
STR_MAINMENU:
.TEXT "=======================<< FDU MAIN MENU >>======================\r\n"
; .TEXT "(S)ETUP: UNIT=XX MEDIA=XXXXXX MODE=XXXXXXXXXX TRACE=XX\r\n"
; .TEXT "(S)ETUP: UNIT=XX MEDIA=XXXXXXXXXXXXX MODE=XXXXXXXXXX TRACE=XX\r\n"
.TEXT "(S)ETUP: UNIT="
MV_UNIT .TEXT "XX"
.TEXT " MEDIA="
MV_MED .TEXT "XXXXXX"
.TEXT " MODE="
MV_MODE .TEXT "XXXXXXXXXX"
.TEXT " TRACE="
MV_TRC .TEXT "XX"
.TEXT "\r\n"
MV_MED .TEXT "XXXXXXXXXXXXX"
.TEXT " MODE="
MV_MODE .TEXT "XXXXXXXXXX"
.TEXT " TRACE="
MV_TRC .TEXT "XX"
.TEXT "\r\n"
.TEXT "----------------------------------------------------------------\r\n"
.TEXT "(R)EAD (W)RITE (F)ORMAT (V)ERIFY\r\n"
.TEXT "(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT\r\n"
@ -1071,21 +1072,29 @@ MMOP_RANDOM1: ; GENERATE RANDOM TRACK
JP P,MMOP_RANDOM1
LD (DCD_TRACK),A
; GENERATE RANDOM HEAD
MMOP_RANDOM2: ; GENERATE RANDOM HEAD
;OR A
;CALL RNDBYTE
;AND 01H ; JUST USE LOW ORDER BIT
;LD (DCD_HEAD),A
LD A,(MDB_NUMHD)
LD C,A
CALL RNDBYTE
AND 01H ; JUST USE LOW ORDER BIT
AND 01H ; USE 1 BIT FOR UP TO 2 HEADS
CP C
JP P,MMOP_RANDOM2
LD (DCD_HEAD),A
MMOP_RANDOM2: ; GENERATE RANDOM SECTOR
MMOP_RANDOM3: ; GENERATE RANDOM SECTOR
LD A,(MDB_EOT)
LD C,A
INC C ; ONE MORE THEN MAX SECTOR
CALL RNDBYTE
AND 1FH ; USE 5 BITS FOR UP TO 32 SECTORS
CP C ; MAX SECTOR NUM IS 9 + 1 = 0AH
JP P,MMOP_RANDOM2
JP P,MMOP_RANDOM3
CP 00H ; SECTOR NUM STARTS AT 1, DON'T ALLOW ZERO
JP Z,MMOP_RANDOM2
JP Z,MMOP_RANDOM3
LD (DCD_SECTOR),A
CALL DIO_RUN
@ -1601,6 +1610,10 @@ MT_PC320 .EQU 2
MT_PC360 .EQU 3
MT_PC120 .EQU 4
MT_PC111 .EQU 5
MT_PC160 .EQU 6
MT_PC180 .EQU 7
MT_PC320SS .EQU 8
MT_PC360SS .EQU 9
;
MIT: ; MEDIA INDEX TABLE
.DW MDB_PC720
@ -1609,6 +1622,10 @@ MIT: ; MEDIA INDEX TABLE
.DW MDB_PC360
.DW MDB_PC120
.DW MDB_PC111
.DW MDB_PC160
.DW MDB_PC180
.DW MDB_PC320SS
.DW MDB_PC360SS
MIT_ENTCNT .EQU (($ - MIT) / 2)
;
; Specify Command:
@ -1660,7 +1677,7 @@ FCB_PC720 .DB 009H ; SECTOR COUNT
.IF (($ - MDB_PC720) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC720 .TEXT "720KB $"
DTL_PC720 .TEXT "720KB DS/DD $"
DTS_PC720 .TEXT "3.5\" 720KB - 9 SECTORS, 2 SIDES, 80 TRACKS, DOUBLE DENSITY$"
;
MDB_PC144 .DW DTL_PC144 ; ADDRESS OF MEDIA LABEL
@ -1683,7 +1700,7 @@ FCB_PC144 .DB 012H ; SECTOR COUNT
.IF (($ - MDB_PC144) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC144 .TEXT "1.44MB$"
DTL_PC144 .TEXT "1.44MB DS/HD $"
DTS_PC144 .TEXT "3.5\" 1.44MB - 18 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY$"
;
MDB_PC320 .DW DTL_PC320 ; ADDRESS OF MEDIA LABEL
@ -1706,7 +1723,7 @@ FCB_PC320 .DB 008H ; SECTOR COUNT
.IF (($ - MDB_PC320) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC320 .TEXT "320KB $"
DTL_PC320 .TEXT "320KB DS/DD $"
DTS_PC320 .TEXT "5.25\" 320KB - 8 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY$"
;
MDB_PC360 .DW DTL_PC360 ; ADDRESS OF MEDIA LABEL
@ -1729,7 +1746,7 @@ FCB_PC360 .DB 009H ; SECTOR COUNT
.IF (($ - MDB_PC360) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC360 .TEXT "360KB $"
DTL_PC360 .TEXT "360KB DS/DD $"
DTS_PC360 .TEXT "5.25\" 360KB - 9 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY$"
;
MDB_PC120 .DW DTL_PC120 ; ADDRESS OF MEDIA LABEL
@ -1752,7 +1769,7 @@ FCB_PC120 .DB 00FH ; SECTOR COUNT
.IF (($ - MDB_PC120) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC120 .TEXT "1.2MB $"
DTL_PC120 .TEXT "1.2MB DS/HD $"
DTS_PC120 .TEXT "5.25\" 1.2MB - 15 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY$"
;
MDB_PC111 .DW DTL_PC111 ; ADDRESS OF MEDIA LABEL
@ -1775,9 +1792,101 @@ FCB_PC111 .DB 00FH ; SECTOR COUNT
.IF (($ - MDB_PC111) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC111 .TEXT "1.11MB$"
DTL_PC111 .TEXT "1.11MB DS/DD $"
DTS_PC111 .TEXT "8\" 1.11MB - 15 SECTORS, 2 SIDES, 77 TRACKS, DOUBLE DENSITY$"
;
MDB_PC160 .DW DTL_PC160 ; ADDRESS OF MEDIA LABEL
.DW DTS_PC160 ; ADDRESS OF MEDIA DESCRIPTION
.DB 028H ; NUMBER OF CYLINDERS
.DB 001H ; NUMBER OF HEADS
.DB 008H ; NUMBER OF SECTORS
.DB 001H ; START OF TRACK (ID OF FIRST SECTOR, USUALLY 1)
FCB_PC160 .DB 008H ; SECTOR COUNT
.DW 200H ; SECTOR SIZE IN BYTES
.DB 02AH ; GAP LENGTH (R/W)
.DB 050H ; GAP LENGTH (FORMAT)
.DB (13 << 4) | 0 ; SRT = 6ms, HUT = 512ms
.DB 4 ; HLT = 16ms
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC160) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC160 .TEXT "160KB SS/DD $"
DTS_PC160 .TEXT "5.25\" 160KB - 8 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY$"
;
MDB_PC180 .DW DTL_PC180 ; ADDRESS OF MEDIA LABEL
.DW DTS_PC180 ; ADDRESS OF MEDIA DESCRIPTION
.DB 028H ; NUMBER OF CYLINDERS
.DB 001H ; NUMBER OF HEADS
.DB 009H ; NUMBER OF SECTORS
.DB 001H ; START OF TRACK (ID OF FIRST SECTOR, USUALLY 1)
FCB_PC180 .DB 009H ; SECTOR COUNT
.DW 200H ; SECTOR SIZE IN BYTES
.DB 02AH ; GAP LENGTH (R/W)
.DB 050H ; GAP LENGTH (FORMAT)
.DB (13 << 4) | 0 ; SRT = 6ms, HUT = 512ms
.DB 4 ; HLT = 16ms
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC180) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC180 .TEXT "180KB SS/DD $"
DTS_PC180 .TEXT "5.25\" 180KB - 9 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY$"
;
MDB_PC320SS .DW DTL_PC320SS ; ADDRESS OF MEDIA LABEL
.DW DTS_PC320SS ; ADDRESS OF MEDIA DESCRIPTION
.DB 050H ; NUMBER OF CYLINDERS
.DB 001H ; NUMBER OF HEADS
.DB 008H ; NUMBER OF SECTORS
.DB 001H ; START OF TRACK (ID OF FIRST SECTOR, USUALLY 1)
FCB_PC320SS .DB 008H ; SECTOR COUNT
.DW 200H ; SECTOR SIZE IN BYTES
.DB 02AH ; GAP LENGTH (R/W)
.DB 050H ; GAP LENGTH (FORMAT)
.DB (13 << 4) | 0 ; SRT = 6ms, HUT = 512ms
.DB 4 ; HLT = 16ms
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC320SS) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC320SS .TEXT "320KB SS/DD $"
DTS_PC320SS .TEXT "5.25\" 320KB - 8 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY$"
;
MDB_PC360SS .DW DTL_PC360SS ; ADDRESS OF MEDIA LABEL
.DW DTS_PC360SS ; ADDRESS OF MEDIA DESCRIPTION
.DB 050H ; NUMBER OF CYLINDERS
.DB 001H ; NUMBER OF HEADS
.DB 009H ; NUMBER OF SECTORS
.DB 001H ; START OF TRACK (ID OF FIRST SECTOR, USUALLY 1)
FCB_PC360SS .DB 009H ; SECTOR COUNT
.DW 200H ; SECTOR SIZE IN BYTES
.DB 02AH ; GAP LENGTH (R/W)
.DB 050H ; GAP LENGTH (FORMAT)
.DB (13 << 4) | 0 ; SRT = 6ms, HUT = 512ms
.DB 4 ; HLT = 16ms
.DB DORA_BR250 ; OPERATIONS REGISTER VALUE
.DB DORB_BR250 ; OPERATIONS REGISTER VALUE
.DB DORC_BR250 ; OPERATIONS REGISTER VALUE
.DB DORD_BR250 ; OPERATIONS REGISTER VALUE
.DB DCR_BR250 ; CONTROL REGISTER VALUE
.IF (($ - MDB_PC360SS) != MDB_LEN)
.ECHO "*** FCB SIZE ERROR!!! ***\n"
.ENDIF
DTL_PC360SS .TEXT "360KB SS/DD $"
DTS_PC360SS .TEXT "5.25\" 360KB - 9 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY$"
;
;===============================================================================
; FLOPPY DISK CONTROL MENU (DIRECT MENU INTERFACE TO FDC & RELATED HARDWARE)
;===============================================================================

5
Source/Apps/FDU/FDU.txt
View File

@ -517,4 +517,7 @@ WW 4/29/2020: v5.5
- Added support for Etched Pixels FDC
WW 12/12/2020: v5.6
- Updated SmallZ80 support for new I/O map
- Updated SmallZ80 support for new I/O map
WW 3/24/2021: v5.7
- Added support for a few single-sided formats

47
Source/CBIOS/cbios.asm
View File

@ -2174,23 +2174,42 @@ INIT2:
#IFDEF PLTWBW
;
; IF WE HAVE MULTIPLE DRIVES AND THE FIRST DRIVE IS RAM DRIVE
; AND THE SECOND DRIVE IS ROM DRIVE OR FLASH DRIVE
; THEN MAKE OUR DEFAULT STARTUP DRIVE THE SECOND DRIVE (B:)
;
; CHECK FOR 2+ DRIVES
LD HL,(DRVMAPADR) ; POINT TO DRIVE MAP
DEC HL ; BUMP BACK TO DRIVE COUNT
LD A,(HL) ; GET IT
CP 2 ; COMPARE TO 2
JR C,INIT2X ; IF LESS THAN 2, THEN DONE
;
; CHECK IF FIRST UNIT IS RAM
LD B,BF_DIODEVICE ; HBIOS FUNC: REPORT DEVICE INFO
INC HL ; POINT TO UNIT FIELD
LD C,(HL) ; ... OF FIRST DRIVE
INC HL ; POINT TO UNIT FIELD OF FIRST DRIVE
LD C,(HL) ; PUT UNIT NUM IN C
RST 08 ; CALL HBIOS
LD A,D ; DEVICE TYPE TO A
CP DIODEV_MD ; MEMORY DISK DEVICE?
JR NZ,INIT2X ; IF NOT, THEN DONE
LD A,C ; GET ATTRIBUTES
AND %00111000 ; ISOLATE TYPE BITS
CP %00101000 ; TYPE = RAM?
JR NZ,INIT2X ; IF NOT THEN DONE
;
; CHECK IF SECOND UNIT IS ROM OR FLASH
LD B,BF_DIODEVICE ; HBIOS FUNC: REPORT DEVICE INFO
LD HL,(DRVMAPADR) ; POINT TO DRIVE MAP
LD A,4 ; 4 BYTES PER ENTRY
CALL ADDHLA ; POINT TO UNIT FIELD OF SECOND DRIVE
LD C,(HL) ; PUT UNIT NUM IN C
RST 08 ; CALL HBIOS
LD A,C ; GET ATTRIBUTES
AND %00111000 ; ISOLATE TYPE BITS
CP %00100000 ; TYPE = ROM?
JR Z,INIT2A ; IF SO, ADJUST DEF DRIVE
CP %00111000 ; TYPE = FLASH?
JR NZ,INIT2X ; IF NOT THEN DONE
;
INIT2A:
; CRITERIA MET, ADJUST DEF DRIVE TO B:
LD A,1 ; USE SECOND DRIVE AS DEFAULT
LD (DEFDRIVE),A ; RECORD DEFAULT DRIVE
;
@ -2712,14 +2731,6 @@ DRV_INIT:
; GET BOOT UNIT/SLICE INFO
LD DE,(HCB + HCB_BOOTVOL) ; BOOT VOLUME (UNIT, SLICE)
LD (BOOTVOL),DE ; D -> UNIT, E -> SLICE
;;
; ; INIT DEFAULT
; LD A,D ; BOOT UNIT?
; CP 1 ; IF ROM BOOT, DEF DRIVE SHOULD BE B:
; JR Z,DRV_INIT1 ; ... SO LEAVE AS IS AND SKIP AHEAD
; XOR A ; ELSE FORCE TO DRIVE A:
;DRV_INIT1:
; LD (DEFDRIVE),A ; STORE IT
;
; SETUP THE DRVMAP STRUCTURE
LD HL,(HEAPTOP) ; GET CURRENT HEAP TOP
@ -2808,11 +2819,8 @@ DRV_INIT5:
LD A,E ; SLICES PER VOLUME VALUE TO ACCUM
LD (HDSPV),A ; SAVE IT
LD DE,(BOOTVOL) ; BOOT VOLUME (UNIT, SLICE)
LD A,1 ; ROM DISK UNIT?
CP D ; CHECK IT
JR Z,DRV_INIT5A ; IF SO, SKIP BOOT DRIVE
LD B,1 ; JUST ONE SLICE PLEASE
CALL DRV_INIT8A ; DO THE BOOT DEVICE
CALL DRV_INIT8A ; DO THE BOOT UNIT & SLICE FIRST
;
DRV_INIT5A:
LD A,(DRVLSTC) ; ACTIVE DRIVE LIST COUNT TO ACCUM
@ -2848,9 +2856,10 @@ DRV_INIT7: ; PROCESS UNIT
DRV_INIT8:
; SLICE CREATION LOOP
; DE=UNIT/SLICE, B=SLICE CNT
;
; FIRST, CHECK TO SEE IF THIS IS THE BOOT VOL & SLICE.
; IF SO, IT HAS ALREADY BEEN PROCESSED ABOVE, SO SKIP IT HERE.
LD A,(BOOTVOL + 1) ; GET BOOT UNIT
CP 1 ; ROM BOOT?
JR Z,DRV_INIT8A ; IF SO, OK TO CONTINUE
CP D ; COMPARE TO CUR UNIT
JR NZ,DRV_INIT8A ; IF NE, OK TO CONTINUE
LD A,(BOOTVOL) ; GET BOOT SLICE

11
Source/CPM3/boot.z80
View File

@ -317,8 +317,14 @@ clrram:
di ; no interrupts
ld a,(0FFE0h) ; get current bank
push af ; save it
;ld a,(bnkramd) ; first bank of ram disk
ld a,080h ; first bank of ram disk
ld b,0FAh ; HBIOS Peek Function
ld a,(@hbbio) ; HBIOS bank id
ld d,a ; ... goes in D
ld hl,1DCh ; Offset 1DCh is ram disk bank 0
rst 08 ; Call HBIOS, value in E
ld a,e ; move to A for bank sel
cp 0FFh
jr z,clrram3
;call hb_bnksel ; select bank
call 0FFF3h ; select bank
@ -348,7 +354,6 @@ clrram2:
or 0ffh ; flag value for cleared
ld (clrflg),a ; save it
clrram3:
;ld a,(bnkuser) ; usr bank (tpa)
pop af ; recover original bank
;call hb_bnksel ; select bank
call 0FFF3h ; select bank

49
Source/CPM3/diskio.z80
View File

@ -15,6 +15,7 @@
public @sysdr
extrn @bootdu,@bootsl
extrn @hbbio
; Variables containing parameters passed by BDOS
@ -354,6 +355,54 @@ dpb$hdnew: ; 8MB Hard Disk Drive (new format)
; called for first time initialization.
dsk$init:
ld b,0FAh ; HBIOS Peek Function
ld a,(@hbbio) ; HBIOS bank id
ld d,a ; ... goes in D
ld hl,10Ch ; Offset 10Ch is ROM bank cnt
rst 08 ; Call HBIOS, value in E
ld a,e ; move count to accum
sub 4 ; reduce by # reserved banks
ld ix,dpb$rom ; address of DPB
call dsk$init1 ; fix it up
ld b,0FAh ; HBIOS Peek Function
ld a,(@hbbio) ; HBIOS bank id
ld d,a ; ... goes in D
ld hl,10Bh ; Offset 10Bh is RAM bank cnt
rst 08 ; Call HBIOS, value in E
ld a,e ; move count to accum
sub 8 ; reduce by # reserved banks
ld ix,dpb$ram ; address of DPB
call dsk$init1 ; fix it up
ret ; done
dsk$init1:
; Setup HL with bank count
ld l,a ; lsb
ld h,0 ; msb is always zero
; Update EXM field
ld a,l ; lsb of bank count
cp 16 + 1 ; compare to EXM threshold
ld a,1 ; assume <= 16 banks, EXM := 0
jr c,dsk$init2 ; done if so
xor a ; > 16 banks, EXM := 0
dsk$init2:
ld (ix + 4),a ; save new EXM value
; Update DSM field
ld b,4 ; prepare to mult by 16
dsk$init3:
sla l ; shift lsb
rl h ; shift msb w/ carry
djnz dsk$init3 ; repeat as needed
dec hl ; subtract 1 for proper DSM value
ld (ix+5),l ; save updated
ld (ix+6),h ; ... DSM value
ret
;ld a,(@rdrv) ; unit being initialized
;ld hl,@bootdu
;cp (hl) ; compare to boot unit

2
Source/HBIOS/Build.sh
View File

@ -25,6 +25,8 @@ config=$2
romsize=$3
romname=$4
export platform
# prompt if no match
platforms=($(find Config -name \*.asm -print | \
sed -e 's,Config/,,' -e 's/_.*$//' | sort -u))

3
Source/HBIOS/Config/RCZ280_nat_zzr.asm
View File

@ -28,8 +28,7 @@
;
#include "Config/RCZ280_nat.asm"
;
;CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ
;
RAMSIZE .SET 384 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAM_RESERVE .SET 128 ; RESERVE FIRST N KB OF RAM (USUALLY 0)

9
Source/HBIOS/Makefile
View File

@ -44,13 +44,20 @@ TOOLS =../../Tools
OTHERS = *.img *.rom *.com *.bin *.z80 cpm.sys zsys.sys Build.inc RomDisk.tmp font*.asm *.dat
include $(TOOLS)/Makefile.inc
ifneq ($(findstring $(platform), N8 MK4 RCZ180 SCZ180 DYNO),)
TASM=$(BINDIR)/uz80as -t hd64180
endif
ifneq ($(findstring $(platform), RCZ280),)
TASM=$(BINDIR)/uz80as -t z280
endif
ifeq ($(DIFFMAKE),1)
DIFFBUILD := -d $(DIFFTO)/Source/HBIOS
endif
DIFFPATH = $(DIFFTO)/Binary
ROMSIZE=512
N8_std.rom: ROMSIZE=512

1
Source/HBIOS/cfg_dyno.asm
View File

@ -43,6 +43,7 @@ Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
;

2
Source/HBIOS/cfg_master.asm
View File

@ -42,11 +42,13 @@ Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU FALSE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
Z280_MEMLOWAIT .EQU 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
Z280_MEMHIWAIT .EQU 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
Z280_TIMER .EQU FALSE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
;
N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR

1
Source/HBIOS/cfg_mk4.asm
View File

@ -38,6 +38,7 @@ Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR

1
Source/HBIOS/cfg_n8.asm
View File

@ -38,6 +38,7 @@ Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR

1
Source/HBIOS/cfg_rcz180.asm
View File

@ -43,6 +43,7 @@ Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
;

1
Source/HBIOS/cfg_rcz280.asm
View File

@ -43,6 +43,7 @@ Z280_MEMLOWAIT .EQU 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
Z280_MEMHIWAIT .EQU 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
Z280_TIMER .EQU TRUE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
;
RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
;

1
Source/HBIOS/cfg_scz180.asm
View File

@ -38,6 +38,7 @@ Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
;

33
Source/HBIOS/hbios.asm
View File

@ -812,7 +812,7 @@ HBX_INT: ; COMMON INTERRUPT ROUTING CODE
POP HL ; RESTORE HL
;
CALL HBX_RETI ; RETI FOR Z80 PERIPHERALS
.DB $ED,$55 ; RETIL
RETIL
;
HBX_RETI:
RETI
@ -1192,8 +1192,6 @@ Z280_INITZ:
;
DIAG(%00000011)
LED($00)
; ok
;
; CHECK BATTERY BACKUP STATUS BEFORE WE COPY PROXY TO UPPER MEMORY
;
@ -1605,6 +1603,8 @@ HB_CPU2:
; MASK ALL EXTERNAL INTERRUPTS FOR NOW
LD A,$01 ; INT0 ENABLED, INT1-2 DISABLED
OUT0 (Z180_ITC),A ; WRITE TO INT/TRAP CONTROL REGISTER
;
#IF (Z180_TIMER)
;
; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
LD HL,HB_TIMINT
@ -1633,6 +1633,8 @@ HB_CPU2:
OUT0 (Z180_RLDR0H),H
LD A,%00010001 ; ENABLE TIMER0 INT AND DOWN COUNTING
OUT0 (Z180_TCR),A
;
#ENDIF
;
#ENDIF
;
@ -1641,6 +1643,8 @@ HB_CPU2:
#IF (CPUFAM == CPU_Z280)
;
#IF (MEMMGR == MM_Z280)
;
#IF (Z280_TIMER)
;
Z280_TC .EQU CPUOSC / 4 / 50 / 2 ; TIME CONSTANT
;
@ -1656,7 +1660,7 @@ Z280_TC .EQU CPUOSC / 4 / 50 / 2 ; TIME CONSTANT
;
LD A,%10100000 ; CONFIG: C, RE, IE
OUT (Z280_CT0_CFG),A ; SET C/T 0
LD HL,Z280_TC ; TIME CONSTANT & COUNTER
LD HL,CPUOSC / 50 / 16 ; TIME CONSTANT & COUNTER
LD C,Z280_CT0_TC ; SET C/T 0
OUTW (C),HL
LD C,Z280_CT0_CT ; SET C/T 0
@ -1668,6 +1672,8 @@ Z280_TC .EQU CPUOSC / 4 / 50 / 2 ; TIME CONSTANT
LD C,Z280_IOPR ; I/O PAGE REGISTER
POP HL ; RESTORE I/O PAGE
LDCTL (C),HL
;
#ENDIF
;
#ENDIF
;
@ -1879,12 +1885,12 @@ HB_Z280BUS1:
#IF (CPUFAM == CPU_Z280)
LD A,Z280_MEMLOWAIT
CALL PRTDECB
CALL PRTSTRD
.TEXT " MEM LO W/S, $"
LD A,'/'
CALL COUT
LD A,Z280_MEMHIWAIT
CALL PRTDECB
CALL PRTSTRD
.TEXT " MEM HI W/S, $"
.TEXT " MEM W/S, $"
#ELSE
XOR A
#IF (CPUFAM == CPU_Z180)
@ -3661,8 +3667,11 @@ Z280_TIMINT:
PUSH DE
PUSH HL
;
; CALL PRIMARY TIMER LOGIC
CALL HB_TIMINT
; CALL PRIMARY TIMER LOGIC ON EVERY OTHER INT
LD A,(Z280_TIMCTR)
XOR $FF
LD (Z280_TIMCTR),A
CALL Z,HB_TIMINT
;
; SELECT I/O PAGE $FE (SAVING PREVIOUS VALUE)
LD C,Z280_IOPR ; REG C POINTS TO I/O PAGE REGISTER
@ -3687,7 +3696,9 @@ Z280_TIMINT:
POP BC
POP AF
;
.DB $ED,$55 ; RETIL
RETIL
;
Z280_TIMCTR .DB 0 ; USED TO DIVIDE TIMER INTS
;
#ENDIF
;
@ -3871,7 +3882,7 @@ Z280_DIAG:
CALL PRTHEXWORDHL ; DUMP MSR
EX (SP),HL ; MSR TO STK, RECOVER HL
;
;.DB $ED,$55 ; RETIL
;RETIL
DI
HALT
;

22
Source/HBIOS/md.asm
View File

@ -33,8 +33,8 @@ MD_FVAR .EQU 1 ; FLASH VERIFY AFTER WRITE
;
MD_CFGTBL:
#IF (MDRAM)
; DEVICE 1 (RAM)
.DB 1 ; DRIVER DEVICE NUMBER
; DEVICE 0 (RAM)
.DB 0 ; DEVICE NUMBER
.DB 0 ; DEVICE STATUS
.DW 0,0 ; CURRENT LBA
.DB MID_MDRAM ; DEVICE MEDIA ID
@ -42,8 +42,8 @@ MD_CFGTBL:
#ENDIF
;
#IF (MDROM)
; DEVICE 0 (ROM)
.DB 0 ; DEVICE NUMBER
; DEVICE 1 (ROM)
.DB 1 ; DEVICE NUMBER
.DB 0 ; DEVICE STATUS
.DW 0,0 ; CURRENT LBA
.DB MID_MDROM ; DEVICE MEDIA ID
@ -158,7 +158,7 @@ MD_RESET:
;
;
;
MD_CAP: ; ASSUMES THAT UNIT 1 IS RAM, UNIT 0 IS ROM
MD_CAP: ; ASSUMES THAT UNIT 0 IS RAM, UNIT 1 IS ROM
LD A,(IY+MD_DEV) ; GET DEVICE NUMBER
OR A ; SET FLAGS
JR Z,MD_CAP0 ; UNIT 0
@ -169,11 +169,11 @@ MD_CAP: ; ASSUMES THAT UNIT 1 IS RAM, UNIT 0 IS ROM
OR A
RET
MD_CAP0:
LD A,(HCB + HCB_ROMBANKS) ; POINT TO ROM BANK COUNT
LD A,(HCB + HCB_RAMBANKS) ; POINT TO RAM BANK COUNT
LD B,4 ; SET # RESERVED ROM BANKS
JR MD_CAP2
MD_CAP1:
LD A,(HCB + HCB_RAMBANKS) ; POINT TO RAM BANK COUNT
LD A,(HCB + HCB_ROMBANKS) ; POINT TO ROM BANK COUNT
LD B,8 ; SET # RESERVED RAM BANKS
MD_CAP2:
SUB B ; SUBTRACT OUT RESERVED BANKS
@ -619,12 +619,12 @@ MD_IOSETUP:
POP AF ; GET BANK AND FLAGS BACK
JR Z,MD_IOSETUP2 ; DO ROM DRIVE, ELSE FALL THRU FOR RAM DRIVE
;
MD_IOSETUP1: ; RAM
ADD A,BID_RAMD0
MD_IOSETUP1: ; ROM
ADD A,BID_ROMD0
RET
;
MD_IOSETUP2: ; ROM
ADD A,BID_ROMD0
MD_IOSETUP2: ; RAM
ADD A,BID_RAMD0
RET
;
;

2
Source/HBIOS/romldr.asm
View File

@ -648,7 +648,7 @@ romload1:
; Record boot information
pop af ; recover source bank
ld l,a ; L := source bank
ld de,$0100 ; boot volume/slice
ld de,$0000 ; boot vol=0, slice=0
ld b,BF_SYSSET ; HBIOS func: system set
ld c,BF_SYSSET_BOOTINFO ; BBIOS subfunc: boot info
rst 08 ; do it

4
Source/HBIOS/std.asm
View File

@ -434,13 +434,17 @@ SYSTIM .SET TM_SIMH
#ENDIF
;
#IF ((CPUFAM == CPU_Z180) & (INTMODE == 2))
#IF (Z180_TIMER)
SYSTIM .SET TM_Z180
.ECHO " Z180"
#ENDIF
#ENDIF
;
#IF ((CPUFAM == CPU_Z280) & (MEMMGR == MM_Z280))
#IF (Z280_TIMER)
SYSTIM .SET TM_Z280
.ECHO " Z280"
#ENDIF
#ENDIF
;
#IF SYSTIM == TM_NONE

2
Source/HBIOS/z2u.asm
View File

@ -245,7 +245,7 @@ Z2U_INTRCV4:
POP BC
POP AF
;
.DB $ED,$55 ; RETIL
RETIL
#ENDIF
;
; DRIVER FUNCTION TABLE

BIN
Source/Images/d_zpm3/u15/tcap.z3t
View File

Binary file not shown.

BIN
Source/Images/d_zpm3/u15/tcselect.com
View File

Binary file not shown.

BIN
Source/Images/d_zpm3/u15/z3tcap.lbr
View File

Binary file not shown.

BIN
Source/RomDsk/ROM_256KB/FLASH.COM
View File

Binary file not shown.

19
Source/ZZR/Bank Layout.txt
View File

@ -0,0 +1,19 @@
Bank ROM RAM RAM
---- --- --- ---
0 HBIOS (IMG) RAMDISK RAMDISK
1 ROMLDR+MON+CP/M2+ZSYS RAMDISK RAMDISK
2 FTH+BAS+TBAS+PLAY+USR RAMDISK RAMDISK
3 RESERVED RAMDISK RAMDISK
4 ROMDISK RAMDISK RAMDISK
5 ROMDISK RAMDISK RAMDISK
6 ROMDISK RAMDISK RAMDISK
7 ROMDISK RAMDISK RAMDISK
8 ROMDISK BUF (CPM3) BUF (CPM3)
9 ROMDISK BUF (CPM3) BUF (CPM3)
A ROMDISK BUF (CPM3) BUF (CPM3)
B ROMDISK BUF (CPM3) BUF (CPM3)
C ROMDISK AUX (CPM3) TPA (CPM3)
D ROMDISK HBIOS (EXEC) HBIOS (EXEC)
E ROMDISK TPA-LO OS (CPM3)
F ROMDISK COMMON (TPA-HI) COMMON (TPA-HI)

6
Source/ZZR/Build.cmd
View File

@ -3,8 +3,10 @@ setlocal
if not exist ..\..\Binary\RCZ280_nat_zzr.rom goto :eof
..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_nat_zzr.rom -Binary -Exclude 0x5000 0x7000 -Output ..\..\Binary\RCZ280_nat_zzr.hex -Intel
..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_nat_zzr.rom -Binary -Exclude 0x5000 0x7000 zzr_romldr.hex -Intel -Output ..\..\Binary\RCZ280_nat_zzr.hex -Intel
copy /b zzr_cfldr.bin + zzr_ptbl.bin + zzr_fill_1.bin + zzr_mon.bin + zzr_fill_2.bin + ..\..\Binary\RCZ280_nat_zzr.rom + zzr_fill_3.bin ..\..\Binary\hd1024_zzr_prefix.dat
..\..\Tools\srecord\srec_cat.exe ..\..\Binary\RCZ280_nat_zzr.hex -Intel -Output ..\..\Binary\RCZ280_nat_zzr_ldr.rom -Binary
copy /b zzr_cfldr.bin + zzr_ptbl.bin + zzr_fill_1.bin + zzr_mon.bin + zzr_fill_2.bin + ..\..\Binary\RCZ280_nat_zzr_ldr.rom + zzr_fill_3.bin ..\..\Binary\hd1024_zzr_prefix.dat
copy /b ..\..\Binary\hd1024_zzr_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zzr_combo.img

10
Source/ZZR/Makefile
View File

@ -1,6 +1,7 @@
HD1024ZZRPREFIX = hd1024_zzr_prefix.dat
HD1024ZZZROMBOIMG = hd1024_zzr_combo.img
ZZRROM = ../../Binary/RCZ280_nat_zzr.rom
ZZRLDRROM = RCZ280_nat_zzr_ldr.rom
ZZRROMHEX = RCZ280_nat_zzr.hex
HD1024IMGS = ../../Binary/hd1024_cpm22.img ../../Binary/hd1024_zsdos.img ../../Binary/hd1024_nzcom.img \
../../Binary/hd1024_cpm3.img ../../Binary/hd1024_zpm3.img ../../Binary/hd1024_ws4.img
@ -10,7 +11,7 @@ OBJECTS :=
ifneq ($(wildcard $(ZZRROM)),)
OBJECTS += $(HD1024ZZRPREFIX) $(HD1024ZZZROMBOIMG) $(ZZRROMHEX)
OBJECTS += $(ZZRROMHEX) $(ZZRLDRROM) $(HD1024ZZRPREFIX) $(HD1024ZZZROMBOIMG)
endif
DEST=../../Binary
@ -22,10 +23,13 @@ include $(TOOLS)/Makefile.inc
DIFFPATH = $(DIFFTO)/Binary
$(HD1024ZZRPREFIX):
cat zzr_cfldr.bin zzr_ptbl.bin zzr_fill_1.bin zzr_mon.bin zzr_fill_2.bin $(ZZRROM) zzr_fill_3.bin >$@
cat zzr_cfldr.bin zzr_ptbl.bin zzr_fill_1.bin zzr_mon.bin zzr_fill_2.bin $(ZZRLDRROM) zzr_fill_3.bin >$@
$(HD1024ZZZROMBOIMG): $(HD1024ZZRPREFIX) $(HD1024IMGS)
cat $^ > $@
$(ZZRROMHEX): $(ZZRROM)
srec_cat $(ZZRROM) -Binary -Exclude 0x5000 0x7000 -Output $(ZZRROMHEX) -Intel
srec_cat $(ZZRROM) -Binary -Exclude 0x5000 0x7000 zzr_romldr.hex -Intel -Output $(ZZRROMHEX) -Intel
$(ZZRLDRROM): $(ZZRROMHEX)
srec_cat $(ZZRROMHEX) -Intel -Output $(ZZRLDRROM) -Binary

48
Source/ZZR/ZZR Disk Layout.txt
View File

@ -1,29 +1,37 @@
CF Boot Loader: Sector 0 (bytes 0-255)
RomWBW Partition Table: Sector 0 (bytes 256-511)
ZZRCC Monitor: Sectors 0xF8-0xFF (bytes 0x1F000-0x1FFFF)
RomWBW: Sectors 0x120-0x31F (bytes 0x24000-0x63FFF)
Start of Slices (0x1E partition): Sector 0x800 (byte 0x100000)
Start Length Description
------- ------- ---------------------------
0x00000 0x00100 CF Boot Loader
0x00100 0x00100 RomWBW Partition Table
0x00200 0x1EE00 Filler
0x1F000 0x01000 ZZRCC Monitor
0x20000 0x04000 Filler
0x24000 0x40000 RomWBW
0x64000 0x9C000 Filler
0x100000: Start of slices (partition 0x1E)
Start Length Sector Count Description
------- ------- ------- ------- -----------------------------------------
0x00000 0x00100 0x000 0x001 CF Boot Loader (first 256 bytes)
0x00100 0x00100 0x000 0x001 RomWBW Partition Table (last 256 bytes)
0x00200 0x1EE00 0x001 0x0F7 Filler
0x1F000 0x01000 0x0F8 0x008 ZZRCC Monitor / RomWBW Loader
0x20000 0x04000 0x100 0x020 Filler
0x24000 0x40000 0x120 0x200 RomWBW (256KB ROM image)
0x64000 0x9C000 0x320 0x4E0 Filler
0x100000 0x800 Slices
Must insert zzr_romldr.bin at 0x5000-x5FFF of ROM image. This is also 0x29000-0x29FFF of CF image.
Notes
-----
- At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
- CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
- User sends ZZRCC RomWBW Loader hex file (?KB) at 0x5000, then runs it using G5000
- User sends RomWBW ROM hex file, then runs it using G0000
- CPLD ROM (CF bootstrap mode) loads CF Boot Loader (256B) at 0xB000 and runs it
- CF Boot Loader loads ZRC Monitor at 0xB400 and runs it
- User loads ZZRCC RomWBW Loader hex file at 0x5000, then runs it using G5000
- User loads RomWBW ROM hex file to contents of RAM, then runs it using G0000
;;- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of RAM
Possible new layout:
Start Length Sector Count Description
------- ------- ------- ------- -----------------------------------------
0x00000 0x00100 0 1 CF Boot Loader (first 256 bytes)
0x00100 0x00100 0 1 RomWBW Partition Table (last 256 bytes)
0x00200 0x01000 0x001 0x008 ZZRCC Monitor / RomWBW Loader
0x01200 0x7EE00 0x009 0x3F7 Filler
0x80000 0x40000 0x400 0x200 RomWBW (256KB ROM image)
0xC0000 0x40000 0x600 0x200 Filler
0x100000 0x800 Slices (0x1E partition start)

BIN
Source/ZZR/zzr_mon.bin
View File

Binary file not shown.

99
Source/ZZR/zzr_romldr.hex
View File

@ -0,0 +1,99 @@
:06500000C31850C30C525E
:1050180031005FCD0F53218855CD0653CD3253FE55
:105028003ACA2E5018F6210000220850CDCD52570A
:105038004F47CDCD52678047CDCD526F8047CDCDFC
:1050480052FE00CA9050FE01CA7E50FE04C2F950BA
:1050580080477AFE02C2F950CDCD523209508047BE
:10506800CDCD523208508047CDCD52ED44B8C2F56F
:10507800503E45C3F050CDCD52212356CD0653CDD9
:105088000851CD1B53C300008047DD210060CDCD02
:1050980052DD77008047DD2315C29650CDCD52ED05
:1050A80044B8C2F550CD1553E50600C50E1F21E0E2
:1050B800F0EDBF0E1CE1EDBF0E1B216F00EDBF0E22
:1050C8001A2100F0EDBF0E193A085067D16A3E0F59
:1050D800B5EDBF0E18626B3EF0B4EDBF2180800EB7
:1050E8001DEDBFCD0F533E2ECD3C5318093E3F1842
:1050F800F73E55CD3C53CD3253FE3A20F9C33450D8
:10510800AF320C503E01320D50116855CD1B53AFD4
:10511800D3153EE0D3160E102147533A0D50D31441
:105128003A0C50D3133E01D3123E30D317DB17E6A7
:1051380008CA355106007EED79237ABC20057BBD6F
:1051480020012B0520F07EED79237ABC20057BBD5C
:1051580020012B0520F0DB17E680C25E513A0C5087
:105168003C320C50FE20C22351AF320E50210A00AF
:10517800CD15533E0AD3F10EF5EDBF3E1AD3F10E0D
:10518800F5EDBFCD1B53AFD3153EE0D3160E10215E
:1051980000A03A0D50D3143A0C50D3133E01D31249
:1051A8003E30D317DB17E608CAAC510600EDB3ED65
:1051B800B3DB17E680C2B9513A0C503C320C502090
:1051C800073A0D503C320D503EB0BC20C53A0E5047
:1051D8003C320E50FAF551260017CB1417CB141792
:1051E800CB1417CB14E6F0F60A6FC37851CD1553DC
:1051F80021AA003E0AD3F10EF5EDBF3E1AD3F10EF7
:10520800F5EDBFC931005FCD0F53210356CD0653CD
:105218003E20320A503E01320B50AF320E50210A66
:1052280000CD15533E06D3F10EF5EDBF3E16D3F172
:105238000EF5EDBFCD1B53AFD3153EE0D3160E10C0
:105248002100603A0B50D3143A0A50D3133E01D3CD
:10525800123E20D317DB17E608CA5D520600EDB2EE
:10526800EDB23A0A503C320A5020073A0B503C3211
:105278000B503E70BC20CC18083A0A50C608320AB7
:10528800503A0E503C320E50FAB152FE0528EAFE52
:105298000628E6260017CB1417CB1417CB1417CB08
:1052A80014E6F0F60A6FC32952CD1553216A003E61
:1052B80006D3F10EF5EDBF3E16D3F10EF5EDBFCDD9
:1052C8001B53C30000D5CD3253CDE2520707070761
:1052D80057CD3253CDE252B2D1C9D630FA0253FE7D
:1052E8000AF8D611FA0053C60AFE10F8D62AFAFEB2
:1052F80052C60AFE10F8C616C611C630BFC97EB718
:10530800C8CD3C532318F7E52EFEC31E53E52EFFE8
:10531800C31E53E52E00C50E08ED6EC1E1C9DB14AE
:10532800E610CA2653DB16D318C9DB14E610CA32B6
:1053380053DB16C9F5DB121FD23D53F1D318C90050
:10534800524F4D5742572020494D470100008004D5
:1053580000050006000700080009000A000B00000D
:10536800524F4D5742572020494D47030000800CAB
:10537800000D000E000F00100011001200130000B5
:10538800524F4D5742572020494D47050000801481
:1053980000150016001700180019001A001B00005D
:1053A800524F4D5742572020494D47070000801C57
:1053B800001D001E001F0020002100220023000005
:1053C800524F4D5742572020494D4709000080242D
:1053D80000250026002700280029002A002B0000AD
:1053E800524F4D5742572020494D470B0000802C03
:1053F800002D002E002F0030003100320033000055
:10540800524F4D5742572020494D470D00008034D8
:1054180000350036003700380039003A003B0000FC
:10542800524F4D5742572020494D470F0000803CAE
:10543800003D003E003F00400041004200430000A4
:10544800524F4D5742572020494D47110000804484
:1054580000450046004700480049004A004B00004C
:10546800524F4D5742572020494D47130000804C5A
:10547800004D004E004F00500051005200530000F4
:10548800524F4D5742572020494D47150000805430
:1054980000550056005700580059005A005B00009C
:1054A800524F4D5742572020494D47170000805C06
:1054B800005D005E005F0060006100620063000044
:1054C800524F4D5742572020494D471900008064DC
:1054D80000650066006700680069006A006B0000EC
:1054E800524F4D5742572020494D471B0000806CB2
:1054F800006D006E006F0070007100720073000094
:10550800524F4D5742572020494D471D0000807487
:1055180000750076007700780079007A007B00003B
:10552800524F4D5742572020494D471F0000807C5D
:10553800007D007E007F00800081008200830000E3
:10554800524F4D5742572020494D47000001000057
:10555800000000000000000000000000000000E55E
:105568000A001A002A003A004A005A006A007A0023
:105578008A009A00AA00BA00CA00DA00EA00FA0013
:105588000A0D20524F4D574257204C6F6164657287
:105598002076302E320D0A20526561647920746FAE
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:1055B80065782066696C650D0A205768656E2066F7
:1055C800696C65206C6F616420636F6D706C6574C5
:1055D80065642C20636F70792066696C6520746F30
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:1055F8007020746F203078300D0A000A0D426F6FEA
:1056080074696E6720524F4D5742572066726F6D0E
:0F561800204346206469736B0D0A00580D0A0089
:00000001FF

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.62"
#DEFINE BIOSVER "3.1.1-pre.67"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.62"
db "3.1.1-pre.67"
endm

2
Tools/Makefile.inc
View File

@ -35,7 +35,7 @@ DIFFPATH := $(DIFFTO)/$(RELPATH)
CASEFN = $(TOOLS)/unix/casefn.sh
ZXCC=$(BINDIR)/zx
TASM=$(BINDIR)/uz80as -t hd64180
TASM=$(BINDIR)/uz80as -t z80
OPENSPIN=$(BINDIR)/openspin
BSTC=$(BINDIR)//bstc
CPMCP=$(BINDIR)/cpmcp

1
Tools/tasm32/TASM280.TAB
View File

@ -438,6 +438,7 @@ RET PE E8 1 NOP 1
RET PO E0 1 NOP 1
RET Z C8 1 NOP 1
RETI "" 4DED 2 NOP 1
RETIL "" 55ED 2 NOP 1 /* Z280 */
RETN "" 45ED 2 NOP 1
RL (HL) 16CB 2 NOP 1

2
Tools/unix/uz80as/targets.c
View File

@ -14,6 +14,7 @@
extern const struct target s_target_z80;
extern const struct target s_target_hd64180;
extern const struct target s_target_z280;
extern const struct target s_target_gbcpu;
extern const struct target s_target_dp2200;
extern const struct target s_target_dp2200ii;
@ -40,6 +41,7 @@ extern const struct target s_target_m68hc11;
static const struct target *s_targets[] = {
&s_target_z80,
&s_target_hd64180,
&s_target_z280,
&s_target_gbcpu,
&s_target_dp2200,
&s_target_dp2200ii,

270
Tools/unix/uz80as/z80.c
View File

@ -47,146 +47,146 @@
*/
static const struct matchtab s_matchtab_z80[] = {
{ "LD b,b", "40b0c1.", 3, 0 },
{ "LD b,b", "40b0c1.", 7, 0 },
{ "LD p,p", "DD.40b0c1.", 1, 1 },
{ "LD q,q", "FD.40b0c1.", 1, 1 },
{ "LD b,(HL)", "46b0.", 3, 0 },
{ "LD b,(e)", "d1.46b0.00.", 3, 0, "ii" },
{ "LD b,(ca)", "d1.46b0.d2.", 3, 0, "ii" },
{ "LD A,I", "ED.57.", 3, 0 },
{ "LD A,R", "ED.5F.", 3, 0 },
{ "LD A,(BC)", "0A.", 3, 0 },
{ "LD A,(DE)", "1A.", 3, 0 },
{ "LD A,(a)", "3A.e0", 3, 0 },
{ "LD b,a", "06b0.d1.", 3, 0, "e8" },
{ "LD b,(HL)", "46b0.", 7, 0 },
{ "LD b,(e)", "d1.46b0.00.", 7, 0, "ii" },
{ "LD b,(ca)", "d1.46b0.d2.", 7, 0, "ii" },
{ "LD A,I", "ED.57.", 7, 0 },
{ "LD A,R", "ED.5F.", 7, 0 },
{ "LD A,(BC)", "0A.", 7, 0 },
{ "LD A,(DE)", "1A.", 7, 0 },
{ "LD A,(a)", "3A.e0", 7, 0 },
{ "LD b,a", "06b0.d1.", 7, 0, "e8" },
{ "LD p,a", "DD.06b0.d1.", 1, 1, "e8" },
{ "LD q,a", "FD.06b0.d1.", 1, 1, "e8" },
{ "LD I,A", "ED.47.", 3, 0 },
{ "LD R,A", "ED.4F.", 3, 0 },
{ "LD SP,HL", "F9.", 3, 0 },
{ "LD SP,e", "d0.F9.", 3, 0 },
{ "LD HL,(HL)", "ED.26.", 2, 0 }, // Z280
{ "LD HL,(a)", "2A.e0", 3, 0 },
{ "LD d,(a)", "ED.4Bf0.e1", 3, 0 },
{ "LD d,a", "01f0.e1", 3, 0 },
{ "LD e,(a)", "d0.2A.e1", 3, 0 },
{ "LD e,a", "d0.21.e1", 3, 0 },
{ "LD (HL),DE", "ED.1E.", 2, 0 }, // Z280
{ "LD (HL),b", "70c0.", 3, 0 },
{ "LD (HL),a", "36.d0.", 3, 0, "e8" },
{ "LD (BC),A", "02.", 3, 0 },
{ "LD (DE),A", "12.", 3, 0 },
{ "LD (e),b", "d0.70c1.00.", 3, 0, "ii" },
{ "LD (ca),b", "d0.70c2.d1.", 3, 0, "ii" },
{ "LD (e),a", "d0.36.00.d1.", 3, 0, "iie8" },
{ "LD (ca),a", "d0.36.d1.d2.", 3, 0, "iie8" },
{ "LD (a),A", "32.e0", 3, 0 },
{ "LD (a),HL", "22.e0", 3, 0 },
{ "LD (a),d", "ED.43f1.e0", 3, 0 },
{ "LD (a),e", "d1.22.e0", 3, 0 },
{ "PUSH f", "C5f0.", 3, 0 },
{ "PUSH e", "d0.E5.", 3, 0 },
{ "POP f", "C1f0.", 3, 0 },
{ "POP e", "d0.E1.", 3, 0 },
{ "EX DE,HL", "EB.", 3, 0 },
{ "EX AF,AF'", "08.", 3, 0 },
{ "EX (SP),HL", "E3.", 3, 0 },
{ "EX (SP),e", "d0.E3.", 3, 0 },
{ "EXX", "D9.", 3, 0 },
{ "LDI", "ED.A0.", 3, 0 },
{ "LDIR", "ED.B0.", 3, 0 },
{ "LDD", "ED.A8.", 3, 0 },
{ "LDDR", "ED.B8.", 3, 0 },
{ "CPI", "ED.A1.", 3, 0 },
{ "CPIR", "ED.B1.", 3, 0 },
{ "CPD", "ED.A9.", 3, 0 },
{ "CPDR", "ED.B9.", 3, 0 },
{ "ADD HL,A", "ED.6D.", 2, 0 }, // Z280
{ "ADD HL,d", "09f0.", 3, 0 },
{ "ADD IX,i", "DD.09f0.", 3, 0 },
{ "ADD IY,j", "FD.09f0.", 3, 0 },
{ "ADC HL,d", "ED.4Af0.", 3, 0 },
{ "SBC HL,d", "ED.42f0.", 3, 0 },
{ "g A,b", "m080b0c1.", 3, 0 },
{ "LD I,A", "ED.47.", 7, 0 },
{ "LD R,A", "ED.4F.", 7, 0 },
{ "LD SP,HL", "F9.", 7, 0 },
{ "LD SP,e", "d0.F9.", 7, 0 },
{ "LD HL,(HL)", "ED.26.", 4, 0 }, // Z280
{ "LD HL,(a)", "2A.e0", 7, 0 },
{ "LD d,(a)", "ED.4Bf0.e1", 7, 0 },
{ "LD d,a", "01f0.e1", 7, 0 },
{ "LD e,(a)", "d0.2A.e1", 7, 0 },
{ "LD e,a", "d0.21.e1", 7, 0 },
{ "LD (HL),DE", "ED.1E.", 4, 0 }, // Z280
{ "LD (HL),b", "70c0.", 7, 0 },
{ "LD (HL),a", "36.d0.", 7, 0, "e8" },
{ "LD (BC),A", "02.", 7, 0 },
{ "LD (DE),A", "12.", 7, 0 },
{ "LD (e),b", "d0.70c1.00.", 7, 0, "ii" },
{ "LD (ca),b", "d0.70c2.d1.", 7, 0, "ii" },
{ "LD (e),a", "d0.36.00.d1.", 7, 0, "iie8" },
{ "LD (ca),a", "d0.36.d1.d2.", 7, 0, "iie8" },
{ "LD (a),A", "32.e0", 7, 0 },
{ "LD (a),HL", "22.e0", 7, 0 },
{ "LD (a),d", "ED.43f1.e0", 7, 0 },
{ "LD (a),e", "d1.22.e0", 7, 0 },
{ "PUSH f", "C5f0.", 7, 0 },
{ "PUSH e", "d0.E5.", 7, 0 },
{ "POP f", "C1f0.", 7, 0 },
{ "POP e", "d0.E1.", 7, 0 },
{ "EX DE,HL", "EB.", 7, 0 },
{ "EX AF,AF'", "08.", 7, 0 },
{ "EX (SP),HL", "E3.", 7, 0 },
{ "EX (SP),e", "d0.E3.", 7, 0 },
{ "EXX", "D9.", 7, 0 },
{ "LDI", "ED.A0.", 7, 0 },
{ "LDIR", "ED.B0.", 7, 0 },
{ "LDD", "ED.A8.", 7, 0 },
{ "LDDR", "ED.B8.", 7, 0 },
{ "CPI", "ED.A1.", 7, 0 },
{ "CPIR", "ED.B1.", 7, 0 },
{ "CPD", "ED.A9.", 7, 0 },
{ "CPDR", "ED.B9.", 7, 0 },
{ "ADD HL,A", "ED.6D.", 4, 0 }, // Z280
{ "ADD HL,d", "09f0.", 7, 0 },
{ "ADD IX,i", "DD.09f0.", 7, 0 },
{ "ADD IY,j", "FD.09f0.", 7, 0 },
{ "ADC HL,d", "ED.4Af0.", 7, 0 },
{ "SBC HL,d", "ED.42f0.", 7, 0 },
{ "g A,b", "m080b0c1.", 7, 0 },
{ "g A,p", "DD.m080b0c1.", 1, 1 },
{ "g A,q", "FD.m080b0c1.", 1, 1 },
{ "g A,(HL)", "m086b0.", 3, 0 },
{ "g A,(ca)", "m0d1.86b0.d2.", 3, 0, "ii" },
{ "g A,a", "m0C6b0.d1.", 3, 0, "e8" },
{ "g b", "n080b0c1.", 3, 0 },
{ "g A,(HL)", "m086b0.", 7, 0 },
{ "g A,(ca)", "m0d1.86b0.d2.", 7, 0, "ii" },
{ "g A,a", "m0C6b0.d1.", 7, 0, "e8" },
{ "g b", "n080b0c1.", 7, 0 },
{ "g p", "DD.n080b0c1.", 1, 1 },
{ "g q", "FD.n080b0c1.", 1, 1 },
{ "g (HL)", "n086b0.", 3, 0 },
{ "g (ca)", "n0d1.86b0.d2.", 3, 0, "ii" },
{ "g a", "n0C6b0.d1.", 3, 0, "e8" },
{ "h b", "04b1c0.", 3, 0 },
{ "g (HL)", "n086b0.", 7, 0 },
{ "g (ca)", "n0d1.86b0.d2.", 7, 0, "ii" },
{ "g a", "n0C6b0.d1.", 7, 0, "e8" },
{ "h b", "04b1c0.", 7, 0 },
{ "h p", "DD.04b1c0.", 1, 1 },
{ "h q", "FD.04b1c0.", 1, 1 },
{ "h (HL)", "34c0.", 3, 0 },
{ "h (ca)", "d1.34c0.d2.", 3, 0, "ii" },
{ "h (e)", "d1.34c0.00.", 3, 0, "ii" },
{ "INC d", "03f0.", 3, 0 },
{ "INC e", "d0.23.", 3, 0 },
{ "DEC d", "0Bf0.", 3, 0 },
{ "DEC e", "d0.2B.", 3, 0 },
{ "DAA", "27.", 3, 0 },
{ "CPL", "2F.", 3, 0 },
{ "NEG", "ED.44.", 3, 0 },
{ "CCF", "3F.", 3, 0 },
{ "SCF", "37.", 3, 0 },
{ "NOP", "00.", 3, 0 },
{ "HALT", "76.", 3, 0 },
{ "DI", "F3.", 3, 0 },
{ "EI", "FB.", 3, 0 },
{ "IM a", "ED.k0.", 3, 0, "tt" },
{ "RLCA", "07.", 3, 0 },
{ "RLA", "17.", 3, 0 },
{ "RRCA", "0F.", 3, 0 },
{ "RRA", "1F.", 3, 0 },
{ "h (HL)", "34c0.", 7, 0 },
{ "h (ca)", "d1.34c0.d2.", 7, 0, "ii" },
{ "h (e)", "d1.34c0.00.", 7, 0, "ii" },
{ "INC d", "03f0.", 7, 0 },
{ "INC e", "d0.23.", 7, 0 },
{ "DEC d", "0Bf0.", 7, 0 },
{ "DEC e", "d0.2B.", 7, 0 },
{ "DAA", "27.", 7, 0 },
{ "CPL", "2F.", 7, 0 },
{ "NEG", "ED.44.", 7, 0 },
{ "CCF", "3F.", 7, 0 },
{ "SCF", "37.", 7, 0 },
{ "NOP", "00.", 7, 0 },
{ "HALT", "76.", 7, 0 },
{ "DI", "F3.", 7, 0 },
{ "EI", "FB.", 7, 0 },
{ "IM a", "ED.k0.", 7, 0, "tt" },
{ "RLCA", "07.", 7, 0 },
{ "RLA", "17.", 7, 0 },
{ "RRCA", "0F.", 7, 0 },
{ "RRA", "1F.", 7, 0 },
{ "SLL b", "CB.30c0.", 1, 1 },
{ "SLL (HL)", "CB.36.", 1, 1 },
{ "SLL (ca)", "d0.CB.d1.36.", 1, 1, "ii" },
{ "SLL (ca),b", "d0.CB.d1.30c2.", 1, 1, "ii" },
{ "k b", "CB.00b0c1.", 3, 0 },
{ "k (HL)", "CB.06b0.", 3, 0 },
{ "k (ca)", "d1.CB.d2.06b0.", 3, 0, "ii" },
{ "k b", "CB.00b0c1.", 7, 0 },
{ "k (HL)", "CB.06b0.", 7, 0 },
{ "k (ca)", "d1.CB.d2.06b0.", 7, 0, "ii" },
{ "k (ca),b", "d1.CB.d2.00b0c3.", 1, 1, "ii" },
{ "RLD", "ED.6F.", 3, 0 },
{ "RRD", "ED.67.", 3, 0 },
{ "l a,b", "CB.00g0b1c2.", 3, 0, "b3" },
{ "l a,(HL)", "CB.06g0b1.", 3, 0, "b3" },
{ "l a,(ca)", "d2.CB.d3.06g0b1.", 3, 0, "b3ii" },
{ "RLD", "ED.6F.", 7, 0 },
{ "RRD", "ED.67.", 7, 0 },
{ "l a,b", "CB.00g0b1c2.", 7, 0, "b3" },
{ "l a,(HL)", "CB.06g0b1.", 7, 0, "b3" },
{ "l a,(ca)", "d2.CB.d3.06g0b1.", 7, 0, "b3ii" },
{ "RES a,(ca),b", "d1.CB.d2.80b0c3.", 1, 1, "b3ii" },
{ "SET a,(ca),b", "d1.CB.d2.C0b0c3.", 1, 1, "b3ii" },
{ "JP (HL)", "E9.", 3, 0 },
{ "JP (e)", "d0.E9.", 3, 0 },
{ "JP m,a", "C2b0.e1", 3, 0 },
{ "JP a", "C3.e0", 3, 0 },
{ "JR n,a", "20b0.i1.", 3, 0, "r8" },
{ "JR a", "18.i0.", 3, 0, "r8" },
{ "DJNZ a", "10.i0.", 3, 0, "r8" },
{ "CALL m,a", "C4b0.e1", 3, 0 },
{ "CALL a", "CD.e0", 3, 0 },
{ "RETI", "ED.4D.", 3, 0 },
{ "RETN", "ED.45.", 3, 0 },
{ "RET m", "C0b0.", 3, 0 },
{ "RET", "C9.", 3, 0 },
{ "RST a", "C7j0.", 3, 0, "ss" },
{ "IN b,(C)", "ED.40b0.", 3, 0 },
{ "IN A,(a)", "DB.d0.", 3, 0, "e8" },
{ "IN F,(a)", "ED.70.", 3, 0 },
{ "JP (HL)", "E9.", 7, 0 },
{ "JP (e)", "d0.E9.", 7, 0 },
{ "JP m,a", "C2b0.e1", 7, 0 },
{ "JP a", "C3.e0", 7, 0 },
{ "JR n,a", "20b0.i1.", 7, 0, "r8" },
{ "JR a", "18.i0.", 7, 0, "r8" },
{ "DJNZ a", "10.i0.", 7, 0, "r8" },
{ "CALL m,a", "C4b0.e1", 7, 0 },
{ "CALL a", "CD.e0", 7, 0 },
{ "RETI", "ED.4D.", 7, 0 },
{ "RETN", "ED.45.", 7, 0 },
{ "RET m", "C0b0.", 7, 0 },
{ "RET", "C9.", 7, 0 },
{ "RST a", "C7j0.", 7, 0, "ss" },
{ "IN b,(C)", "ED.40b0.", 7, 0 },
{ "IN A,(a)", "DB.d0.", 7, 0, "e8" },
{ "IN F,(a)", "ED.70.", 7, 0 },
{ "IN (C)", "ED.70.", 1, 1 },
{ "INI", "ED.A2.", 3, 0 },
{ "INIR", "ED.B2.", 3, 0 },
{ "IND", "ED.AA.", 3, 0 },
{ "INDR", "ED.BA.", 3, 0 },
{ "INI", "ED.A2.", 7, 0 },
{ "INIR", "ED.B2.", 7, 0 },
{ "IND", "ED.AA.", 7, 0 },
{ "INDR", "ED.BA.", 7, 0 },
{ "OUT (C),0", "ED.71.", 1, 1 },
{ "OUT (C),b", "ED.41b0.", 3, 0 },
{ "OUT (a),A", "D3.d0.", 3, 0, "e8" },
{ "OUTI", "ED.A3.", 3, 0 },
{ "OTIR", "ED.B3.", 3, 0 },
{ "OUTD", "ED.AB.", 3, 0 },
{ "OTDR", "ED.BB.", 3, 0 },
{ "OUT (C),b", "ED.41b0.", 7, 0 },
{ "OUT (a),A", "D3.d0.", 7, 0, "e8" },
{ "OUTI", "ED.A3.", 7, 0 },
{ "OTIR", "ED.B3.", 7, 0 },
{ "OUTD", "ED.AB.", 7, 0 },
{ "OTDR", "ED.BB.", 7, 0 },
/* hd64180 added instructions */
{ "IN0 b,(a)", "ED.00b0.d1.", 2, 0, "e8" },
{ "OUT0 (a),b", "ED.01b1.d0.", 2, 0, "e8" },
@ -201,14 +201,15 @@ static const struct matchtab s_matchtab_z80[] = {
{ "TST a", "ED.64.d0.", 2, 0, "e8" },
{ "TSTIO a", "ED.74.d0.", 2, 0, "e8" },
/* Z280 added instructions */
{ "PCACHE", "ED.65.", 2, 0 },
{ "LDCTL (C),HL", "ED.6E.", 2, 0 },
{ "LDCTL HL,(C)", "ED.66.", 2, 0 },
{ "LDCTL USP,HL", "ED.8F.", 2, 0 },
{ "LDCTL IY,(C)", "FD.ED.66.", 2, 0 },
{ "LDCTL (C),IY", "FD.ED.6E.", 2, 0 },
{ "MULTU A,a", "FD.ED.F9.d0.", 2, 0 },
{ "OUTW (C),HL", "ED.BF.", 2, 0 },
{ "PCACHE", "ED.65.", 4, 0 },
{ "LDCTL (C),HL", "ED.6E.", 4, 0 },
{ "LDCTL HL,(C)", "ED.66.", 4, 0 },
{ "LDCTL USP,HL", "ED.8F.", 4, 0 },
{ "LDCTL IY,(C)", "FD.ED.66.", 4, 0 },
{ "LDCTL (C),IY", "FD.ED.6E.", 4, 0 },
{ "MULTU A,a", "FD.ED.F9.d0.", 4, 0 },
{ "OUTW (C),HL", "ED.BF.", 4, 0 },
{ "RETIL", "ED.55.", 4, 0 },
{ NULL, NULL },
};
@ -374,3 +375,14 @@ const struct target s_target_hd64180 = {
.pat_next_str = pat_next_str_z80,
.mask = 2
};
const struct target s_target_z280 = {
.id = "z280",
.descr = "Zilog Z280",
.matcht = s_matchtab_z80,
.matchf = match_z80,
.genf = gen_z80,
.pat_char_rewind = pat_char_rewind_z80,
.pat_next_str = pat_next_str_z80,
.mask = 4
};

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