Merge pull request #310 from b1ackmai1er/dev

ym2612 stub and minors
3 years ago · e83e26b6db
23 changed files with 383 additions and 10 deletions
--- a/Source/Doc/Architecture.md
+++ b/Source/Doc/Architecture.md
@ -921,7 +921,7 @@ device number assigned by the driver.
 Each RTC device is handled by an appropriate driver (DSRTC, BQRTC,
 etc.) which is identified by a device type id from the table below.

-**Type ID** | **Disk Device Type**
+**Type ID** | **RTC Device Type**
 ----------- | --------------------
 0x00        | DS1302
 0x10        | BQ4845P
--- a/Source/HBIOS/Config/SBC_max.asm
+++ b/Source/HBIOS/Config/SBC_max.asm
@ -62,6 +62,8 @@ SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 ;
 PRPENABLE	.SET	TRUE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
-AY38910ENABLE	.SET	TRUE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER (AY38910.ASM)
 ;
-SN76489ENABLE	.SET	TRUE		; SN : SN76489 DRIVER
+SN76489ENABLE	.SET	TRUE		; SN: ENABLE SN76489 SOUND DRIVER (SN76489.ASM)
+;
+YM2612ENABLE	.SET	TRUE		; YM2612: ENABLE ECB VGM YM2612 SOUND DRIVER (YM2612.ASM)
--- a/Source/HBIOS/audio.inc
+++ b/Source/HBIOS/audio.inc
@ -46,7 +46,7 @@ AUD_NOTE:
 	LD	DE, 48
 	CALL	DIV16
 					; BC IS OCTAVE COUNT
-					; HL is NOTE WITIN OCTAVE
+					; HL is NOTE WITHIN OCTAVE
 	ADD	HL, HL
 	pop	de
 	ADD	HL, DE
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@ -210,3 +210,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@ -254,3 +254,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@ -334,3 +334,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@ -258,3 +258,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
+
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@ -260,3 +260,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@ -255,3 +255,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@ -267,3 +267,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@ -282,3 +282,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@ -274,3 +274,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@ -255,3 +255,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@ -258,3 +258,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@ -262,3 +262,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@ -186,3 +186,6 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@ -194,7 +194,9 @@ SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@ -112,7 +112,7 @@ CTC_PREINIT1:
 ;
 	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
 	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
-	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
+	; START OF THE IVT, SO THE FIRST FOUR ENTRIES OF THE
 	; IVT CORRESPOND TO CTC CHANNELS A-D.
 	LD	A,INT_CTC0A * 2
 	OUT	(CTCBASE),A		; SETUP CTC BASE INT VECTOR
--- a/Source/HBIOS/ds7rtc.asm
+++ b/Source/HBIOS/ds7rtc.asm
@ -325,7 +325,7 @@ DS7_RL1:CALL	PCF_READI2C
 ;
 #IF (0)
 	LD	A,8
-	LD	DE,DS7_BUF	; DISLAY DATA READ
+	LD	DE,DS7_BUF	; DISPLAY DATA READ
 	CALL	PRTHEXBUF	; 
 	CALL   	NEWLINE
 #ENDIF
--- a/Source/HBIOS/dsky.asm
+++ b/Source/HBIOS/dsky.asm
@ -3,7 +3,7 @@
 ; DSKY (DISPLAY AND KEYBOARD) ROUTINES 
 ;==================================================================================================
 ;
-; THE DSKY MAY COSESIDE ON THE SAME PPI BUS AS A PPISD.  IT MAY NOT
+; THE DSKY MAY COINCIDE ON THE SAME PPI BUS AS A PPISD.  IT MAY NOT
 ; SHARE A PPI BUS WITH A PPIDE.  SEE PPI_BUS.TXT FOR MORE INFORMATION.
 ;
 ; LED SEGMENTS (BIT VALUES)
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@ -2979,6 +2979,9 @@ HB_INITTBL:
 #IF (SN76489ENABLE)
 	.DW	SN76489_INIT
 #ENDIF
+#IF (YM2612ENABLE)
+	.DW	YM2612_INIT
+#ENDIF
 #IF (SPKENABLE)
 	.DW	SP_INIT			; AUDIBLE INDICATOR OF BOOT START
 #ENDIF
@ -3082,7 +3085,6 @@ HB_INITTBL:
 #IF (PPPENABLE)
 	.DW	PPP_INIT
 #ENDIF
-
 ;
 HB_INITTBLLEN	.EQU	(($ - HB_INITTBL) / 2)
 ;
@ -6174,6 +6176,14 @@ SIZ_AY38910	.EQU	$ - ORG_AY38910
 		.ECHO	SIZ_AY38910
 		.ECHO	" bytes.\n"
 #ENDIF
+#IF (YM2612ENABLE)
+ORG_YM2612	.EQU	$
+  #INCLUDE "ym2612.asm"
+SIZ_YM2612	.EQU	$ - ORG_YM2612
+		.ECHO	"YM2612 occupies "
+		.ECHO	SIZ_YM2612
+		.ECHO	" bytes.\n"
+#ENDIF
 ;
 		.ECHO	"RTCDEF="
 		.ECHO	RTCDEF
--- a/Source/HBIOS/pio_ps.asm
+++ b/Source/HBIOS/pio_ps.asm
@ -605,7 +605,7 @@ PIOMIVT(PIO3IN,PI3_IST,PRTTAB+3)
 #DEFCONT ;\
 #DEFCONT ;	WAIT FOR SPACE FOR THE CHARACTER\
 #DEFCONT ;	IF WE ARE WAITING FOR A		\
-#DEFCONT ;	CHARACTRE THEN OUTPUT IT NOW	\
+#DEFCONT ;	CHARACTER THEN OUTPUT IT NOW	\
 #DEFCONT ;	OTHERWISE STORE IT UNTIL THE	\
 #DEFCONT ;	INTERRUPT CALLS FOR IT		\
 #DEFCONT ;\
--- a/Source/HBIOS/ym2612.asm
+++ b/Source/HBIOS/ym2612.asm
@ -0,0 +1,319 @@
+;======================================================================
+;	YM2612 sound driver
+;
+;	WRITTEN BY: PHIL SUMMERS
+;======================================================================
+;
+; PRESENTLY THIS IS JUST A STUB TO MUTE OUTPUT
+;
+;======================================================================
+; 
+;======================================================================
+;
+YMSEL		.EQU	VGMBASE+00H		; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.EQU	VGMBASE+01H		; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.EQU	VGMBASE+02H		; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.EQU	VGMBASE+03H		; Secondary YM2162 11000011 a1=1 a0=1
+;
+YM_CLR		.EQU	FALSE			; Set to clear all registers
+;
+;------------------------------------------------------------------------------
+; YM2162 Mute
+;------------------------------------------------------------------------------
+;
+YM2612_INIT:	ld	hl,s1			; Start of register list to write
+
+		ld	b,+(s2-s1)/2
+pt1:		call	set1			; [1]
+		djnz	pt1
+
+		ld	b,+(s3-s2)/2
+pt2:		call	set2			; [2]
+		djnz	pt2
+
+		ld	b,+(s4-s3)/2
+pt3:		call	set1			; [1]
+		djnz	pt3
+
+		ld	b,+(s5-s4)/2
+pt4:		call	set2			; [2]
+		djnz	pt4
+
+		ret
+
+set1:		ld	a,(hl)			; YM2162 Register write
+		inc	hl			; Register bank [1]
+		out	(YMSEL),a
+		ld	a,(hl)
+		inc	hl
+		out	(YMDAT),a
+		push	bc
+		ld	b,0			; check
+set1a:		in	a,(YMSEL)       	; device
+		rlca                    	; ready
+		jp	nc,set1b        	; with
+		djnz	set1a           	; timeout
+		; timed out
+set1b:		pop	bc
+		ret
+;
+set2:		ld	a,(hl)			; YM2162 Register write
+		inc	hl			; Register Bank [2]
+		out	(YM2SEL),a
+		ld	a,(hl)
+		inc	hl
+		out	(YM2DAT),a
+		push	bc			; check
+		ld	b,0			; device
+set2a:		in	a,(YM2SEL)		; ready
+		rlca				; with
+		jp	nc,set2b		; timeout
+		djnz	set2a
+		; timed out
+set2b:		pop	bc
+		ret
+
+s1:		.db	$22,$00			; [1] lfo off
+
+		.db	$27,$00			; [1] Disable independant Channel 3
+		.db	$28,$00			; [1] note off ch 1
+		.db	$28,$01			; [1] note off ch 2
+		.db	$28,$02			; [1] note off ch 3
+		.db	$28,$04			; [1] note off ch 4
+		.db	$28,$05			; [1] note off ch 5
+		.db	$28,$06			; [1] note off ch 6
+		.db	$2b,$00			; [1] dac off
+
+		.db	$b4,$00			; [1] sound off ch 1-3
+		.db	$b5,$00	
+		.db	$b6,$00	
+
+s2:		.db	$b4,$00			; [2] sound off ch 4-6
+		.db	$b5,$00			; [2] 
+		.db	$b6,$00			; [2] 
+
+s3:		.db	$40,$7f			; [1] ch 1-3 total level minimum
+		.db	$41,$7f			; [1] 
+		.db	$42,$7f			; [1] 
+		.db	$44,$7f			; [1] 
+		.db	$45,$7f			; [1] 
+		.db	$46,$7f			; [1] 
+		.db	$48,$7f			; [1] 
+		.db	$49,$7f			; [1] 
+		.db	$4a,$7f			; [1] 
+		.db	$4c,$7f			; [1] 
+		.db	$4d,$7f			; [1] 
+		.db	$4e,$7f			; [1] 
+s4:
+		.db	$40,$7f			; [2] ch 4-6 total level minimum
+		.db	$41,$7f			; [2]
+		.db	$42,$7f			; [2]
+		.db	$44,$7f			; [2]
+		.db	$45,$7f			; [2]
+		.db	$46,$7f			; [2]
+		.db	$48,$7f			; [2]
+		.db	$49,$7f			; [2]
+		.db	$4a,$7f			; [2]
+		.db	$4c,$7f			; [2]
+		.db	$4d,$7f			; [2]
+		.db	$4e,$7f			; [2]
+s5:
+#IF (YM_CLR)
+		.db	$2a,$00			; [1]	; dac value
+ 
+		.db	$24,$00			; [1]	; timer A frequency
+		.db	$25,$00			; [1]	; timer A frequency
+		.db	$26,$00			; [1]	; time B frequency
+
+		.db	$30,$00			; [1]	; ch 1-3 multiply & detune
+		.db	$31,$00	                ; [1]
+		.db	$32,$00	                ; [1]
+		.db	$34,$00	                ; [1]
+		.db	$35,$00	                ; [1]
+		.db	$36,$00	                ; [1]
+		.db	$38,$00	                ; [1]
+		.db	$39,$00	                ; [1]
+		.db	$3a,$00	                ; [1]
+		.db	$3c,$00	                ; [1]
+		.db	$3d,$00	                ; [1]
+		.db	$3e,$00	                ; [1]
+s6:
+		.db	$30,$00			; [2] ch 4-6 multiply & detune
+		.db	$31,$00			; [2]
+		.db	$32,$00			; [2]
+		.db	$34,$00			; [2]
+		.db	$35,$00			; [2]
+		.db	$36,$00			; [2]
+		.db	$38,$00			; [2]
+		.db	$39,$00			; [2]
+		.db	$3a,$00			; [2]
+		.db	$3c,$00			; [2]
+		.db	$3d,$00			; [2]
+		.db	$3e,$00			; [2]
+s7:                             			
+		.db	$50,$00	                ; [1] ch 1-3 attack rate and scaling
+		.db	$51,$00	                ; [1]
+		.db	$52,$00	                ; [1]
+		.db	$54,$00	                ; [1]
+		.db	$55,$00	                ; [1]
+		.db	$56,$00	                ; [1]
+		.db	$58,$00	                ; [1]
+		.db	$59,$00	                ; [1]
+		.db	$5a,$00	                ; [1]
+		.db	$5c,$00	                ; [1]
+		.db	$5d,$00	                ; [1]
+		.db	$5e,$00	                ; [1]
+s8:
+		.db	$50,$00			; [2] ch 4-6 attack rate and scaling
+		.db	$51,$00			; [2]
+		.db	$52,$00			; [2]
+		.db	$54,$00			; [2]
+		.db	$55,$00			; [2]
+		.db	$56,$00			; [2]
+		.db	$58,$00			; [2]
+		.db	$59,$00			; [2]
+		.db	$5a,$00			; [2]
+		.db	$5c,$00			; [2]
+		.db	$5d,$00			; [2]
+		.db	$5e,$00			; [2]
+s9:
+		.db	$60,$00	                ; [1] ch 1-3 decay rate and am enable
+		.db	$61,$00	                ; [1]
+		.db	$62,$00	                ; [1]
+		.db	$64,$00	                ; [1]
+		.db	$65,$00	                ; [1]
+		.db	$66,$00	                ; [1]
+		.db	$68,$00	                ; [1]
+		.db	$69,$00	                ; [1]
+		.db	$6a,$00	                ; [1]
+		.db	$6c,$00	                ; [1]
+		.db	$6d,$00	                ; [1]
+		.db	$6e,$00	                ; [1]
+s10:
+		.db	$60,$00			; [2] ch 4-6 decay rate and am enable
+		.db	$61,$00			; [2]
+		.db	$62,$00			; [2]
+		.db	$64,$00			; [2]
+		.db	$65,$00			; [2]
+		.db	$66,$00			; [2]
+		.db	$68,$00			; [2]
+		.db	$69,$00			; [2]
+		.db	$6a,$00			; [2]
+		.db	$6c,$00			; [2]
+		.db	$6d,$00			; [2]
+		.db	$6e,$00			; [2]
+s11:
+		.db	$70,$00	                ; [1] ch 1-3 sustain rate
+		.db	$71,$00	                ; [1]
+		.db	$72,$00	                ; [1]
+		.db	$74,$00	                ; [1]
+		.db	$75,$00	                ; [1]
+		.db	$76,$00	                ; [1]
+		.db	$78,$00	                ; [1]
+		.db	$79,$00	                ; [1]
+		.db	$7a,$00	                ; [1]
+		.db	$7c,$00	                ; [1]
+		.db	$7d,$00	                ; [1]
+		.db	$7e,$00	                ; [1]
+s12:
+		.db	$70,$00			; [2] ch 4-6 sustain rate
+		.db	$71,$00			; [2]
+		.db	$72,$00			; [2]
+		.db	$74,$00			; [2]
+		.db	$75,$00			; [2]
+		.db	$76,$00			; [2]
+		.db	$78,$00			; [2]
+		.db	$79,$00			; [2]
+		.db	$7a,$00			; [2]
+		.db	$7c,$00			; [2]
+		.db	$7d,$00			; [2]
+		.db	$7e,$00			; [2]
+s13:
+		.db	$80,$00	                ; [1] ch 1-3 release rate and sustain level
+		.db	$81,$00	                ; [1]
+		.db	$82,$00	                ; [1]
+		.db	$84,$00	                ; [1]
+		.db	$85,$00	                ; [1]
+		.db	$86,$00	                ; [1]
+		.db	$88,$00	                ; [1]
+		.db	$89,$00	                ; [1]
+		.db	$8a,$00	                ; [1]
+		.db	$8c,$00	                ; [1]
+		.db	$8d,$00	                ; [1]
+		.db	$8e,$00	                ; [1]
+s14:
+		.db	$80,$00			; [2] ch 4-6 release rate and sustain level
+		.db	$81,$00			; [2]
+		.db	$82,$00			; [2]
+		.db	$84,$00			; [2]
+		.db	$85,$00			; [2]
+		.db	$86,$00			; [2]
+		.db	$88,$00			; [2]
+		.db	$89,$00			; [2]
+		.db	$8a,$00			; [2]
+		.db	$8c,$00			; [2]
+		.db	$8d,$00			; [2]
+		.db	$8e,$00			; [2]
+s15:
+		.db	$90,$00	                ; [1] ch 1-3 ssg-eg
+		.db	$91,$00	                ; [1]
+		.db	$92,$00	                ; [1]
+		.db	$94,$00	                ; [1]
+		.db	$95,$00	                ; [1]
+		.db	$96,$00	                ; [1]
+		.db	$98,$00	                ; [1]
+		.db	$99,$00	                ; [1]
+		.db	$9a,$00	                ; [1]
+		.db	$9c,$00	                ; [1]
+		.db	$9d,$00	                ; [1]
+		.db	$9e,$00	                ; [1]
+s16:
+		.db	$90,$00			; [2] ch 4-6 ssg-eg
+		.db	$91,$00			; [2]
+		.db	$92,$00			; [2]
+		.db	$94,$00			; [2]
+		.db	$95,$00			; [2]
+		.db	$96,$00			; [2]
+		.db	$98,$00			; [2]
+		.db	$99,$00			; [2]
+		.db	$9a,$00			; [2]
+		.db	$9c,$00			; [2]
+		.db	$9d,$00			; [2]
+		.db	$9e,$00			; [2]
+s17:
+		.db	$a0,$00	                ; [1] ch 1-3 frequency
+		.db	$a1,$00	                ; [1]
+		.db	$a2,$00	                ; [1]
+		.db	$a4,$00	                ; [1]
+		.db	$a5,$00	                ; [1]
+		.db	$a6,$00	                ; [1]
+;		.db	$a8,$00	                ; [1] ch 3 special mode
+;		.db	$a9,$00	                ; [1]
+;		.db	$aa,$00	                ; [1]
+;		.db	$ac,$00	                ; [1]
+;		.db	$ad,$00	                ; [1]
+;		.db	$ae,$00	                ; [1]
+s18:
+		.db	$a0,$00			; [2] ch 4-6 frequency
+		.db	$a1,$00			; [2]
+		.db	$a2,$00			; [2]
+		.db	$a4,$00			; [2]
+		.db	$a5,$00			; [2]
+		.db	$a6,$00			; [2]
+;		.db	$a8,$00			; [2] ch 3 special mode
+;		.db	$a9,$00			; [2]
+;		.db	$aa,$00			; [2]
+;		.db	$ac,$00			; [2]
+;		.db	$ad,$00			; [2]
+;		.db	$ae,$00			; [2]
+s19:
+		.db	$b0,$00	                ; [1] ch 1-3 algorith + feedback
+		.db	$b1,$00	                ; [1]
+		.db	$b2,$00	                ; [1]
+s20:
+		.db	$b0,$00			; [2] ch 4-6 algorith + feedback
+		.db	$b1,$00			; [2]
+		.db	$b2,$00			; [2]
+s21:
+#ENDIF
+