diff --git a/Binary/Apps/Tunes/Clean.cmd b/Binary/Apps/Tunes/Clean.cmd
index b57e2e0c..3039d346 100644
--- a/Binary/Apps/Tunes/Clean.cmd
+++ b/Binary/Apps/Tunes/Clean.cmd
@@ -2,3 +2,4 @@
 setlocal
 
 if exist *.pt? del *.pt?
+if exist *.mym del *.mym
diff --git a/Binary/Apps/Tunes/Demo.mym b/Binary/Apps/Tunes/Demo.mym
deleted file mode 100644
index 255fc160..00000000
Binary files a/Binary/Apps/Tunes/Demo.mym and /dev/null differ
diff --git a/Binary/Apps/Tunes/Demo1.mym b/Binary/Apps/Tunes/Demo1.mym
deleted file mode 100644
index b224f321..00000000
Binary files a/Binary/Apps/Tunes/Demo1.mym and /dev/null differ
diff --git a/Binary/Apps/Tunes/Demo3.mym b/Binary/Apps/Tunes/Demo3.mym
deleted file mode 100644
index 808db891..00000000
Binary files a/Binary/Apps/Tunes/Demo3.mym and /dev/null differ
diff --git a/Binary/Apps/Tunes/Demo3mix.mym b/Binary/Apps/Tunes/Demo3mix.mym
deleted file mode 100644
index b5981848..00000000
Binary files a/Binary/Apps/Tunes/Demo3mix.mym and /dev/null differ
diff --git a/Binary/Apps/Tunes/Demo4.mym b/Binary/Apps/Tunes/Demo4.mym
deleted file mode 100644
index ed2e8a85..00000000
Binary files a/Binary/Apps/Tunes/Demo4.mym and /dev/null differ
diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index 5a485c7b..3247befe 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -23,6 +23,7 @@ Version 2.9.2
 - WBW: DSRTC now detects DS-1302 presence dynamically
 - WBW: SC126 platform renamed to SCZ180 w/ configs for SC126, SC130
 - WBW: Add status LED support
+- WBW: Add support for secondry SPI (SD Card) on SC126
 
 Version 2.9.1
 -------------
diff --git a/ReadMe.txt b/ReadMe.txt
index 53dcb871..cbd34453 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre.13, 2019-10-02
+Version 2.9.2-pre.16, 2019-10-09
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
diff --git a/Source/Apps/FAT/FAT.COM b/Source/Apps/FAT/FAT.COM
index 4bd4cc70..2fcfc9e7 100644
Binary files a/Source/Apps/FAT/FAT.COM and b/Source/Apps/FAT/FAT.COM differ
diff --git a/Source/Apps/FAT/ReadMe.txt b/Source/Apps/FAT/ReadMe.txt
index e3c60813..844bc673 100644
--- a/Source/Apps/FAT/ReadMe.txt
+++ b/Source/Apps/FAT/ReadMe.txt
@@ -1,7 +1,7 @@
 RomWBW HBIOS CP/M FAT Utility ("FAT.COM")
 
 Author: Wayne Warthen
-Updated: 8-May-2019
+Updated: 8-Oct-2019
 
 Application to manipulate and exchange files with a FAT (DOS)
 filesystem.  Runs on any HBIOS hosted CP/M implementation.
@@ -92,3 +92,4 @@ HISTORY:
  2-May-2019: v0.9 initial release (beta)
  7-May-2019: v0.9.1 added REN and DEL (beta)
  8-May-2019: v0.9.2 handle file collisions w/ user prompt (beta)
+ 8-Oct-2019: v0.9.3 fixed incorrect filename buffer size (MAX_FN)
diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc
index 30e053b4..fd9cafab 100644
--- a/Source/CBIOS/ver.inc
+++ b/Source/CBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.13"
+#DEFINE BIOSVER	"2.9.2-pre.16"
diff --git a/Source/HBIOS/Config/EZZ80_std.asm b/Source/HBIOS/Config/EZZ80_std.asm
index dd0c4da6..b69ab59d 100644
--- a/Source/HBIOS/Config/EZZ80_std.asm
+++ b/Source/HBIOS/Config/EZZ80_std.asm
@@ -25,4 +25,6 @@
 #include "cfg_ezz80.asm"
 ;
 CPUOSC		.SET	10000000	; CPU OSC FREQ IN MHZ
-DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+;SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+;SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
diff --git a/Source/HBIOS/Config/RCZ180_ext.asm b/Source/HBIOS/Config/RCZ180_ext.asm
index 6966fa07..a7a449f7 100644
--- a/Source/HBIOS/Config/RCZ180_ext.asm
+++ b/Source/HBIOS/Config/RCZ180_ext.asm
@@ -33,6 +33,9 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
+;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
+;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
diff --git a/Source/HBIOS/Config/RCZ180_nat.asm b/Source/HBIOS/Config/RCZ180_nat.asm
index 1e70e1fa..74dc43f5 100644
--- a/Source/HBIOS/Config/RCZ180_nat.asm
+++ b/Source/HBIOS/Config/RCZ180_nat.asm
@@ -33,6 +33,9 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
+;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
+;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
diff --git a/Source/HBIOS/Config/RCZ80_kio.asm b/Source/HBIOS/Config/RCZ80_kio.asm
index fdbc29e0..45d7637b 100644
--- a/Source/HBIOS/Config/RCZ80_kio.asm
+++ b/Source/HBIOS/Config/RCZ80_kio.asm
@@ -34,12 +34,15 @@ CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.SET	KIOBASE+$04	; CTC BASE I/O ADDRESS
 ;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.SET	SIOMODE_EZZ80	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.SET	KIOBASE+$08	; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.SET	1843200		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCLK	.SET	1843200		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+;SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+;SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
diff --git a/Source/HBIOS/Config/RCZ80_std.asm b/Source/HBIOS/Config/RCZ80_std.asm
index 6ec8193d..b990c968 100644
--- a/Source/HBIOS/Config/RCZ80_std.asm
+++ b/Source/HBIOS/Config/RCZ80_std.asm
@@ -25,10 +25,14 @@
 #include "cfg_rcz80.asm"
 ;
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
-DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;ACIA0CFG	.SET	SER_115200_8N1	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+;ACIA1CFG	.SET	SER_115200_8N1	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+;SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 ;
 FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
diff --git a/Source/HBIOS/Config/SCZ180_126.asm b/Source/HBIOS/Config/SCZ180_126.asm
index 7894206c..4b6e44e8 100644
--- a/Source/HBIOS/Config/SCZ180_126.asm
+++ b/Source/HBIOS/Config/SCZ180_126.asm
@@ -33,6 +33,9 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
+;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
+;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
@@ -45,3 +48,5 @@ IDEMODE		.SET	IDEMODE_RC	; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 ;
 SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+
diff --git a/Source/HBIOS/Config/SCZ180_130.asm b/Source/HBIOS/Config/SCZ180_130.asm
index ebe53ba9..5ef52318 100644
--- a/Source/HBIOS/Config/SCZ180_130.asm
+++ b/Source/HBIOS/Config/SCZ180_130.asm
@@ -35,6 +35,9 @@ Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;ASCI0CFG	.SET	SER_115200_8N1	; ASCI 0: SERIAL LINE CONFIG
+;ASCI1CFG	.SET	SER_115200_8N1	; ASCI 1: SERIAL LINE CONFIG
+;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index be94d948..94402b1f 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -691,7 +691,7 @@ ACIA0_CFG:
         .DB     0                       ; ACIA TYPE (SET DURING INIT)
         .DB     0                       ; MODULE ID
         .DB     ACIA0BASE               ; BASE PORT
-        .DW     DEFSERCFG               ; LINE CONFIGURATION
+        .DW     ACIA0CFG                ; LINE CONFIGURATION
         .DW     ACIA0_RCVBUF            ; POINTER TO RCV BUFFER STRUCT
 	.DW     ACIA0_INT		; INT HANDLER POINTER
 	.DW	(ACIA0CLK / ACIA0DIV) & $FFFF	; CLOCK FREQ AS
@@ -707,7 +707,7 @@ ACIA1_CFG:
         .DB     0                       ; ACIA TYPE (SET DURING INIT)
         .DB     1                       ; MODULE ID
         .DB     ACIA1BASE               ; BASE PORT
-        .DW     DEFSERCFG               ; LINE CONFIGURATION
+        .DW     ACIA1CFG                ; LINE CONFIGURATION
         .DW     ACIA1_RCVBUF            ; POINTER TO RCV BUFFER STRUCT
 	.DW     ACIA1_INT		; INT HANDLER POINTER
 	.DW	(ACIA1CLK / ACIA1DIV) & $FFFF	; CLOCK FREQ AS
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 6e94bdb1..121f3aaf 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -77,7 +77,7 @@ SIO0MODE	.EQU	SIOMODE_EZZ80	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	1843200		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	DEFSERCFG	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	1843200		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
@@ -85,7 +85,7 @@ SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	DEFSERCFG	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
@@ -125,6 +125,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index a1254959..947bd5e0 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -116,7 +116,7 @@ SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	DEFSERCFG	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
@@ -124,7 +124,7 @@ SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	DEFSERCFG	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
@@ -167,6 +167,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 9c7eade5..a49b0191 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -125,6 +125,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 12b9fb6e..b813abb9 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -128,6 +128,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 0b93fe0f..0754bb12 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -83,7 +83,7 @@ SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	SER_115200_8N1	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	SER_115200_8N1	; SER_115200_8N1 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
@@ -91,7 +91,7 @@ SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	SER_115200_8N1	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	SER_115200_8N1	; SER_115200_8N1 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
@@ -131,6 +131,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 2839083a..669e4ca6 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -86,7 +86,7 @@ SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	DEFSERCFG	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
@@ -94,7 +94,7 @@ SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	DEFSERCFG	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
@@ -134,6 +134,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index a4d0d56d..c275e36d 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -82,7 +82,7 @@ SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	4915200		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	8		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	DEFSERCFG	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	4915200		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	8		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
@@ -125,6 +125,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 4c1fa3b1..2442318b 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -78,7 +78,7 @@ SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ADIV	.EQU	1		; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO0ACFG	.EQU	SER_115200_8N1	; AIO 0A: SERIAL LINE CONFIG
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BDIV	.EQU	1		; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
@@ -86,7 +86,7 @@ SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ADIV	.EQU	1		; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
-SIO1ACFG	.EQU	SER_115200_8N1	; AIO 1A: SERIAL LINE CONFIG
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
 SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1BDIV	.EQU	1		; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
 SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
@@ -126,6 +126,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 330071d5..00ecda6e 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -104,6 +104,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 07a506a7..ea319e0e 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -108,6 +108,7 @@ PPIDE8BIT	.EQU	FALSE		; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 ;
diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm
index 0faf1d54..e96977cb 100644
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -173,7 +173,7 @@ SD_DO		.EQU	%00100000	; UART MSR:5 IS DATA OUT (CARD -> CPU)
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_DSD)		; DUAL SD
-SD_DEVCNT	.EQU	2		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_DEVCNT	.EQU	SDCNT		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	$08		; DEDICATED OPERATIONS REGISTER
 SD_OPRDEF	.EQU	%00000001	; QUIESCENT STATE
 SD_INPREG	.EQU	SD_OPRREG	; INPUT REGISTER IS OPRREG
@@ -195,10 +195,11 @@ SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
 ;
 #IF (SDMODE == SDMODE_SC)		; SC
-SD_DEVCNT	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_DEVCNT	.EQU	SDCNT		; NUMBER OF PHYSICAL UNITS (SOCKETS)
 SD_OPRREG	.EQU	RTCIO		; USES RTC LATCHES FOR OPERATION
 SD_OPRDEF	.EQU	%00001100	; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
-SD_CS		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
+SD_CS0		.EQU	%00000100	; RTC:2 IS SELECT FOR PRIMARY SPI CARD
+SD_CS1		.EQU	%00001000	; RTC:3 IS SELECT FOR SECONDARY SPI CARD
 SD_CNTR		.EQU	Z180_CNTR
 SD_TRDR		.EQU	Z180_TRDR
 #ENDIF
@@ -1464,7 +1465,23 @@ SD_CHKWP:
 SD_SELECT:
 	LD	A,(SD_OPRVAL)
 #IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+  #IF (SDMODE == SDMODE_SC)
+	LD	A,(IY+SD_DEV)		; GET CURRENT DEVICE
+	OR	A			; SET FLAGS
+	LD	A,(SD_OPRVAL)		; GET CURRENT OPRVAL BACK
+	JR	NZ,SD_SELECT1		; IF NOT ZERO, DO SECONDARY
+	; ASSERT PRIMARY CS, DEASSERT SECONDARY
+	AND	~SD_CS0
+	OR	SD_CS1
+	JR	SD_SELECT2
+SD_SELECT1:
+	; DEASSERT PRIMARY CS, ASSERT SECONDARY
+	OR	SD_CS0
+	AND	~SD_CS1
+SD_SELECT2:
+  #ELSE
 	AND	~SD_CS			; SET SD_CS (CHIP SELECT)
+  #ENDIF
 #ELSE
 	OR	SD_CS			; SET SD_CS (CHIP SELECT)
 #ENDIF
@@ -1477,7 +1494,12 @@ SD_SELECT:
 SD_DESELECT:
 	LD	A,(SD_OPRVAL)
 #IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+  #IF (SDMODE == SDMODE_SC)
+	OR	SD_CS0			; RESET PRIMARY CHIP SELECT
+	OR	SD_CS1			; RESET SECONDARY CHIP SELECT
+  #ELSE
 	OR	SD_CS			; RESET SD_CS (CHIP SELECT)
+  #ENDIF
 #ELSE
 	AND	~SD_CS			; RESET SD_CS (CHIP SELECT)
 #ENDIF
diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc
index 30e053b4..fd9cafab 100644
--- a/Source/HBIOS/ver.inc
+++ b/Source/HBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.13"
+#DEFINE BIOSVER	"2.9.2-pre.16"
diff --git a/Source/Images/fd0/u0/FAT.COM b/Source/Images/fd0/u0/FAT.COM
index 4bd4cc70..2fcfc9e7 100644
Binary files a/Source/Images/fd0/u0/FAT.COM and b/Source/Images/fd0/u0/FAT.COM differ
diff --git a/Source/Images/fd1/u0/FAT.COM b/Source/Images/fd1/u0/FAT.COM
index 4bd4cc70..2fcfc9e7 100644
Binary files a/Source/Images/fd1/u0/FAT.COM and b/Source/Images/fd1/u0/FAT.COM differ
diff --git a/Source/Images/hd0/s0/u0/FAT.COM b/Source/Images/hd0/s0/u0/FAT.COM
index 4bd4cc70..2fcfc9e7 100644
Binary files a/Source/Images/hd0/s0/u0/FAT.COM and b/Source/Images/hd0/s0/u0/FAT.COM differ
diff --git a/Source/RomDsk/ROM_1024KB/FAT.COM b/Source/RomDsk/ROM_1024KB/FAT.COM
index 4bd4cc70..4568817c 100644
Binary files a/Source/RomDsk/ROM_1024KB/FAT.COM and b/Source/RomDsk/ROM_1024KB/FAT.COM differ