diff --git a/Source/Apps/XM/xmx.180 b/Source/Apps/XM/xmx.180
index ecca2f71..6e05ca4c 100644
--- a/Source/Apps/XM/xmx.180
+++ b/Source/Apps/XM/xmx.180
@@ -582,10 +582,11 @@ UB_RCVRDY:
 	PUSH	DE
 	PUSH	HL
 	LD	BC,0013H	; unit 0, func 13h (input stat)
-	LD	A,E		; # chars waiting to A
-	SUB	1		; CF set IFF zero
-	RL	A		; CF to bit 0 of A
-	AND	01H		; set Z flag as needed
+	RST	08
+	XOR	A		; zero accum		; 4
+	CP	E		; CF means not zero	; 4
+	CCF			; CF means zero		; 4
+	RLA			; ZF means not zero	; 4
 	LD	A,0		; report no line errors
 	POP	HL
 	POP	DE
@@ -601,10 +602,11 @@ UB_SNDRDY:
 	PUSH	DE
 	PUSH	HL
 	LD	BC,0014H	; unit 0, func 14h (output stat)
-	LD	A,E		; # chars space in output buf
-	SUB	1		; CF set IFF zero
-	RL	A		; CF to bit 0 of A
-	AND	01H		; set Z flag as needed
+	RST	08
+	XOR	A		; zero accum		; 4
+	CP	E		; CF means not zero	; 4
+	CCF			; CF means zero		; 4
+	RLA			; ZF means not zero	; 4
 	POP	HL
 	POP	DE
 	POP	BC
@@ -655,15 +657,15 @@ UA_JPTBL:
 ; UART initialization
 ;
 UA_INIT:
-	LD	DE,13000	; Receive loop timeout scalar
+	LD	DE,13000	; receive loop timeout scalar
 	LD	(RCVSCL),DE	; ... for UART RCVRDY timing
 ;
-	LD	A,L		; Get base I/O port address
-	LD	(UA_SCP),A	; Set port value in SENDR
-	LD	(UA_GCP),A	; Set port value in GETCHR
+	LD	A,L		; get base I/O port address
+	LD	(UA_SCP),A	; set port value in SENDR
+	LD	(UA_GCP),A	; set port value in GETCHR
 	ADD	A,5		; UART control port is 5 higher
-	LD	(UA_RRP),A	; Set port value in RCVRDY
-	LD	(UA_SRP),A	; Set port value in SNDRDY
+	LD	(UA_RRP),A	; set port value in RCVRDY
+	LD	(UA_SRP),A	; set port value in SNDRDY
 ;
 	LD	HL,UA_JPTBL
 	LD	DE,UA_LBL
@@ -713,7 +715,7 @@ UA_GCP	EQU	$-1		; port value
 ;
 UA_RCVRDY:
 	IN	A,(0FFH)	; get modem status
-UA_RRP	EQU	$-1		; port value	
+UA_RRP	EQU	$-1		; port value
 	AND	UA_RCVB		; isolate ready bit
 	CP	UA_RCVR		; test it (set flags)
 	LD	A,0		; report no line errors
@@ -776,17 +778,17 @@ UF_JPTBL:
 ; USB-FIFO initialization
 ;
 UF_INIT:
-	LD	DE,12000	; Receive loop timeout scalar
+	LD	DE,12000	; receive loop timeout scalar
 	LD	(RCVSCL),DE	; ... for UART RCVRDY timing
 ;
-	LD	A,L		; Get base I/O port address (data port)
-	LD	(UF_SCDP),A	; Set data port in SENDR
-	LD	(UF_GCDP),A	; Set data port in GETCHR/MDIN
-	INC	A		; Bump to status port
-	LD	(UF_RRSP),A	; Set status port in RCVRDY
-	LD	(UF_SRSP),A	; Set status port in SNDRDY
-	INC	A		; Bump to send immediate port
-	LD	(UF_SCIP),A	; Set send immed port in SENDR
+	LD	A,L		; get base I/O port address (data port)
+	LD	(UF_SCDP),A	; set data port in SENDR
+	LD	(UF_GCDP),A	; set data port in GETCHR/MDIN
+	INC	A		; bump to status port
+	LD	(UF_RRSP),A	; set status port in RCVRDY
+	LD	(UF_SRSP),A	; set status port in SNDRDY
+	INC	A		; bump to send immediate port
+	LD	(UF_SCIP),A	; set send immed port in SENDR
 ;
 	LD	HL,UF_JPTBL
 	LD	DE,UF_LBL
@@ -820,8 +822,8 @@ UF_CAROK:
 ; GETCHR must not block
 ;
 UF_GETCHR:
-	CALL	UF_RCVRDY
-	RET	NZ
+	CALL	UF_RCVRDY	; check for char ready
+	RET	NZ		; return if not
 	; Fall thru if char ready
 ;
 ; MDIN can assume a character is ready
@@ -838,11 +840,11 @@ UF_GCDP	EQU	$-1		; data port
 ; *** Error code does not seem to be used ***
 ;
 UF_RCVRDY:
-	IN	A,(0FFH)	; b7=0 if char avail, =1 if no char.
+	IN	A,(0FFH)	; bit 7 = 0 if char avail, = 1 if no char.
 UF_RRSP	EQU	$-1		; status port
-	RLCA			; b0=0 if char avail, =1 if no char.
-	AND	00000001B	; a=0, zf=1 if no char, a=1, zf=0 if char avail.
-	LD	A,0
+	RLCA			; bit 0 = 0 if char avail, = 1 if no char.
+	AND	00000001B	; A = 0, ZF = 1 if no char, A = 1, ZF = 0 if char avail.
+	LD	A,0		; no errors
 	RET
 ;
 ;-----------------------------------------------------------------------
@@ -850,9 +852,9 @@ UF_RRSP	EQU	$-1		; status port
 ; Test for ready to send a character, Z = ready
 ;
 UF_SNDRDY:
-	IN	A,(0FFH)	; bit 0=0 if space avail, =1 IF FULL
+	IN	A,(0FFH)	; bit 0 = 0 if space avail, = 1 if full
 UF_SRSP	EQU	$-1		; status port
-	AND	00000001B	; A=0, ZF=1 if space avail, A=1, ZF=0 if full.
+	AND	00000001B	; A = 0, ZF = 1 if space avail, A = 1, ZF = 0 if full.
 	RET
 ;
 ;-----------------------------------------------------------------------
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 7c001f72..fe01a1c7 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -46,6 +46,7 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 4e0e3b6a..aebb4956 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -64,6 +64,7 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index e3cc8fe4..0e8d5ca3 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -45,6 +45,7 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 2bb6d10a..4c4242f7 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -43,6 +43,7 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index eecac1ec..fd95b4d2 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -46,6 +46,7 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$20		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
 CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
 CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
diff --git a/Source/HBIOS/ctc.asm b/Source/HBIOS/ctc.asm
index a9d80441..192ffb78 100644
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@@ -5,6 +5,20 @@
 ;   DISPLAY CONFIGURATION DETAILS
 ;______________________________________________________________________________________________________________________
 ;
+CTC_DEFCFG	.EQU	%01010011	; CTC DEFAULT CONFIG
+CTC_CTRCFG	.EQU	%01010111	; CTC COUNTER MODE CONFIG
+CTC_TIM16CFG	.EQU	%00010111	; CTC TIMER/16 MODE CONFIG
+CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
+CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
+		;	 |||||||+-- CONTROL WORD FLAG
+		;	 ||||||+--- SOFTWARE RESET
+		;	 |||||+---- TIME CONSTANT FOLLOWS
+		;	 ||||+----- AUTO TRIGGER WHEN TIME CONST LOADED
+		;	 |||+------ RISING EDGE TRIGGER
+		;	 ||+------- TIMER MODE PRESCALER (0=16, 1=256)
+		;	 |+-------- COUNTER MODE
+		;	 +--------- INTERRUPT ENABLE
+;
 #IF (CTCTIMER)
 ;
 ; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
@@ -21,53 +35,39 @@ CTC_PREIO	.EQU	CTCBASE + CTCPRECH
 CTC_SCLIO	.EQU	CTCBASE + CTCTIMCH
 ;
   #IF (CTCMODE == CTCMODE_CTR)
-CTC_DIV		.EQU	CTCOSC / TICKFREQ
+CTC_PRECFG	.EQU	CTC_CTRCFG
+CTC_PRESCL	.EQU	1
   #ENDIF
   #IF (CTCMODE == CTCMODE_TIM16)
-CTC_DIV		.EQU	CTCOSC / 16 / TICKFREQ
+CTC_PRECFG	.EQU	CTC_TIM16CFG
+CTC_PRESCL	.EQU	16
   #ENDIF
   #IF (CTCMODE == CTCMODE_TIM256)
-CTC_DIV		.EQU	CTCOSC / 256 / TICKFREQ
+CTC_PRECFG	.EQU	CTC_TIM256CFG
+CTC_PRESCL	.EQU	256
   #ENDIF
+;
+CTC_DIV		.EQU	CTCOSC / CTC_PRESCL / TICKFREQ
 ;
 	.ECHO "CTC DIVISOR: "
 	.ECHO CTC_DIV
 	.ECHO "\n"
 ;
-#IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
+  #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF))
 	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
 	!!!
-#ENDIF
-;
-CTC_DIVHI	.EQU	((CTC_DIV >> 8) & $FF)
-CTC_DIVLO	.EQU	(CTC_DIV & $FF)
-;
-CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
+  #ENDIF
 ;
-CTC_DEFCFG	.EQU	%01010011	; CTC DEFAULT CONFIG
-CTC_CTRCFG	.EQU	%01010111	; CTC COUNTER MODE CONFIG
-CTC_TIM16CFG	.EQU	%00010111	; CTC TIMER/16 MODE CONFIG
-CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
-CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
-		;	 |||||||+-- CONTROL WORD FLAG
-		;	 ||||||+--- SOFTWARE RESET
-		;	 |||||+---- TIME CONSTANT FOLLOWS
-		;	 ||||+----- AUTO TRIGGER WHEN TIME CONST LOADED
-		;	 |||+------ RISING EDGE TRIGGER
-		;	 ||+------- TIMER MODE PRESCALER (0=16, 1=256)
-		;	 |+-------- COUNTER MODE
-		;	 +--------- INTERRUPT ENABLE
+CTC_DIVHI	.EQU	CTCPRE
+CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
 ;
-  #IF (CTCMODE == CTCMODE_CTR)
-CTC_PRECFG	.EQU	CTC_CTRCFG
-  #ENDIF
-  #IF (CTCMODE == CTCMODE_TIM16)
-CTC_PRECFG	.EQU	CTC_TIM16CFG
-  #ENDIF
-  #IF (CTCMODE == CTCMODE_TIM256)
-CTC_PRECFG	.EQU	CTC_TIM256CFG
+  #IF ((CTC_DIVHI * CTC_DIVLO * CTC_PRESCL * TICKFREQ) != CTCOSC)
+	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
+	!!!
   #ENDIF
 ;
+CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
+;
 #ENDIF
 ;
 ;
@@ -102,7 +102,7 @@ CTC_PREINIT1:
 	; TO THE TIMER CHANNEL TRIGGER INPUT VIA HARDWARE.
 	LD	A,CTC_PRECFG		; PRESCALE CHANNEL CONFIGURATION
 	OUT	(CTC_PREIO),A		; SETUP PRESCALE CHANNEL
-	LD	A,CTC_DIVHI		; PRESCALE CHANNEL CONSTANT
+	LD	A,CTC_DIVHI & $FF	; PRESCALE CHANNEL CONSTANT
 	OUT	(CTC_PREIO),A		; SET PRESCALE CONSTANT
 ;
 	LD	A,CTC_TIMCFG		; TIMER CHANNEL CONTROL WORD VALUE
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 9debbc45..a7c41062 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -624,7 +624,7 @@ SIO_INITDEV1D:
 	RR	C			; ... TO DIVIDE BY 2
 	JR	NC,SIO_ADJDONE		; DONE IF NO CARRY
 ;
-	; IF CARRY, RESULTANT CIVISOR IS UNWORKABLE
+	; IF CARRY, RESULTANT DIVISOR IS UNWORKABLE
 	POP	DE			; POP STACK
 	JR	SIO_INITFAIL		; AND FAIL