From eeab78684899ff61cbc141cc1381c8beeba4023a Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 1 May 2020 17:30:12 -0700 Subject: [PATCH] Update sd.asm Optimize SD Card protocol timing delay for CSIO interface. --- Source/HBIOS/sd.asm | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index ef187081..1fefcfa7 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -866,7 +866,7 @@ SD_INITCARD1: ; MAKE SURE WE FINISH SENDING #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) CALL SD_WAITTX ; WAIT FOR TE TO CLEAR - CALL DLY4 ; WAIT A BIT MORE FOR FINAL BIT + CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT #ENDIF ; ; PUT CARD IN IDLE STATE @@ -1025,7 +1025,7 @@ SD_INITCARD5: ; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION ; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING - CALL DLY4 ; WAIT A BIT MORE FOR FINAL BIT + CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT XOR A ; ZERO MEANS MAX SPEED OUT (Z180_CNTR),A ; NOW SET CSIO PORT #ENDIF @@ -1674,12 +1674,10 @@ SD_DESELECT: ; FINISH SENDING AFTER TE IS CLEARED. THE DELAY BELOW WILL ; DO THIS FOR THE SLOWEST POSSIBLE SEND RATE WHICH IS ; CLK / 1320, SO DELAY AT LEAST 1320 T-STATES - ;CALL DLY64 ; DELAY FOR FINAL BIT ; - ; IN PRACTICE, IT LOOKS LIKE THIS WORST CASE SCENARIO NEVER - ; OCCURS. FOR NOW, USE A SMALL DELAY WHICH SEEMS TO BE MORE - ; THAN ADEQUATE BASED ON LOGIC ANALYZER TRACES. - CALL DLY4 ; DELAY FOR FINAL BIT + ; IN PRACTICE, A SMALLER DELAY IS FINE BASED ON LOGIC ANALYZER + ; TRACES. + CALL DLY32 ; DELAY FOR FINAL BIT #ENDIF ; LD A,(SD_OPRVAL)