Initial ecb-dma support

Source/HBIOS/cfg_dyno.asm

@@ -188,3 +188,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_ezz80.asm

@@ -223,3 +223,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_master.asm

@@ -291,3 +291,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_mk4.asm

@@ -223,3 +223,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_n8.asm

@@ -223,3 +223,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_rcz180.asm

@@ -236,3 +236,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_rcz280.asm

@@ -252,3 +252,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_rcz80.asm

@@ -241,3 +241,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_sbc.asm

@@ -224,3 +224,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_scz180.asm

@@ -231,3 +231,7 @@ AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_zeta.asm

@@ -159,3 +159,7 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/cfg_zeta2.asm

@@ -170,3 +170,8 @@ UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
 AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_WKD	; DMA: DMA MODE (NONE|WKD|Z180|Z280|RC)

Source/HBIOS/dma.asm

@@ -0,0 +1,198 @@
+;==================================================================================================
+; Z80 DMA DRIVER FOR ECB-DMA
+;==================================================================================================
+;
+; DUE TO LOW CLOCK SPEED CONTRAINTS OF Z80 DMA CHIP, THE HALF CLOCK FACILITY 
+; IS USED DURING DMA PROGRAMMING AND CONTINUOUS BLOCK TRANSFERS.
+; TESTING CONDUCTED ON A SBC-V2-005 @ 10Mhz
+;
+DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
+DMA_BYTE			.equ 	%10011101	; + Pulse
+DMA_BURST 			.equ	%11011101	; + Pulse
+DMA_LOAD			.equ	$cf 		; %11001111
+DMA_ENABLE			.equ	$87		; %10000111
+DMA_FORCE_READY 		.equ 	$b3
+DMA_DISABLE			.equ	$83
+;
+;DMA_RESET			.equ	$c3
+;DMA_RESET_PORT_A_TIMING	.equ	$c7
+;DMA_RESET_PORT_B_TIMING	.equ	$cb
+;DMA_CONTINUE			.equ	$d3
+;DMA_DISABLE_INTERUPTS		.equ	$af
+;DMA_ENABLE_INTERUPTS		.equ	$ab
+;DMA_RESET_DISABLE_INTERUPTS	.equ 	$a3
+;DMA_ENABLE_AFTER_RETI		.equ	$b7
+;DMA_READ_STATUS_BYTE		.equ	$bf
+;DMA_REINIT_STATUS_BYTE		.equ	$8b
+;DMA_START_READ_SEQUENCE	.equ	$a7
+;DMA_WRITE_REGISTER_COMMAND	.equ	$bb
+;
+;==================================================================================================
+; DMA INITIALIZATION CODE
+;==================================================================================================
+;
+DMA_INIT:
+	CALL	NEWLINE
+	PRTS("DMA: IO=0x$")
+	LD	A, DMABASE
+	CALL	PRTHEXBYTE
+;
+	ld	a,0
+	out	(DMABASE+1),a		; force ready off
+;
+	ld	hl,DMACode		; program the
+	ld	b,DMACode_Len		; dma command
+	ld	c,DMABASE		; block
+;
+	ld	a,(RTCVAL)
+	or	%00001000		; half
+	out	(112),a			; clock
+	di
+	otir				; load dma
+	ei
+	and	%11110111		; full
+	out	(112),a			; clock
+	ret
+;
+DMACode		;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+		.dw	0 		; R0-Port A, Start address
+		.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+		.dw	0 		; R4-Port B, Destination address
+		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
+		.db	%10011010 	; R5-Stop on end of block, ce/wait multiplexed, READY active HIGH
+		.db	DMA_LOAD 	; R6-Command Load
+;		.db	DMA_FORCE_READY	; R6-Command Force ready
+;		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACode_Len 	.equ	$-DMACode
+;
+;==================================================================================================
+; DMA COPY BLOCK CODE -  ASSUMES DMA PREINITIALIZED
+;==================================================================================================
+;
+DMALDIR:
+	ld	(DMASource),hl		; populate the dma
+	ld	(DMADest),de		; register template
+	ld	(DMALength),bc
+;
+	ld	hl,DMACopy		; program the
+	ld	b,DMACopy_Len		; dma command
+	ld	c,DMABASE		; block
+;
+	ld	a,(RTCVAL)
+	or	%00001000		; half
+	out	(112),a			; clock
+	di
+	otir				; load and execute dma
+	ei
+	and	%11110111		; full
+	out	(112),a			; clock
+	ret
+;
+DMACopy 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+DMASource	.dw	0 		; R0-Port A, Start address
+DMALength	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMADest		.dw	0 		; R4-Port B, Destination address
+		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
+;		.db	%10011010 	; R5-Stop on end of block, ce/wait multiplexed, READY active HIGH
+		.db	DMA_LOAD 	; R6-Command Load
+		.db	DMA_FORCE_READY	; R6-Command Force ready
+		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACopy_Len 	.equ	$-DMACopy
+;
+;==================================================================================================
+; DMA I/O OUT BLOCK CODE - ADDRESS TO I/O PORT
+;==================================================================================================
+;
+DMAOTIR:
+	ld	(DMAOutSource),hl	; populate the dma
+	ld	(DMAOutDest),a		; register template
+	ld	(DMAOutLength),bc	
+;
+	ld	hl,DMAOutCode		; program the
+	ld	b,DMAOut_Len		; dma command
+	ld	c,DMABASE		; block
+;
+	ld	a,(RTCVAL)
+	or	%00001000		; half
+	out	(112),a			; clock
+	di
+	otir				; load and execute dma
+	ei
+	and	%11110111		; full
+	out	(112),a			; clock
+	ret
+;
+DMAOutCode  	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111001 	; R0-Transfer mode, B -> A (temp), start address, block length follow	
+DMAOutSource	.dw	0 		; R0-Port A, Start address
+DMAOutLength	.dw	0 		; R0-Block length
+
+		.db	%00010100	; R1-No timing bytes follow, fixed incrementing address, is memory	
+		.db	%00101000 	; R2-No timing bytes follow, address static, is i/o			
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+
+		.db	%10100101	; R4-Continuous mode, destination port, interrupt and control byte follow
+DMAOutDest	.db	0 		; R4-Port B, Destination port
+;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+;		.db	0		; R4-Pulse offset
+
+		.db	%10011010 	; R5-Stop on end of block, ce/wait multiplexed, READY active HIGH	
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	%00000101	; R0-Port A is Source							
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	DMA_FORCE_READY	; R6-Command Force ready						
+		.db	DMA_ENABLE 	; R6-Command Enable DMA							
+DMAOut_Len 	.equ	$-DMAOutCode
+;
+;==================================================================================================
+; DMA I/O INPUT BLOCK CODE - I/O PORT TO ADDRESS
+;==================================================================================================
+;
+DMAINIR:
+	ld	(DMAInDest),hl		; populate the dma
+	ld	(DMAInSource),a		; register template
+	ld	(DMAInLength),bc	
+;
+	ld	hl,DMAInCode		; program the
+	ld	b,DMAIn_Len		; dma command
+	ld	c,DMABASE		; block
+;
+	ld	a,(RTCVAL)
+	or	%00001000		; half
+	out	(112),a			; clock
+	di
+	otir				; load and execute dma
+	ei
+	and	%11110111		; full
+	out	(112),a			; clock
+	ret
+;
+DMAInCode 	;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111001 	; R0-Transfer mode, B -> A, start address, block length follow		
+DMAInDest	.dw	0 		; R0-Port A, Start address
+DMAInLength	.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory		
+		.db	%00111000 	; R2-No timing bytes follow, address static, is i/o			
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+		.db	%10100101	; R4-Continuous mode, destination port, no interrupt, control byte.	
+DMAInSource	.db	0 		; R4-Port B, Destination port
+;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+;		.db	0		; R4-Pulse offset
+		.db	%10011010 	; R5-Stop on end of block, ce/wait multiplexed, READY active HIGH	
+		.db	DMA_LOAD 	; R6-Command Load							
+		.db	DMA_FORCE_READY	; R6-Command Force ready						
+		.db	DMA_ENABLE 	; R6-Command Enable DMA							
+
+DMAIn_Len 	.equ	$-DMAInCode

Source/HBIOS/hbios.asm

@@ -2339,6 +2339,9 @@ HB_INITTBL:
 #IF (DSKYENABLE)
 	.DW	DSKY_INIT
 #ENDIF
+#IF (DMAENABLE)
+	.DW	DMA_INIT
+#ENDIF
 #IF (MDENABLE)
 	.DW	MD_INIT
 #ENDIF
@@ -4645,6 +4648,14 @@ SIZ_NEC	.EQU	$ - ORG_NEC
 		.ECHO	SIZ_NEC
 		.ECHO	" bytes.\n"
 #ENDIF
+#IF (DMAENABLE)
+ORG_DMA	.EQU	$
+#INCLUDE "dma.asm"
+SIZ_DMA	.EQU	$ - ORG_DMA
+		.ECHO	"DMA occupies "
+		.ECHO	SIZ_DMA
+		.ECHO	" bytes.\n"
+#ENDIF
 ;
 ; FONTS AREA
 ;

Source/HBIOS/md.asm

@@ -350,9 +350,14 @@ MD_SECM:
 	LD	HL,MD_F4KBUF		; POINT TO THE SECTOR WE 
 	ADD	HL,DE			; WANT TO COPY
 	LD	DE,(MD_DSKBUF)
+;
+#IF (DMAENABLE)
+	LD	BC,512-1		; COPY ONE 512B SECTOR FROM THE
+	CALL	DMALDIR			; 4K SECTOR TO THE DISK BUFFER
+#ELSE	
 	LD	BC,512			; COPY ONE 512B SECTOR FROM THE
 	LDIR				; 4K SECTOR TO THE DISK BUFFER
-;
+#ENDIF
 	XOR	A
 	RET
 ;
@@ -466,8 +471,13 @@ MD_SECM1:				; DESIRED SECTOR IS IN BUFFER
 	EX	DE,HL
 ;
 	LD	HL,(MD_DSKBUF)
+#IF (DMAENABLE)
+	LD	BC,512-1		; COPY ONE 512B SECTOR FROM THE
+	CALL	DMALDIR			; THE DISK BUFFER TO 4K SECTOR
+#ELSE
 	LD	BC,512			; COPY ONE 512B SECTOR FROM THE
 	LDIR				; THE DISK BUFFER TO 4K SECTOR
+#ENDIF
 ;
 	LD	IX,MD_F4KBUF		; SET SOURCE ADDRESS
 	LD	HL,MD_FWRIT_R		; PUT ROUTINE TO CALL
@@ -745,7 +755,7 @@ MD_PROBE:
 	JR	Z,MD_PR2		; R/W FLAG TO R/O
 	LD	HL,MD_FFSEN		; A NON ZERO VALUE
 	SET	0,(HL)			; MEANS WE CAN'T
-					; ENABLE FLASH WRITING;
+					; ENABLE FLASH WRITING
 MD_PR2:
 	POP	HL
 #IF (MD_FVBS==1)

Source/HBIOS/rf.asm

@@ -12,7 +12,7 @@ RF_U3IO		.EQU	$AC		; BASED ADDRESS OF RAMFLOPPY 4
 ;
 ; IO PORT OFFSETS
 ;
-RF_DAT		.EQU	0		; DATA IN/OUT ONLT TO SRAM      - R/W
+RF_DAT		.EQU	0		; DATA IN/OUT ONLY TO SRAM      - R/W
 RF_AL		.EQU	1		; ADDRESS LOW FOR RAMF MEMORY   - W/O 
 RF_AH		.EQU	2		; ADDRESS HIGH FOR RAMF MEMORY  - W/O
 RF_ST		.EQU	3		; STATUS PORT			- R/O
@@ -271,12 +271,18 @@ RF_RW3:
 RF_RDSEC:
 	CALL	RF_SETADR		; SEND SECTOR STARTING ADDRESS TO CARD
 	LD	HL,(RF_DSKBUF)		; HL := DISK BUFFER ADDRESS
-	LD	B,0			; INIT BYTE COUNTER
 	LD	A,(RF_IO)		; GET IO PORT BASE
+#IF (DMAENABLE)
+	LD	BC,512-1		; READ 512 BYTES
+	CALL	DMAINIR			; USING DMA
+#ELSE
 	OR	RF_DAT			; OFFSET TO DAT PORT
 	LD	C,A			; PUT IN C FOR PORT IO
+	LD	B,0			; INIT BYTE COUNTER
 	INIR				; READ 256 BYTES
 	INIR				; AND ANOTHER 256 BYTES FOR 512 TOTAL
+#ENDIF
+
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND DONE
 ;
@@ -285,12 +291,17 @@ RF_RDSEC:
 RF_WRSEC:
 	CALL	RF_SETADR		; SEND SECTOR STARTING ADDRESS TO CARD
 	LD	HL,(RF_DSKBUF)		; HL := DISK BUFFER ADDRESS
-	LD	B,0			; INIT BYTE COUNTER
 	LD	A,(RF_IO)		; GET IO PORT BASE
 	OR	RF_DAT			; OFFSET TO DAT PORT
+#IF (DMAENABLE==1)
+	LD	BC,512-1		; WRITE 512 BYTES
+	CALL	DMAOTIR			; USING DMA
+#ELSE
 	LD	C,A			; PUT IN C FOR PORT IO
+	LD	B,0			; INIT BYTE COUNTER
 	OTIR				; WRITE 256 BYTES
 	OTIR				; AND ANOTHER 256 BYTES FOR 512 TOTAL
+#ENDIF
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND DONE
 ;

Source/HBIOS/std.asm

@@ -203,6 +203,14 @@ TMSMODE_N8	.EQU	2		; N8 BUILT-IN VIDEO
 TMSMODE_RC	.EQU	3		; RC2014 TMS9918 VIDEO BOARD
 TMSMODE_RCV9958	.EQU	4		; RC2014 V9958 VIDEO BOARD
 ;
+; DMA MODE SELECTIONS
+;
+DMAMODE_NONE	.EQU	0
+DMAMODE_WKD	.EQU	1		; ECB-DMA WOLFGANG KABATZKE'S Z80 DMA ECB BOARD
+DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
+DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
+DMAMODE_RC	.EQU	4		; RC2014 Z80 DMA
+;
 ; SERIAL DEVICE CONFIGURATION CONSTANTS
 ;
 SER_DATA5	.EQU	0 << 0