diff --git a/Source/Apps/XM/XModem Xfer Anomaly b/Source/Apps/XM/XModem Xfer Anomaly.txt
similarity index 100%
rename from Source/Apps/XM/XModem Xfer Anomaly
rename to Source/Apps/XM/XModem Xfer Anomaly.txt
diff --git a/Source/Apps/XM/xmdm125.asm b/Source/Apps/XM/xmdm125.asm
index 23c35c41..e735b618 100644
--- a/Source/Apps/XM/xmdm125.asm
+++ b/Source/Apps/XM/xmdm125.asm
@@ -3497,6 +3497,12 @@ RECVDG:	CALL	GETCHR
 	CALL	GETCHR
 ;
 RECV:	PUSH	D		; Save 'DE' regs.
+;
+; [WBW] BEGIN: Check immediately for char pending to avoid delay
+	CALL	RCVRDY		; Input from modem ready
+	JZ	MCHAR		; Got the character
+; [WBW] END
+;
 ; [WBW] BEGIN: Use dynamic CPU speed
 ;	MVI	E,MHZ		; Get the clock speed
 	LDA	CPUMHZ		; Get the clock speed
diff --git a/Source/Apps/XM/xmx.180 b/Source/Apps/XM/xmx.180
index e583458b..ecca2f71 100644
--- a/Source/Apps/XM/xmx.180
+++ b/Source/Apps/XM/xmx.180
@@ -281,7 +281,7 @@ RCVSCL	DW	6600		; RECV loop timeout scalar
 UNIT	DB	0		; BIOS serial device unit number
 BIOSBID	DB	00H		; BIOS bank id
 ;
-TAG	DB	"RomWBW, 23-May-2020$"
+TAG	DB	"RomWBW, 30-May-2020$"
 ;
 HB_LBL	DB	", HBIOS FastPath$"
 UB_LBL	DB	", UNA UBIOS$"
@@ -776,8 +776,8 @@ UF_JPTBL:
 ; USB-FIFO initialization
 ;
 UF_INIT:
-	LD	HL,12000	; Receive loop timeout scalar
-	LD	(RCVSCL),HL	; ... for UART RCVRDY timing
+	LD	DE,12000	; Receive loop timeout scalar
+	LD	(RCVSCL),DE	; ... for UART RCVRDY timing
 ;
 	LD	A,L		; Get base I/O port address (data port)
 	LD	(UF_SCDP),A	; Set data port in SENDR