diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index ba080d08..2dcd48d9 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -1,5 +1,3 @@ - -- DDW: Added support for the 'N8PC' platform. Includes support for the M6242 RTC chip. Version 3.6 ----------- - RDG: Added VDA driver for Xosera FPGA-based VDC @@ -36,6 +34,7 @@ Version 3.6 - HJB: Added IDE driver master media detect option - WBW: Add support for S100 Serial I/O DLP Serial connection - P?D: Generate compressed ROM for EaZyZ80 512 +- DDW: Added support for the 'N8PC' platform. Includes support for the M6242 RTC chip. Version 3.5.1 ------------- diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index f5c256cc..a09df7b8 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index 0acd571b..3395e454 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf index 9957bb19..aa7b1903 100644 Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ diff --git a/Doc/RomWBW Introduction.pdf b/Doc/RomWBW Introduction.pdf index fccd89c0..94cebe26 100644 Binary files a/Doc/RomWBW Introduction.pdf and b/Doc/RomWBW Introduction.pdf differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 142f1441..ead41adb 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index 2fcab94d..0db99167 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/ReadMe.md b/ReadMe.md index fdaab2f1..0d606e30 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -7,7 +7,7 @@ **RomWBW Introduction** \ Version 3.6 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -25 Nov 2025 +29 Nov 2025 # Overview diff --git a/ReadMe.txt b/ReadMe.txt index 1378794f..4350d358 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW Introduction Wayne Warthen (wwarthen@gmail.com) -25 Nov 2025 +29 Nov 2025 diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md index 7a01a0e6..93458ad8 100644 --- a/Source/Doc/Hardware.md +++ b/Source/Doc/Hardware.md @@ -69,6 +69,7 @@ Andrew Lynch | [Nhyodyne Z80 MBC] | MBC | MBC_std.rom | 38400 | | [Rhyophyre Z180 SBC] | - | RPH_std.rom | 38400 | | [N8 Z180 SBC] (date >= 2312) | ECB | N8_std.rom | 38400 | +| [N8 PC] | ECB | N8PC_std.rom | 38400 | Bill Shen @@ -929,6 +930,45 @@ This configuration is for the N8-2312 and latter (4314) revisions `\clearpage`{=latex} +## N8 PC + +This is a variant of the N8 computer. + +* Creator: Dan Werner + +#### ROM Image File: N8PC_std.rom + +| | | +|-------------------|---------------| +| Bus | ECB | +| Default CPU Speed | 9.216 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 38400 Baud | +| Memory Manager | N8 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- PKD: IO=132, SIZE=8X1 +- M6242RTC: IO=160 +- ASCI: IO=64, INTERRUPTS ENABLED +- ASCI: IO=65, INTERRUPTS ENABLED +- TMS: MODE=N8PC, IO=152, SCREEN=80X24, KEYBOARD=KBD +- KBD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=N8, IO=140, DRIVE 0, TYPE=3.5" HD +- FD: MODE=N8, IO=140, DRIVE 1, TYPE=3.5" HD +- PPIDE: MODE=STD, IO=132, MASTER +- PPIDE: MODE=STD, IO=132, SLAVE +- AY38910: MODE=N8, IO=156, CLOCK=3579545 HZ + +#### Notes: + +`\clearpage`{=latex} + ## RCBus Z80 ### RCBus Z80 CPU Module @@ -2494,6 +2534,7 @@ Note: | SIMRTC | SIMH Simulator Real-Time Clock | | MMRTC | NS MM58167B Real-Time Clock (no NVRAM) | | DS12RTC | Dallas Semiconductor DS1288x Real-Time Clock w/ NVRAM | +| M6242 | MSM6242 Real-Time Clock (no NVRAM) | ## DsKy (DiSplay KeYpad) diff --git a/Source/HBIOS/Config/ZETA2_std.asm b/Source/HBIOS/Config/ZETA2_std.asm index 02594945..8d4c5468 100644 --- a/Source/HBIOS/Config/ZETA2_std.asm +++ b/Source/HBIOS/Config/ZETA2_std.asm @@ -56,7 +56,7 @@ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC|N8PC] +FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] ; diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index 0168729b..66925847 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -169,10 +169,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index 29f41163..de27ee41 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index e7f20c08..605fb221 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -164,10 +164,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm index 6d5114e2..49841abe 100644 --- a/Source/HBIOS/cfg_EZZ80.asm +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index d5e0f1da..97ed8e6b 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -163,10 +163,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 83fec71b..630c0987 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm index 250feea3..c53897d3 100644 --- a/Source/HBIOS/cfg_MASTER.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -204,12 +204,15 @@ DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .EQU FALSE ; PCRTC: DISABLE DS12885 etc. RTC +PCRTC_BASE .EQU $C0 ; Default port for PCRTC, like DSRTC. +; MMRTCENABLE .EQU FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .EQU FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; -PCRTCENABLE .EQU FALSE ; PCRTC: DISABLE DS12885 etc. RTC -PCRTC_BASE .EQU $C0 ; Default port for PCRTC, like DSRTC. +M6242RTCENABLE .EQU TRUE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +M6242RTC_BASE .EQU $A0 ; M6242RTC: I/O BASE ADDRESS ; SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index 16eec5f5..a4c0feec 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -162,10 +162,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index 42e30f20..9a645e66 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index fd7789d4..4bde4934 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -165,10 +165,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_MSX.asm b/Source/HBIOS/cfg_MSX.asm index 1eb44a71..c8407895 100644 --- a/Source/HBIOS/cfg_MSX.asm +++ b/Source/HBIOS/cfg_MSX.asm @@ -171,10 +171,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index a640f73b..c0de0dc0 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -168,12 +168,16 @@ SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; -DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC ; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; +DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_N8PC.asm b/Source/HBIOS/cfg_N8PC.asm index bb5d0f7a..0d636bb9 100644 --- a/Source/HBIOS/cfg_N8PC.asm +++ b/Source/HBIOS/cfg_N8PC.asm @@ -168,6 +168,8 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index 3976ad5d..3c3323ce 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm index 7cf132af..b65694c5 100644 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -166,10 +166,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index 201014d5..0fc37129 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index 7ba91648..3102d795 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index cf551e41..e1439d2d 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -171,10 +171,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index 6b0280c1..19f9d8d1 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index d117d785..5adfdd21 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -163,10 +163,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index 7d2eddc0..b2ec1f8d 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -168,10 +168,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_SZ180.asm b/Source/HBIOS/cfg_SZ180.asm index dfe1f5eb..c6bc5256 100644 --- a/Source/HBIOS/cfg_SZ180.asm +++ b/Source/HBIOS/cfg_SZ180.asm @@ -165,10 +165,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) ; PLDSERENABLE .SET FALSE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm index 1ea71320..ed3ab1a5 100644 --- a/Source/HBIOS/cfg_SZ80.asm +++ b/Source/HBIOS/cfg_SZ80.asm @@ -158,11 +158,13 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; -MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) ; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) ; diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index d01905ba..5b9e2032 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -166,10 +166,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index 8b239077..3e659a06 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -155,10 +155,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index 7ec8374e..ff8f6d83 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -166,10 +166,14 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] ; DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) ; DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) ; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG SSERSTATUS .SET $FF ; SSER: STATUS PORT diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index c2656a53..f5d008a4 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -8955,11 +8955,11 @@ SIZ_INTRTC .EQU $ - ORG_INTRTC ; #IF (M6242RTCENABLE) ORG_M6242RTC .EQU $ - #INCLUDE "m6242.asm" + #INCLUDE "m6242rtc.asm" SIZ_M6242RTC .EQU $ - ORG_M6242RTC - .ECHO "M6242 occupies " - .ECHO SIZ_M6242RTC - .ECHO " bytes.\n" + MEMECHO "M6242RTC occupies " + MEMECHO SIZ_M6242RTC + MEMECHO " bytes.\n" #ENDIF ; #IF (SSERENABLE) diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 6af11622..d34e06b3 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -438,10 +438,10 @@ RTCDEV_DS7 .EQU $04 ; DS1307 (I2C) RTCDEV_RP5 .EQU $05 ; RP5C01 RTCDEV_DS5 .EQU $06 ; DS1305 (SPI) RTCDEV_EZ80 .EQU $07 ; EZ80 ON-CHIP RTC -RTCDEV_PC .EQU $08 ; PC style parallel RTC +RTCDEV_PC .EQU $08 ; PC STYLE PARALLEL RTC RTCDEV_MM .EQU $09 ; NS MM58167B RTC (NO NVRAM) RTCDEV_DS12 .EQU $0A ; DS1288X -RTCDEV_M6242 .EQU $0B ; DS1288X +RTCDEV_M6242 .EQU $0B ; OKI MSM6242 RTC (NO NVRAM) ; ; DSKY DEVICE IDS ; diff --git a/Source/HBIOS/m6242.asm b/Source/HBIOS/m6242rtc.asm similarity index 65% rename from Source/HBIOS/m6242.asm rename to Source/HBIOS/m6242rtc.asm index 8e416d6b..15ca3a07 100644 --- a/Source/HBIOS/m6242.asm +++ b/Source/HBIOS/m6242rtc.asm @@ -20,26 +20,26 @@ M6242RTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) ; a:filedate -REG_1SEC .EQU $00 -REG_10SEC .EQU $01 -REG_1MIN .EQU $02 -REG_10MIN .EQU $03 -REG_1HR .EQU $04 -REG_10HR .EQU $05 -REG_1DAY .EQU $06 -REG_10DAY .EQU $07 -REG_1MNTH .EQU $08 -REG_10MNTH .EQU $09 -REG_1YEAR .EQU $0A -REG_10YEAR .EQU $0B -REG_DAYWEEK .EQU $0C ; NOT USED BY THIS DRIVER -REG_CONTROL1 .EQU $0D -REG_CONTROL2 .EQU $0E -REG_CONTROL3 .EQU $0F +M6242RTC_REG_1SEC .EQU $00 +M6242RTC_REG_10SEC .EQU $01 +M6242RTC_REG_1MIN .EQU $02 +M6242RTC_REG_10MIN .EQU $03 +M6242RTC_REG_1HR .EQU $04 +M6242RTC_REG_10HR .EQU $05 +M6242RTC_REG_1DAY .EQU $06 +M6242RTC_REG_10DAY .EQU $07 +M6242RTC_REG_1MNTH .EQU $08 +M6242RTC_REG_10MNTH .EQU $09 +M6242RTC_REG_1YEAR .EQU $0A +M6242RTC_REG_10YEAR .EQU $0B +M6242RTC_REG_DAYWEEK .EQU $0C ; NOT USED BY THIS DRIVER +M6242RTC_REG_CONTROL1 .EQU $0D +M6242RTC_REG_CONTROL2 .EQU $0E +M6242RTC_REG_CONTROL3 .EQU $0F - .ECHO "M6242: IO=" - .ECHO M6242RTC_BASE - .ECHO "\n" + DEVECHO "M6242RTC: IO=" + DEVECHO M6242RTC_BASE + DEVECHO "\n" M6242RTC_INIT: LD A, (RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? @@ -47,7 +47,7 @@ M6242RTC_INIT: RET NZ ; IF ALREADY ACTIVE, ABORT CALL NEWLINE ; FORMATTING - PRTS("M6242 RTC: $") + PRTS("M6242RTC: $") ; PRINT RTC LATCH PORT ADDRESS PRTS("IO=0x$") ; LABEL FOR IO ADDRESS @@ -65,15 +65,15 @@ M6242RTC_INIT: M6242RTC_INIT1: ; ENSURE DEVICE IS RESET AND NOT IN TEST MODE LD A, 05h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR - OUT (REG_CONTROL3 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL3 + M6242RTC_BASE), A LD A, 05h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR - OUT (REG_CONTROL3 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL3 + M6242RTC_BASE), A LD A, 04h ; TURN OFF ALL TEST MODE BITS, SET 24 HOUR - OUT (REG_CONTROL3 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL3 + M6242RTC_BASE), A LD A, 00h ; LET CLOCK RUN - OUT (REG_CONTROL1 + M6242RTC_BASE), A - OUT (REG_CONTROL2 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL1 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL2 + M6242RTC_BASE), A ; DISPLAY CURRENT TIME LD HL, M6242RTC_BCDBUF ; POINT TO BCD BUF @@ -90,18 +90,18 @@ M6242RTC_INIT1: ; M6242RTC_DETECT: LD A, 01h ; TURN ON REST BIT - OUT (REG_CONTROL3 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL3 + M6242RTC_BASE), A CALL DLY64 CALL DLY64 - IN A,(REG_CONTROL3 + M6242RTC_BASE) + IN A,(M6242RTC_REG_CONTROL3 + M6242RTC_BASE) AND 01h CP 01h JR NZ, M6242RTC_DETECTERR ; IF NOT MATCH, ERROR LD A, 00h ; TURN OFF REST BIT - OUT (REG_CONTROL3 + M6242RTC_BASE), A + OUT (M6242RTC_REG_CONTROL3 + M6242RTC_BASE), A CALL DLY64 CALL DLY64 - IN A,(REG_CONTROL3 + M6242RTC_BASE) + IN A,(M6242RTC_REG_CONTROL3 + M6242RTC_BASE) AND 01h CP 00h JR NZ, M6242RTC_DETECTERR ; IF NOT MATCH, ERROR @@ -165,73 +165,73 @@ M6242RTC_SETALM: M6242RTC_GETTIM: PUSH HL PUSH BC - IN A,(REG_10YEAR + M6242RTC_BASE) + IN A,(M6242RTC_REG_10YEAR + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1YEAR + M6242RTC_BASE) + IN A,(M6242RTC_REG_1YEAR + M6242RTC_BASE) AND 0FH OR C LD (HL),A INC HL - IN A,(REG_10MNTH + M6242RTC_BASE) + IN A,(M6242RTC_REG_10MNTH + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1MNTH + M6242RTC_BASE) + IN A,(M6242RTC_REG_1MNTH + M6242RTC_BASE) AND 0FH OR C LD (HL),A INC HL - IN A,(REG_10DAY + M6242RTC_BASE) + IN A,(M6242RTC_REG_10DAY + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1DAY + M6242RTC_BASE) + IN A,(M6242RTC_REG_1DAY + M6242RTC_BASE) AND 0FH OR C LD (HL),A INC HL - IN A,(REG_10HR + M6242RTC_BASE) + IN A,(M6242RTC_REG_10HR + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1HR + M6242RTC_BASE) + IN A,(M6242RTC_REG_1HR + M6242RTC_BASE) AND 0FH OR C LD (HL),A INC HL - IN A,(REG_10MIN + M6242RTC_BASE) + IN A,(M6242RTC_REG_10MIN + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1MIN + M6242RTC_BASE) + IN A,(M6242RTC_REG_1MIN + M6242RTC_BASE) AND 0FH OR C LD (HL),A INC HL - IN A,(REG_10SEC + M6242RTC_BASE) + IN A,(M6242RTC_REG_10SEC + M6242RTC_BASE) RLA RLA RLA RLA LD C,A - IN A,(REG_1SEC + M6242RTC_BASE) + IN A,(M6242RTC_REG_1SEC + M6242RTC_BASE) AND 0FH OR C LD (HL),A @@ -252,57 +252,57 @@ M6242RTC_GETTIM: M6242RTC_SETTIM: PUSH HL LD A, (HL) - OUT (REG_1YEAR + M6242RTC_BASE), A + OUT (M6242RTC_REG_1YEAR + M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10YEAR + M6242RTC_BASE), A + OUT (M6242RTC_REG_10YEAR + M6242RTC_BASE), A INC HL LD A, (HL) - OUT (REG_1MNTH + M6242RTC_BASE), A + OUT (M6242RTC_REG_1MNTH + M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10MNTH + M6242RTC_BASE), A + OUT (M6242RTC_REG_10MNTH + M6242RTC_BASE), A INC HL LD A, (HL) - OUT (REG_1DAY+ M6242RTC_BASE), A + OUT (M6242RTC_REG_1DAY+ M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10DAY + M6242RTC_BASE), A + OUT (M6242RTC_REG_10DAY + M6242RTC_BASE), A INC HL LD A, (HL) - OUT (REG_1HR + M6242RTC_BASE), A + OUT (M6242RTC_REG_1HR + M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10HR + M6242RTC_BASE), A + OUT (M6242RTC_REG_10HR + M6242RTC_BASE), A INC HL LD A, (HL) - OUT (REG_1MIN + M6242RTC_BASE), A + OUT (M6242RTC_REG_1MIN + M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10MIN + M6242RTC_BASE), A + OUT (M6242RTC_REG_10MIN + M6242RTC_BASE), A INC HL LD A, (HL) - OUT (REG_1SEC + M6242RTC_BASE), A + OUT (M6242RTC_REG_1SEC + M6242RTC_BASE), A RRA RRA RRA RRA - OUT (REG_10SEC + M6242RTC_BASE), A + OUT (M6242RTC_REG_10SEC + M6242RTC_BASE), A POP HL XOR A ; SIGNAL SUCCESS RET ; AND RETURN diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 11601cf7..e2985158 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -27,8 +27,7 @@ ; 23. SZ80 S100 Computers Z80-based System ; 24. RCEZ80 RCBus eZ80 ; 25. MSX MSX Computers -; 26. N8PC MSX-ish Z180 ATX SBC w/ onboard video and sound -; +; 26. N8PC MSX-ish Z180 ATX SBC w/ onboard video and sound ; ; INCLUDE BUILD VERSION ; diff --git a/Source/ReadMe.txt b/Source/ReadMe.txt index e8f86b82..451cd92b 100644 --- a/Source/ReadMe.txt +++ b/Source/ReadMe.txt @@ -200,7 +200,7 @@ to determine the component of the configuration filename: GMZ180 Doug Jacksons' Genesis Z180 System NABU NABU w/ Les Bird's RomWBW Option Board FZ80 S100 Computers FPGA Z80 - N8PC MSX-ish Z180 ATX SBC w/ onboard video and sound + N8PC MSX-ish Z180 ATX SBC w/ onboard video and sound Configuration files are found in the Source\HBIOS\Config directory. If you look in the this directory, you will see a