diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 0eb02e8c..de383635 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -37,6 +37,7 @@ Version 3.6 - DDW: Added support for the 'N8PC' platform. Includes support for the M6242 RTC chip - JMD: Added VGMINFO application - WBW: Created SCSI Driver derived from code from Jay Cotton +- WBW: Add official RC2014 platform (derived from RCZ80) Version 3.5.1 ------------- diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index e196f2d6..da847854 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index c3fbed10..01c50a59 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf index 3b86d5da..110bdc85 100644 Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ diff --git a/Doc/RomWBW Introduction.pdf b/Doc/RomWBW Introduction.pdf index 40ab367a..d3e407ce 100644 Binary files a/Doc/RomWBW Introduction.pdf and b/Doc/RomWBW Introduction.pdf differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 2d25c196..db616f87 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index aa562ef4..bc7481f2 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/ReadMe.md b/ReadMe.md index f2c0b5dc..425bf73f 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -7,7 +7,7 @@ **RomWBW Introduction** \ Version 3.6 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -12 Dec 2025 +05 Jan 2026 # Overview diff --git a/ReadMe.txt b/ReadMe.txt index a5bfc9fa..a3211036 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW Introduction Wayne Warthen (wwarthen@gmail.com) -12 Dec 2025 +05 Jan 2026 diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md index dea1c43e..9447da28 100644 --- a/Source/Doc/Hardware.md +++ b/Source/Doc/Hardware.md @@ -28,6 +28,7 @@ including RC26, RC40, RC80, and BP80. | **Description** | **Bus** | **ROM Image File** | **Baud Rate** | |-------------------------------------------------------------|---------|------------------------------|--------------:| +| [RC2014 Z80 CPU Module], 512K RAM/ROM | RCBus | RC2014_std.rom | 115200 | | [RCBus Z80 CPU Module], 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 | | [RCBus Z80 CPU Module (KIO)], 512K w/KIO | RCBus | RCZ80_kio_std.rom | 115200 | | [RCBus Z180 CPU Module (External)] | RCBus | RCZ180_ext_std.rom | 115200 | @@ -973,6 +974,59 @@ This is a variant of the N8 computer. ## RCBus Z80 +The RC2014 ROM is for the official RC2014 Kits by Spencer Owen. + +* Creator: Spencer Owen +* Google Groups: [RC2014-Z80](https://groups.google.com/g/rc2014-z80) +* Github: [RC2014](https://github.com/RC2014Z80/RC2014) + +### RC2014 Z80 CPU Module + +Generic Rom Image. + +#### ROM Image File: RC2014_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 7.372 MHz | +| Interrupts | Mode 1 | +| System Timer | None | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 + +`\clearpage`{=latex} + ### RCBus Z80 CPU Module Generic Rom Image. diff --git a/Source/HBIOS/Build.cmd b/Source/HBIOS/Build.cmd index 29a072a6..3b67e140 100644 --- a/Source/HBIOS/Build.cmd +++ b/Source/HBIOS/Build.cmd @@ -235,8 +235,9 @@ call Build ZETA2 std || exit /b call Build N8 std || exit /b call Build N8PC std || exit /b call Build MK4 std || exit /b -call Build RCZ80 std || exit /b +call Build RC2014 std || exit /b call Build RCEZ80 std || exit /b +call Build RCZ80 std || exit /b call Build RCZ80 kio_std || exit /b call Build EZZ80 easy_std || exit /b call Build EZZ80 tiny_std || exit /b diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index be402d51..a5cf686e 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -27,7 +27,7 @@ $ErrorAction = 'Stop' # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80", "MSX" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RC2014", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80", "MSX" $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "SZ180", "EPITX", "GMZ180","N8PC" $PlatformListZ280 = "RCZ280" diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index 20be672d..974d5e96 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -19,6 +19,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="N8PC"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="RC2014"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RCEZ80"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh diff --git a/Source/HBIOS/Config/RC2014_std.asm b/Source/HBIOS/Config/RC2014_std.asm new file mode 100644 index 00000000..0247c850 --- /dev/null +++ b/Source/HBIOS/Config/RC2014_std.asm @@ -0,0 +1,112 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RC2014 Z80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED +#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +; +#INCLUDE "cfg_RC2014.asm" +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER +CHSCSIENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE MASS STORAGE DEVICES (REQUIRES CHNATIVEENABLE) +CHUFIENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE UFI FLOPPY DISK DEVICES (REQUIRES CHNATIVEENABLE) +CHNATIVEFORCE .SET FALSE ; CH376: DISABLE AUTO-DETECTION OF MODULE - ASSUME ITS INSTALLED +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) +IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) +SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index 658590ae..3aa57ae6 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index cb4cdc94..802117bc 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index f851f75f..a831899d 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm index 606f6790..54b02180 100644 --- a/Source/HBIOS/cfg_EZZ80.asm +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index c7cd2485..8dc43d88 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 52ae85c4..719e87d7 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm index f23b1b91..6664a4b8 100644 --- a/Source/HBIOS/cfg_MASTER.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -49,7 +49,7 @@ ; #INCLUDE "hbios.inc" ; -PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .EQU FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index 17159de1..d990dd87 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index c7d811d2..22a1c406 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index 11465939..f28b9ceb 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -51,7 +51,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index 12d4f2d6..abd5c5a3 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_N8PC.asm b/Source/HBIOS/cfg_N8PC.asm index b7f6f0c5..5ccf77d7 100644 --- a/Source/HBIOS/cfg_N8PC.asm +++ b/Source/HBIOS/cfg_N8PC.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_N8PC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_N8PC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index ee352249..532b8bc1 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_RC2014.asm b/Source/HBIOS/cfg_RC2014.asm new file mode 100644 index 00000000..002f28e8 --- /dev/null +++ b/Source/HBIOS/cfg_RC2014.asm @@ -0,0 +1,425 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RC2014 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RC2014", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE +#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED +#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RC2014 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] +NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME +BT_REC_TYPE .SET BT_REC_NONE ; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI] +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +STRICTPART .SET TRUE ; ENFORCE STRICT PARTITION TABLE VALIDATION +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMFONTS .SET TRUE ; LOAD FONTS FROM ROM +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +PCFCLK .SET PCFCLK_8 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12] +PCFTRNS .SET PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15] +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6F ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +; +MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) +; +DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) +; +M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DLPSERENABLE .SET FALSE ; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM) +; +TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM) +TSERCFG .SET SER_9600_8N1 ; TSER: SERIAL LINE CONFIG +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_RC ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $18 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_RC ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $20 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1MODE .SET PPIDEMODE_STD ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2MODE .SET PPIDEMODE_STD ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) +; +SCSIENABLE .SET FALSE ; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] +AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm index e64e22b8..3f66e2f1 100644 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index 70f5d868..55478379 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index 71decae8..4553f374 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index 4bbcc25e..74f15542 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC +PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index 101c4ba0..1010d4a0 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index 7876ea5c..71c09dc3 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index 81e0da08..eae3763e 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_SZ180.asm b/Source/HBIOS/cfg_SZ180.asm index 1179cb61..a8365ad0 100644 --- a/Source/HBIOS/cfg_SZ180.asm +++ b/Source/HBIOS/cfg_SZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_SZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm index aa8d1726..1f3bafc9 100644 --- a/Source/HBIOS/cfg_SZ80.asm +++ b/Source/HBIOS/cfg_SZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_SZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_TEMPLATE.asm b/Source/HBIOS/cfg_TEMPLATE.asm new file mode 100644 index 00000000..1b5aeba9 --- /dev/null +++ b/Source/HBIOS/cfg_TEMPLATE.asm @@ -0,0 +1,526 @@ +; +;================================================================================================== +; ROMWBW GLOBAL MASTER CONFIGURATION FILE +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE +#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED +#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +CPUFAM .SET CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] +NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET FALSE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME +BT_REC_TYPE .SET BT_REC_NONE ; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI] +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +STRICTPART .SET TRUE ; ENFORCE STRICT PARTITION TABLE VALIDATION +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 1000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMFONTS .SET TRUE ; LOAD FONTS FROM ROM +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET FALSE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) +Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) +Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) +Z280_TIMER .SET FALSE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER +; +N8_PPI0 .SET $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR +N8_PPI1 .SET $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR +N8_RTC .SET $88 ; N8: RTC LATCH REGISTER ADR +N8_ACR .SET $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR +N8_RMAP .SET $96 ; N8: ROM PAGE REGISTER ADR +N8_DEFACR .SET $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) +; +RPH_PPI0 .SET $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR +RPH_RTC .SET $84 ; RPH: RTC LATCH REGISTER ADR +RPH_ACR .SET $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR +RPH_DEFACR .SET $00 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) +; +MK4_IDE .SET $80 ; MK4: IDE REGISTERS BASE ADR +MK4_XAR .SET $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR +MK4_SD .SET $89 ; MK4: SD CARD CONTROL REGISTER ADR +MK4_RTC .SET $8A ; MK4: RTC LATCH REGISTER ADR +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET 614400 ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6F ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET FALSE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD +GM7303BASE .SET $30 ; BASE ADDRESS FOR GM3703 BOARD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +PCRTCENABLE .SET FALSE ; PCRTC: DISABLE DS12885 etc. RTC +PCRTC_BASE .SET $C0 ; Default port for PCRTC, like DSRTC. +; +MMRTCENABLE .SET FALSE ; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM) +; +DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM) +DS12RTC_BASE .SET $70 ; DS12RTC: I/O BASE ADDRESS +; +M6242RTCENABLE .SET TRUE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) +M6242RTC_BASE .SET $A0 ; M6242RTC: I/O BASE ADDRESS +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DLPSERENABLE .SET FALSE ; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM) +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +Z2UOSC .SET 1843200 ; Z2U: OSC FREQUENCY IN MHZ +Z2UOSCEXT .SET TRUE ; Z2U: USE EXTERNAL OSCILLATOR +Z2U0BASE .SET $10 ; Z2U 0: BASE I/O ADDRESS +Z2U0CFG .SET DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG +Z2U0HFC .SET FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +GDCMODE .SET GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH] +GDCMON .SET GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA] +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_NONE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_NONE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0MODE .SET PPIDEMODE_NONE ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1MODE .SET PPIDEMODE_NONE ; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 1B (SLAVE): 8 BIT XFER +PPIDE2MODE .SET PPIDEMODE_NONE ; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B] +PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET FALSE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET FALSE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS +PPPSDENABLE .SET FALSE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPPCONENABLE .SET FALSE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +ESPCONENABLE .SET FALSE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_NONE ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_NONE ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_NONE ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) +; +SCSIENABLE .SET FALSE ; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM) +SCSITRACE .SET 1 ; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SCSICNT .SET 2 ; SCSI: NUMBER OF TARGET DEVICES (1-2) +SCSI_TID .SET 0 ; SCSI: TARGET DEVICE ID (0-6) +SCSI0_LUN .SET 0 ; SCSI0: TARGET LUN +SCSI1_LUN .SET 1 ; SCSI1: TARGET LUN +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +SN76489CHNOUT .SET SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] +AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +SPKPORT .SET RTCIO ; SPK: THE PORT WITH THE SPEAKER IO BIT +SPKSHADOW .SET HB_RTCVAL ; SPK: THE SHADOW VALUE FOR THE PORT THAT HAS TO BE MAINTAINED +SPKMASK .SET 00000100b ; SPK: THE BIT MASK TO ACTUALLY TOGGLE +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) +; +; EZ80 SETTINGS +; +EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS +EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS +EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) +; +EZ80UARTENABLE .SET FALSE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) +EZ80RTCENABLE .SET FALSE ; EZ80 ON CHIP RTC +EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] +EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO +; +; BUS TIMING FOR PAGED MEMORY ACCESS (CS3) +EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES +EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_MEM_WS .SET 5 ; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT +EZ80_MEM_MIN_WS .SET 0 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +; +; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2) +EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES +EZ80_IO_WS .SET 5 ; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT +EZ80_IO_MIN_NS .SET 320 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_IO_MIN_WS .SET 6 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +; +; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD +EZ80_WSMD_TYP .SET EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT] +; +; BUS TIMING FOR ON CHIP ROM +; +EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7) +EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC +EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED) diff --git a/Source/HBIOS/cfg_UNA.asm b/Source/HBIOS/cfg_UNA.asm index 4c3ff790..f4ab3ab0 100644 --- a/Source/HBIOS/cfg_UNA.asm +++ b/Source/HBIOS/cfg_UNA.asm @@ -15,7 +15,7 @@ ; #INCLUDE "../UBIOS/ubios.inc" ; -;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] ; diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index 70271cb6..17e7a5e3 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index 2c666b2a..76f9639d 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index 3bc56c5f..4adbeb8a 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] +PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 58cf4417..8a75c9ae 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -211,6 +211,7 @@ PLT_SZ80 .EQU 23 ; S100 COMPUTERS Z80 SYSTEM PLT_RCEZ80 .EQU 24 ; RCBUS W/ eZ80 PLT_MSX .EQU 25 ; MSX COMPUTER PLT_N8PC .EQU 26 ; N8PC (HOME COMPUTER, ATX FORMAT) Z180 SBC +PLT_RC2014 .EQU 27 ; OFFICIAL RC2014 Z80 KITS ; ; HBIOS GLOBAL ERROR RETURN VALUES ; diff --git a/Source/HBIOS/plt_pretty.inc b/Source/HBIOS/plt_pretty.inc index f23abaaa..c63c514b 100644 --- a/Source/HBIOS/plt_pretty.inc +++ b/Source/HBIOS/plt_pretty.inc @@ -41,6 +41,7 @@ ; S100 Z80 ; RCBUS eZ80 ; N8PC ZS180 +; RC2014 ; STR_PLT_PRETTY: ; @@ -189,5 +190,17 @@ STR_PLT_PRETTY: .DB "| _ \\ / __| | _ ) | | | | / __| ___ |_ / ( _ ) / \\ ",10,13 .DB "| / | (__ | _ \\ | |_| | \\__ \\ / -_) / / / _ \\ | () |",10,13 .DB "|_|_\\ \\___| |___/ \\___/ |___/ \\___| /___| \\___/ \\__/",10,13 +#ENDIF +#IF (PLATFORM == PLT_RC2014) + .DB " ___ ___ ___ __ _ _ _",10,13 + .DB "| _ \\ / __| |_ ) / \\ / | | | |",10,13 + .DB "| / | (__ / / | () | | | |_ _|",10,13 + .DB "|_|_\\ \\___| /___| \\__/ |_| |_|",10,13 #ENDIF .DB "$" + + + + + + \ No newline at end of file diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 624bb936..3c1a40a5 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -28,6 +28,7 @@ ; 24. RCEZ80 RCBus eZ80 ; 25. MSX MSX Computers ; 26. N8PC MSX-ish Z180 ATX SBC w/ onboard video and sound +; 27. RC2014 Official RC2014 Z80 Kits ; ; INCLUDE BUILD VERSION ; diff --git a/Source/ver.inc b/Source/ver.inc index 7d4d147d..476849bb 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 6 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.6.0-dev.47" +#DEFINE BIOSVER "3.6.0-dev.48" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index c9aa85f4..1944f0ef 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 6 rup equ 0 rtp equ 0 biosver macro - db "3.6.0-dev.47" + db "3.6.0-dev.48" endm