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Add RC2014 UART, Improve SD protocol fix

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- RC2014 and related platforms will autodetect a UART at 0xA0 and 0xA8
- Ensure that CS fully brackets all SD I/O
This commit is contained in:
Wayne Warthen
2020-04-09 11:49:09 -07:00
parent 5c3f75d504
commit f4daaa91a4
23 changed files with 121 additions and 24 deletions
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2
Source/HBIOS/Config/RCZ180_ext.asm
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@@ -34,8 +34,8 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

2
Source/HBIOS/Config/RCZ180_nat.asm
View File

@@ -34,8 +34,8 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;

2
Source/HBIOS/Config/RCZ80_std.asm
View File

@@ -28,8 +28,8 @@
;
CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

3
Source/HBIOS/Config/SCZ180_126.asm
View File

@@ -36,10 +36,9 @@ Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

3
Source/HBIOS/Config/SCZ180_130.asm
View File

@@ -43,10 +43,9 @@ DIAGENABLE .SET FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
TIMRTCENABLE .SET TRUE ; ENABLE PERIODIC TIMER CLOCK DRIVER (TIMRTC.ASM)
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

3
Source/HBIOS/Config/SCZ180_131.asm
View File

@@ -43,10 +43,9 @@ DIAGENABLE .SET FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
TIMRTCENABLE .SET TRUE ; ENABLE PERIODIC TIMER CLOCK DRIVER (TIMRTC.ASM)
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
;
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

9
Source/HBIOS/cfg_ezz80.asm
View File

@@ -70,7 +70,14 @@ DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

1
Source/HBIOS/cfg_master.asm
View File

@@ -100,6 +100,7 @@ UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

1
Source/HBIOS/cfg_mk4.asm
View File

@@ -85,6 +85,7 @@ UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

1
Source/HBIOS/cfg_n8.asm
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@@ -88,6 +88,7 @@ UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

9
Source/HBIOS/cfg_rcz180.asm
View File

@@ -73,7 +73,14 @@ DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

9
Source/HBIOS/cfg_rcz80.asm
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@@ -69,7 +69,14 @@ DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

1
Source/HBIOS/cfg_sbc.asm
View File

@@ -79,6 +79,7 @@ UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

9
Source/HBIOS/cfg_scz180.asm
View File

@@ -68,7 +68,14 @@ DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG

1
Source/HBIOS/cfg_zeta.asm
View File

@@ -73,6 +73,7 @@ UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

1
Source/HBIOS/cfg_zeta2.asm
View File

@@ -78,6 +78,7 @@ UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

5
Source/HBIOS/dbgmon.asm
View File

@@ -31,7 +31,10 @@ BUFLEN .EQU 40 ; INPUT LINE LENGTH
JP DSKY_ENTRY
JP UART_ENTRY
;
;#DEFINE USEDELAY
#IF DSKYENABLE
#DEFINE USEDELAY
#ENDIF
;
#INCLUDE "util.asm"
;
;__UART_ENTRY_________________________________________________________________

4
Source/HBIOS/dsrtc.asm
View File

@@ -120,6 +120,8 @@ DSRTC_IDLE .EQU %00101000 ; QUIESCENT STATE
;
#ENDIF
;
RTCDEF .SET DSRTC_IDLE ; FOR HBIOS MAINLINE
;
DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
;
; RTC DEVICE PRE-INITIALIZATION ENTRY
@@ -129,7 +131,7 @@ DSRTC_PREINIT:
; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
; TO THEIR QUIESENT STATE
LD A,(RTCVAL) ; GET CURRENT SHADOW REG VAL
AND DSRTC_MASK ; CLEAR OUR BITS
AND ~DSRTC_MASK ; CLEAR OUR BITS
OR DSRTC_IDLE ; SET OUR IDLE BITS
LD (RTCVAL),A ; SAVE IT
;

8
Source/HBIOS/hbios.asm
View File

@@ -132,6 +132,12 @@ CTCC .EQU CTCBASE + 2 ; CTC: CHANNEL C REGISTER ADR
CTCD .EQU CTCBASE + 3 ; CTC: CHANNEL D REGISTER ADR
#ENDIF
;
; THIS EQUATE IS UPDATED BY DRIVER INCLUDES THAT SHARE THE RTC LATCH.
; AS DRIVER IS INCLUDED, IT WILL USE .SET TO SET ANY BITS THEY OWN
; AND WANT TO SET AS DEFAULT.
;
RTCDEF .EQU 0 ; ALLOWS DRIVERS TO SET BITS
;
;
;
#IFNDEF APPBOOT
@@ -4100,7 +4106,7 @@ HB_SECS .FILL 4,0 ; 32 BIT SECONDS COUNTER
;
HB_CPUTYPE .DB 0 ; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG
;
RTCVAL .DB 0 ; SHADOW VALUE FOR RTC LATCH PORT
RTCVAL .DB RTCDEF ; SHADOW VALUE FOR RTC LATCH PORT
;
HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK)
;

51
Source/HBIOS/sd.asm
View File

@@ -119,31 +119,40 @@ SD_NOPULLUP .EQU TRUE ; ASSUME NO PULLUP
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE
SD_OPRMSK .EQU %10000111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC
SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT
SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK
SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU)
;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
;
#IF (SDMODE == SDMODE_N8) ; UNMODIFIED N8-2511
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE
SD_OPRMSK .EQU %01000111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC
SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT
SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK
SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU)
;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
;
#IF (SDMODE == SDMODE_CSIO) ; N8-2312
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00000000 ; QUIESCENT STATE
SD_OPRMSK .EQU %00000100 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
;
#IF (SDMODE == SDMODE_PPI) ; PPISD
@@ -165,6 +174,7 @@ SD_DO .EQU %10000000 ; PPIB:7 IS DATA OUT (CARD -> CPU)
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU SIO_MCR ; UART MCR PORT (OUTPUT: CS, CLK, DIN)
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE
SD_OPRMSK .EQU %00101101 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
SD_INPREG .EQU SIO_MSR ; INPUT REGISTER IS MSR
SD_CS0 .EQU %00001000 ; UART MCR:3 IS SELECT
SD_CLK .EQU %00000100 ; UART MCR:2 IS CLOCK
@@ -198,10 +208,13 @@ SD_TRDR .EQU Z180_TRDR
SD_DEVCNT .EQU SDCNT ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED)
SD_OPRMSK .EQU %00001100 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD
SD_CS1 .EQU %00001000 ; RTC:3 IS SELECT FOR SECONDARY SPI CARD
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF
;
#IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO)
@@ -318,6 +331,7 @@ SD_INIT:
CALL PRTHEXBYTE
;
LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE
AND ~SD_OPRMSK ; CLEAR OUR BITS
OR SD_OPRDEF ; SET OUR BIT DEFAULTS
LD (RTCVAL),A ; SAVE IT
#ENDIF
@@ -329,6 +343,7 @@ SD_INIT:
CALL PRTHEXBYTE
;
LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE
AND ~SD_OPRMSK ; CLEAR OUR BITS
OR SD_OPRDEF ; SET OUR BIT DEFAULTS
LD (RTCVAL),A ; SAVE IT
#ENDIF
@@ -349,6 +364,7 @@ SD_INIT:
CALL PRTHEXBYTE
;
LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE
AND ~SD_OPRMSK ; CLEAR OUR BITS
OR SD_OPRDEF ; SET OUR BIT DEFAULTS
LD (RTCVAL),A ; SAVE IT
#ENDIF
@@ -412,6 +428,7 @@ SD_INIT:
CALL PRTHEXBYTE
;
LD A,(RTCVAL) ; GET RTC PORT SHADOW VALUE
AND ~SD_OPRMSK ; CLEAR OUR BITS
OR SD_OPRDEF ; SET OUR BIT DEFAULTS
LD (RTCVAL),A ; SAVE IT
#ENDIF
@@ -844,6 +861,12 @@ SD_INITCARD1:
CALL SD_PUT ; SEND 8 CLOCKS
POP BC ; RESTORE LOOP CONTROL
DJNZ SD_INITCARD1 ; LOOP AS NEEDED
;
; MAKE SURE WE FINISH SENDING
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
CALL SD_WAITTX ; WAIT FOR TE TO CLEAR
CALL DLY4 ; WAIT A BIT MORE FOR FINAL BIT
#ENDIF
;
; PUT CARD IN IDLE STATE
CALL SD_GOIDLE ; GO TO IDLE
@@ -1538,8 +1561,8 @@ SD_SETUP:
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
; CSIO SETUP FOR Z180 CSIO
; LD A,2 ; 18MHz/20 <= 400kHz
LD A,6 ; ???
; LD A,2 ; DIV 80, 225KHZ @ 18MHZ CLK
LD A,6 ; DIV 1280, 14KHZ @ 18MHZ CLK
OUT0 (SD_CNTR),A
#ENDIF
;
@@ -1556,7 +1579,6 @@ SD_SETUP:
#ENDIF
;
#IF (SDMODE == SDMODE_UART)
SD_OPRMSK .EQU (SD_CS0 | SD_CLK | SD_DI)
IN A,(SD_OPRREG) ; OPRREG == SIO_MCR
AND ~SD_OPRMSK ; MASK OFF SD CONTROL BITS
OR SD_OPRDEF ; SET DEFAULT BITS
@@ -1605,9 +1627,10 @@ SD_CHKWP:
; SELECT CARD
;
SD_SELECT:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
CALL SD_WAITTX
#ENDIF
; ; FINISH SENDING BEFORE ASSERTING CS!
;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
; CALL SD_WAITTX
;#ENDIF
;
LD A,(IY+SD_DEV) ; GET CURRENT DEVICE
OR A ; SET FLAGS
@@ -1641,6 +1664,22 @@ SD_SELECT2:
; DESELECT CARD
;
SD_DESELECT:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC))
; DON'T REMOVE CS UNTIL WE ARE DONE SENDING!
CALL SD_WAITTX ; WAIT FOR TE TO CLEAR
;
; ACCORDING TO Z180 DOCS, IT MAY TAKE UP TO 1 BIT TIME TO
; FINISH SENDING AFTER TE IS CLEARED. THE DELAY BELOW WILL
; DO THIS FOR THE SLOWEST POSSIBLE SEND RATE WHICH IS
; CLK / 1320, SO DELAY AT LEAST 1320 T-STATES
;CALL DLY64 ; DELAY FOR FINAL BIT
;
; IN PRACTICE, IT LOOKS LIKE THIS WORST CASE SCENARIO NEVER
; OCCURS. FOR NOW, USE A SMALL DELAY WHICH SEEMS TO BE MORE
; THAN ADEQUATE BASED ON LOGIC ANALYZER TRACES.
CALL DLY4 ; DELAY FOR FINAL BIT
#ENDIF
;
LD A,(SD_OPRVAL)
#IF (SD_DEVCNT > 1)
AND ~(SD_CS0 | SD_CS1)

16
Source/HBIOS/uart.asm
View File

@@ -626,5 +626,21 @@ UART_CFG:
.DW UARTCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF
#IF (UARTRC)
; UARTRC SERIAL PORT A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB $A0 ; IO PORT BASE (RBR, THR)
.DB $A0 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
; UARTRC SERIAL PORT B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB $A8 ; IO PORT BASE (RBR, THR)
.DB $A8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF
;
UART_CNT .EQU ($ - UART_CFG) / 8