From 0b661442c5173027e4433da171fffaa8838d4c60 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 4 Aug 2019 17:51:29 -0700 Subject: [PATCH 1/2] SIO & ACIA Driver Updates --- Doc/ChangeLog.txt | 3 +- ReadMe.txt | 2 +- Source/CBIOS/ver.inc | 2 +- Source/HBIOS/Config/EZZ80_std.asm | 2 +- Source/HBIOS/Config/RCZ180_sc126.asm | 2 +- Source/HBIOS/acia.asm | 920 +++++++++++++++------------ Source/HBIOS/cfg_ezz80.asm | 22 +- Source/HBIOS/cfg_mk4.asm | 4 + Source/HBIOS/cfg_n8.asm | 4 + Source/HBIOS/cfg_rcz180.asm | 24 +- Source/HBIOS/cfg_rcz80.asm | 33 +- Source/HBIOS/cfg_sbc.asm | 20 +- Source/HBIOS/cfg_una.asm | 1 + Source/HBIOS/cfg_zeta.asm | 4 + Source/HBIOS/hbios.asm | 184 +++--- Source/HBIOS/sio.asm | 347 ++++++---- Source/HBIOS/siobaud.inc | 393 ------------ Source/HBIOS/std.asm | 71 ++- Source/HBIOS/uart.asm | 18 +- Source/HBIOS/ver.inc | 2 +- 20 files changed, 957 insertions(+), 1101 deletions(-) delete mode 100644 Source/HBIOS/siobaud.inc diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 175efb5d..4da46964 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -3,8 +3,9 @@ Version 2.9.2 - PMS: Fixed DS1210-related issue resulting in "Invalid BIOS" errors - SCC: Support for SC126 motherboard - WBW: Enable Auto-CTS/DCD in SIO driver for pacing output data -- WBW: Support missing pull-up resistors in SD driver (a common occurence) +- WBW: Support missing pull-up resistors on SPI SD adapter boards (common) - WBW: Support two SIO modules w/ auto-detection +- PMS: Support ECB USB-FIFO board Version 2.9.1 ------------- diff --git a/ReadMe.txt b/ReadMe.txt index a1875a4c..f5277665 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.2-pre.1, 2019-07-22 +Version 2.9.2-pre.2, 2019-08-04 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index 27042a0c..43cecdb0 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.1" +#DEFINE BIOSVER "2.9.2-pre.2" diff --git a/Source/HBIOS/Config/EZZ80_std.asm b/Source/HBIOS/Config/EZZ80_std.asm index beed33aa..b9039f6f 100644 --- a/Source/HBIOS/Config/EZZ80_std.asm +++ b/Source/HBIOS/Config/EZZ80_std.asm @@ -6,4 +6,4 @@ #include "cfg_ezz80.asm" ; CPUOSC .SET 10000000 ; CPU OSC FREQ -DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE) +DEFSERCFG .SET SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG diff --git a/Source/HBIOS/Config/RCZ180_sc126.asm b/Source/HBIOS/Config/RCZ180_sc126.asm index f6fc5cc2..e87c811a 100644 --- a/Source/HBIOS/Config/RCZ180_sc126.asm +++ b/Source/HBIOS/Config/RCZ180_sc126.asm @@ -1,6 +1,6 @@ ; ;================================================================================================== -; RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER +; SC126 ;================================================================================================== ; #include "cfg_rcz180.asm" diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm index 48e54a92..be94d948 100644 --- a/Source/HBIOS/acia.asm +++ b/Source/HBIOS/acia.asm @@ -10,40 +10,56 @@ ; F E D C B A 9 8 7 6 5 4 3 2 1 0 ; -- MSB (D REGISTER) -- -- LSB (E REGISTER) -- ; -; CURRENTLY ONLY SUPPORTS A SINGLE CHIP IN SYSTEM ; -ACIA_DEBUG .EQU FALSE -; -ACIA_NONE .EQU 0 -ACIA_ACIA .EQU 1 +; ACIA STATUS REGISTER: ; -; POSSIBLE BASE I/O ADDRESSES -; NOTE THAT THE ACIA ONLY QUALIFIES ADDRESS BITS 7 & 6, SO -; THE ACIA'S TWO PORTS APPEAR REPEATEDLY OVER AN ADDRESS RANGE -; OF $40 STARTING FROM THE REAL BASE PORT. -; WE TAKE ADVANTAGE OF THIS TO AVOID CONFLICTING WITH SIO -; AND COMPACT FLASH MODULES DURING DETECTION PROBES. +; D7 D6 D5 D4 D3 D2 D1 D0 +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; | /IRQ | PE | OVRN | FE | /CTS | /DCD | TDRE | RDRF | +; +-------+-------+-------+-------+-------+-------+-------+-------+ ; -ACIAA_BASE .EQU $80 + $20 ; MODULE A -ACIAB_BASE .EQU $40 + $20 ; MODULE B +; ACIA CONTROL REGISTER: ; -#IF (INTMODE == 0) +; D7 D6 D5 D4 D3 D2 D1 D0 +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; | RIE | TC2 | TC1 | WS3 | WS2 | WS1 | CDS2 | CDS1 | +; +-------+-------+-------+-------+-------+-------+-------+-------+ ; -ACIA_RTSON .EQU %00010110 ; NO RCV INT, RTS ASSERTED, 8N1, CLK/64 BAUD -ACIA_RTSOFF .EQU %01010110 ; NO RCV INT, RTS DEASSERTED, 8N1, CLK/64 BAUD -; -#ENDIF -; -#IF (INTMODE == 1) +; RIE: RECEIVE INTERRUPT ENABLE (RECEIVE DATA REGISTER FULL) ; -ACIA_RTSON .EQU %10010110 ; RCV INT, RTS ASSERTED, 8N1, CLK/64 BAUD -ACIA_RTSOFF .EQU %11010110 ; RCV INT, RTS DEASSERTED, 8N1, CLK/64 BAUD +; TC: TRANSMIT CONTROL (TRANSMIT DATA REGISTER EMPTY) +; 0 0 - /RTS=LOW, TDRE INT DISABLED +; 0 1 - /RTS=LOW, TDRE INT ENABLED +; 1 0 - /RTS=HIGH, TDRE INT DISABLED +; 1 1 - /RTS=LOW, TRANSMIT BREAK, TDRE INT DISABLED +; +; WS: WORD SELECT (DATA BITS, PARITY, STOP BITS) +; 0 0 0 - 7,E,2 +; 0 0 1 - 7,O,2 +; 0 1 0 - 7,E,1 +; 0 1 1 - 7,O,1 +; 1 0 0 - 8,N,2 +; 1 0 1 - 8,N,1 +; 1 1 0 - 8,E,1 +; 1 1 1 - 8,O,1 +; +; CDS: COUNTER DIVIDE SELECT +; 0 0 - DIVIDE BY 1 +; 0 1 - DIVIDE BY 16 +; 1 0 - DIVIDE BY 64 +; 1 1 - MASTER RESET +; +ACIA_BUFSZ .EQU 32 ; RECEIVE RING BUFFER SIZE +; +ACIA_NONE .EQU 0 +ACIA_ACIA .EQU 1 +; +ACIA_RTSON .EQU %00000000 ; BIT MASK TO ASSERT RTS +ACIA_RTSOFF .EQU %01000000 ; BIT MASK TO DEASSERT RTS ; -#ENDIF - #IF (INTMODE > 1) - .ECHO "*** ERROR: UNSUPPORTED INTMODE FOR ACIA DRIVER!!!\n" - !!! ; FORCE AN ASSEMBLY ERROR + .ECHO "*** ERROR: UNSUPPORTED INTMODE FOR ACIA DRIVER!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR #ENDIF ; ; @@ -54,23 +70,13 @@ ACIA_PREINIT: ; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN ; DISABLED. ; - LD B,ACIA_CNT ; LOOP CONTROL - LD C,0 ; PHYSICAL UNIT INDEX - XOR A ; ZERO TO ACCUM - LD (ACIA_DEV),A ; CURRENT DEVICE NUMBER -ACIA_PREINIT0: + LD B,ACIA_CFGCNT ; LOOP CONTROL + XOR A ; ZERO TO ACCUM + LD (ACIA_DEV),A ; CURRENT DEVICE NUMBER + LD IY,ACIA_CFG ; POINT TO START OF CFG TABLE +ACIA_PREINIT0: PUSH BC ; SAVE LOOP CONTROL - LD A,C ; PHYSICAL UNIT TO A - RLCA ; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES) - RLCA ; ... - RLCA ; ... TO GET OFFSET INTO CFG TABLE - LD HL,ACIA_CFG ; POINT TO START OF CFG TABLE - CALL ADDHLA ; HL := ENTRY ADDRESS - PUSH HL ; SAVE IT - PUSH HL ; COPY CFG DATA PTR - POP IY ; ... TO IY CALL ACIA_INITUNIT ; HAND OFF TO GENERIC INIT CODE - POP DE ; GET ENTRY ADDRESS BACK, BUT PUT IN DE POP BC ; RESTORE LOOP CONTROL ; LD A,(IY+1) ; GET THE ACIA TYPE DETECTED @@ -78,73 +84,73 @@ ACIA_PREINIT0: JR Z,ACIA_PREINIT2 ; SKIP IT IF NOTHING FOUND ; PUSH BC ; SAVE LOOP CONTROL + PUSH IY ; CFG ENTRY ADDRESS + POP DE ; ... TO DE LD BC,ACIA_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL NZ,CIO_ADDENT ; ADD ENTRY IF ACIA FOUND, BC:DE POP BC ; RESTORE LOOP CONTROL ; ACIA_PREINIT2: - INC C ; NEXT PHYSICAL UNIT + LD DE,ACIA_CFGSIZ ; SIZE OF CFG ENTRY + ADD IY,DE ; BUMP IY TO NEXT ENTRY DJNZ ACIA_PREINIT0 ; LOOP UNTIL DONE -; +; +ACIA_PREINIT3: XOR A ; SIGNAL SUCCESS RET ; AND RETURN ; ; ACIA INITIALIZATION ROUTINE ; ACIA_INITUNIT: - CALL ACIA_DETECT ; DETERMINE ACIA TYPE - LD (IY+1),A ; SAVE IN CONFIG TABLE - OR A ; SET FLAGS - RET Z ; ABORT IF NOTHING THERE + CALL ACIA_DETECT ; DETERMINE ACIA TYPE + LD (IY+1),A ; SAVE IN CONFIG TABLE + OR A ; SET FLAGS + RET Z ; ABORT IF NOTHING THERE - ; UPDATE WORKING ACIA DEVICE NUM - LD HL,ACIA_DEV ; POINT TO CURRENT UART DEVICE NUM - LD A,(HL) ; PUT IN ACCUM - INC (HL) ; INCREMENT IT (FOR NEXT LOOP) - LD (IY),A ; UPDATE UNIT NUM + ; UPDATE WORKING ACIA DEVICE NUM + LD HL,ACIA_DEV ; POINT TO CURRENT UART DEVICE NUM + LD A,(HL) ; PUT IN ACCUM + INC (HL) ; INCREMENT IT (FOR NEXT LOOP) + LD (IY),A ; UPDATE UNIT NUM ; #IF (INTMODE == 1) - ; ADD IM1 INT CALL LIST ENTRY - LD L,(IY+6) ; GET RCVBUF PTR - LD H,(IY+7) ; ... INTO HL - LD A,5 ; OFFSET OF INT HANDLER PTR - CALL ADDHLA ; ADD TO HL - LD A,(HL) ; DEREFERENCE - INC HL ; ... - LD H,(HL) ; ... - LD L,A ; ... - CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST + ; ADD IM1 INT CALL LIST ENTRY + LD L,(IY+8) ; GET INT HANDLER PTR + LD H,(IY+9) ; ... INTO HL + CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST #ENDIF - - ; SET DEFAULT CONFIG - LD DE,-1 ; LEAVE CONFIG ALONE - ; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL - ; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS! - JP ACIA_INITDEVX ; IMPLEMENT IT AND RETURN +; +#IF (INTMODE > 1) + .ECHO "*** ERROR: ACIA DEVICE DOES NOT SUPPORT INTMODE 2!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR +#ENDIF +; + ; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED + ; DUE TO THE CONSTRAINTS OF THE ACIA. HERE WE FORCE A GENERIC + ; FAILSAFE CONFIG ONTO THE CHANNEL. IF THE SUBSEQUENT "REAL" + ; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT + ; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG. + CALL ACIA_INITSAFE +; + ; SET DEFAULT CONFIG + LD DE,-1 ; LEAVE CONFIG ALONE + ; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL + ; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS! + JP ACIA_INITDEVX ; IMPLEMENT IT AND RETURN ; ; ; ACIA_INIT: - LD B,ACIA_CNT ; COUNT OF POSSIBLE ACIA UNITS - LD C,0 ; INDEX INTO ACIA CONFIG TABLE + LD B,ACIA_CFGCNT ; COUNT OF POSSIBLE ACIA UNITS + LD IY,ACIA_CFG ; POINT TO START OF CFG TABLE ACIA_INIT1: PUSH BC ; SAVE LOOP CONTROL - - LD A,C ; PHYSICAL UNIT TO A - RLCA ; MULTIPLY BY CFG TABLE ENTRY SIZE (8 BYTES) - RLCA ; ... - RLCA ; ... TO GET OFFSET INTO CFG TABLE - LD HL,ACIA_CFG ; POINT TO START OF CFG TABLE - CALL ADDHLA ; HL := ENTRY ADDRESS - PUSH HL ; COPY CFG DATA PTR - POP IY ; ... TO IY - LD A,(IY+1) ; GET ACIA TYPE OR A ; SET FLAGS CALL NZ,ACIA_PRTCFG ; PRINT IF NOT ZERO - POP BC ; RESTORE LOOP CONTROL - INC C ; NEXT UNIT + LD DE,ACIA_CFGSIZ ; SIZE OF CFG ENTRY + ADD IY,DE ; BUMP IY TO NEXT ENTRY DJNZ ACIA_INIT1 ; LOOP TILL DONE ; XOR A ; SIGNAL SUCCESS @@ -154,91 +160,76 @@ ACIA_INIT1: ; #IF (INTMODE > 0) ; -ACIAA_INT: - LD IY,ACIAA_CFG ; POINT TO CONFIG +ACIA0_INT: + LD IY,ACIA0_CFG ; POINT TO ACIA0 CFG + JR ACIA_INTRCV ; TRY TO RECEIVE FROM IT AND RETURN ; - ; CHECK FOR RECEIVE PENDING - LD C,(IY+3) ; STATUS PORT - IN A,(C) ; GET STATUS - AND $01 ; ISOLATE RECEIVE READY BIT - RET Z ; IF NOT, RETURN WITH Z SET +#IF (ACIACNT >= 2) ; -ACIAA_INT00: - ; HANDLE PENDING RECEIVE - INC C ; DATA PORT - IN A,(C) ; READ PORT - DEC C ; BACK TO CONTROL PORT - LD E,A ; SAVE BYTE READ - LD A,(ACIAA_BUFCNT) ; GET CURRENT BUFFER USED COUNT - CP ACIAA_BUFSZ ; COMPARE TO BUFFER SIZE - JR Z,ACIAA_INT2 ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED - INC A ; INCREMENT THE COUNT - LD (ACIAA_BUFCNT),A ; AND SAVE IT - CP ACIAA_BUFSZ / 2 ; BUFFER GETTING FULL? - JR NZ,ACIAA_INT0 ; IF NOT, BYPASS DEASSERTING RTS - LD A,ACIA_RTSOFF ; VALUE TO DEASSERT RTS - OUT (C),A ; DO IT -ACIAA_INT0: - LD HL,(ACIAA_HD) ; GET HEAD POINTER - LD A,L ; GET LOW BYTE - CP ACIAA_BUFEND & $FF ; PAST END? - JR NZ,ACIAA_INT1 ; IF NOT, BYPASS POINTER RESET - LD HL,ACIAA_BUF ; ... OTHERWISE, RESET TO START OF BUFFER -ACIAA_INT1: - LD A,E ; RECOVER BYTE READ - LD (HL),A ; SAVE RECEIVED BYTE TO HEAD POSITION - INC HL ; INCREMENT HEAD POINTER - LD (ACIAA_HD),HL ; SAVE IT -; -ACIAA_INT2: - ; CHECK FOR MORE PENDING... - IN A,(C) ; GET STATUS - RRA ; READY BIT TO CF - JR C,ACIAA_INT00 ; IF SET, DO SOME MORE - OR $FF ; NZ SET TO INDICATE INT HANDLED - RET ; AND RETURN +ACIA1_INT: + LD IY,ACIA1_CFG ; POINT TO ACIA1 CFG + JR ACIA_INTRCV ; TRY TO RECEIVE FROM IT AND RETURN ; -ACIAB_INT: - LD IY,ACIAB_CFG ; POINT TO CONFIG +#ENDIF +; +; HANDLE INT FOR A SPECIFIC CHANNEL +; BASED ON UNIT CFG POINTED TO BY IY ; - ; CHECK FOR RECEIVE PENDING - LD C,(IY+3) ; STATUS PORT +ACIA_INTRCV: + ; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE + LD C,(IY+3) ; CMD/STAT PORT TO C IN A,(C) ; GET STATUS AND $01 ; ISOLATE RECEIVE READY BIT - RET Z ; IF NOT, RETURN WITH Z SET + RET Z ; NOTHING AVAILABLE ON CURRENT CHANNEL ; -ACIAB_INT00: - ; HANDLE PENDING RECEIVE - INC C ; DATA PORT +ACIA_INTRCV1: + ; RECEIVE CHARACTER INTO BUFFER + INC C ; DATA PORT IN A,(C) ; READ PORT - DEC C ; BACK TO CONTROL PORT - LD E,A ; SAVE BYTE READ - LD A,(ACIAB_BUFCNT) ; GET CURRENT BUFFER USED COUNT - CP ACIAB_BUFSZ ; COMPARE TO BUFFER SIZE - JR Z,ACIAB_INT2 ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED + DEC C ; BACK TO CONTROL PORT + LD B,A ; SAVE BYTE READ + LD L,(IY+6) ; SET HL TO + LD H,(IY+7) ; ... START OF BUFFER STRUCT + LD A,(HL) ; GET COUNT + CP ACIA_BUFSZ ; COMPARE TO BUFFER SIZE + JR Z,ACIA_INTRCV4 ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED INC A ; INCREMENT THE COUNT - LD (ACIAB_BUFCNT),A ; AND SAVE IT - CP ACIAB_BUFSZ / 2 ; BUFFER GETTING FULL? - JR NZ,ACIAB_INT0 ; IF NOT, BYPASS DEASSERTING RTS - LD A,ACIA_RTSOFF ; VALUE TO DEASSERT RTS + LD (HL),A ; AND SAVE IT + CP ACIA_BUFSZ / 2 ; BUFFER GETTING FULL? + JR NZ,ACIA_INTRCV2 ; IF NOT, BYPASS CLEARING RTS + LD A,(ACIA_CMD) ; CONFIG BYTE W/O RTS BIT + OR ACIA_RTSOFF ; CLEAR RTS OUT (C),A ; DO IT -ACIAB_INT0: - LD HL,(ACIAB_HD) ; GET HEAD POINTER - LD A,L ; GET LOW BYTE - CP ACIAB_BUFEND & $FF ; PAST END? - JR NZ,ACIAB_INT1 ; IF NOT, BYPASS POINTER RESET - LD HL,ACIAB_BUF ; ... OTHERWISE, RESET TO START OF BUFFER -ACIAB_INT1: - LD A,E ; RECOVER BYTE READ - LD (HL),A ; SAVE RECEIVED BYTE TO HEAD POSITION - INC HL ; INCREMENT HEAD POINTER - LD (ACIAB_HD),HL ; SAVE IT -; -ACIAB_INT2: +ACIA_INTRCV2: + INC HL ; HL NOW HAS ADR OF HEAD PTR + PUSH HL ; SAVE ADR OF HEAD PTR + LD A,(HL) ; DEREFERENCE HL + INC HL + LD H,(HL) + LD L,A ; HL IS NOW ACTUAL HEAD PTR + LD (HL),B ; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD + INC HL ; BUMP HEAD POINTER + POP DE ; RECOVER ADR OF HEAD PTR + LD A,L ; GET LOW BYTE OF HEAD PTR + SUB ACIA_BUFSZ+4 ; SUBTRACT SIZE OF BUFFER AND POINTER + CP E ; IF EQUAL TO START, HEAD PTR IS PAST BUF END + JR NZ,ACIA_INTRCV3 ; IF NOT, BYPASS + LD H,D ; SET HL TO + LD L,E ; ... HEAD PTR ADR + INC HL ; BUMP PAST HEAD PTR + INC HL + INC HL + INC HL ; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START +ACIA_INTRCV3: + EX DE,HL ; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR + LD (HL),E ; SAVE UPDATED HEAD PTR + INC HL + LD (HL),D ; CHECK FOR MORE PENDING... IN A,(C) ; GET STATUS RRA ; READY BIT TO CF - JR C,ACIAB_INT00 ; IF SET, DO SOME MORE + JR C,ACIA_INTRCV1 ; IF SET, DO SOME MORE +ACIA_INTRCV4: OR $FF ; NZ SET TO INDICATE INT HANDLED RET ; AND RETURN ; @@ -247,15 +238,16 @@ ACIAB_INT2: ; DRIVER FUNCTION TABLE ; ACIA_FNTBL: - .DW ACIA_IN - .DW ACIA_OUT - .DW ACIA_IST - .DW ACIA_OST - .DW ACIA_INITDEV - .DW ACIA_QUERY - .DW ACIA_DEVICE + .DW ACIA_IN + .DW ACIA_OUT + .DW ACIA_IST + .DW ACIA_OST + .DW ACIA_INITDEV + .DW ACIA_QUERY + .DW ACIA_DEVICE #IF (($ - ACIA_FNTBL) != (CIO_FNCNT * 2)) - .ECHO "*** INVALID ACIA FUNCTION TABLE ***\n" + .ECHO "*** INVALID ACIA FUNCTION TABLE ***\n" + !!! ; FORCE AN ASSEMBLY ERROR #ENDIF ; ; @@ -263,73 +255,57 @@ ACIA_FNTBL: #IF (INTMODE == 0) ; ACIA_IN: - CALL ACIA_IST ; CHAR WAITING? - JR Z,ACIA_IN ; LOOP IF NOT - LD C,(IY+3) ; C := ACIA BASE PORT - INC C ; BUMP TO DATA PORT - IN E,(C) ; GET BYTE - XOR A ; SIGNAL SUCCESS - RET + CALL ACIA_IST ; CHAR WAITING? + JR Z,ACIA_IN ; LOOP IF NOT + LD C,(IY+3) ; C := ACIA BASE PORT + INC C ; BUMP TO DATA PORT + IN E,(C) ; GET BYTE + XOR A ; SIGNAL SUCCESS + RET ; #ELSE ; ACIA_IN: - LD A,(IY+2) ; GET MODULE ID - OR A ; SET FLAGS - JR Z,ACIAA_IN ; HANDLE MODULE 0 - DEC A ; TEST FOR NEXT - JR Z,ACIAB_IN ; HANDLE MODULE 1 - CALL PANIC ; ELSE FATAL ERROR - RET -; -ACIAA_IN: - CALL ACIAA_IST ; RECEIVED CHAR READY? - JR Z,ACIAA_IN ; LOOP TILL WE HAVE SOMETHING IN BUFFER - HB_DI ; AVOID COLLISION WITH INT HANDLER - LD A,(ACIAA_BUFCNT) ; GET COUNT - DEC A ; DECREMENT COUNT - LD (ACIAA_BUFCNT),A ; SAVE SAVE IT - CP ACIAA_BUFSZ / 4 ; BUFFER LOW THRESHOLD - JR NZ,ACIAA_IN0 ; IF NOT, BYPASS SETTING RTS - LD C,(IY+3) ; C := ACIA CMD PORT - LD A,ACIA_RTSON ; ASSERT RTS - OUT (C),A ; DO IT -ACIAA_IN0: - LD HL,(ACIAA_TL) ; GET BUFFER TAIL POINTER - LD E,(HL) ; GET BYTE - INC HL ; BUMP TAIL POINTER - LD A,L ; GET LOW BYTE - CP ACIAA_BUFEND & $FF ; PAST END? - JR NZ,ACIAA_IN1 ; IF NOT, BYPASS POINTER RESET - LD HL,ACIAA_BUF ; ... OTHERWISE, RESET TO START OF BUFFER -ACIAA_IN1: - LD (ACIAA_TL),HL ; SAVE UPDATED TAIL POINTER - HB_EI ; INTERRUPTS OK AGAIN - XOR A ; SIGNAL SUCCESS - RET ; AND DONE -; -ACIAB_IN: - CALL ACIAB_IST ; RECEIVED CHAR READY? - JR Z,ACIAB_IN ; LOOP TILL WE HAVE SOMETHING IN BUFFER + CALL ACIA_IST ; SEE IF CHAR AVAILABLE + JR Z,ACIA_IN ; LOOP UNTIL SO HB_DI ; AVOID COLLISION WITH INT HANDLER - LD A,(ACIAB_BUFCNT) ; GET COUNT + LD L,(IY+6) ; SET HL TO + LD H,(IY+7) ; ... START OF BUFFER STRUCT + LD A,(HL) ; GET COUNT DEC A ; DECREMENT COUNT - LD (ACIAB_BUFCNT),A ; SAVE SAVE IT - CP ACIAB_BUFSZ / 4 ; BUFFER LOW THRESHOLD - JR NZ,ACIAB_IN0 ; IF NOT, BYPASS SETTING RTS - LD C,(IY+3) ; C := ACIA CMD PORT - LD A,ACIA_RTSON ; ASSERT RTS + LD (HL),A ; SAVE UPDATED COUNT + CP ACIA_BUFSZ / 4 ; BUFFER LOW THRESHOLD + JR NZ,ACIA_IN1 ; IF NOT, BYPASS SETTING RTS + LD C,(IY+3) ; C IS CMD/STATUS PORT ADR + LD A,(ACIA_CMD) ; CONFIG BYTE W/O RTS BIT + OR ACIA_RTSON ; SET RTS OUT (C),A ; DO IT -ACIAB_IN0: - LD HL,(ACIAB_TL) ; GET BUFFER TAIL POINTER - LD E,(HL) ; GET BYTE - INC HL ; BUMP TAIL POINTER - LD A,L ; GET LOW BYTE - CP ACIAB_BUFEND & $FF ; PAST END? - JR NZ,ACIAB_IN1 ; IF NOT, BYPASS POINTER RESET - LD HL,ACIAB_BUF ; ... OTHERWISE, RESET TO START OF BUFFER -ACIAB_IN1: - LD (ACIAB_TL),HL ; SAVE UPDATED TAIL POINTER +ACIA_IN1: + INC HL + INC HL + INC HL ; HL NOW HAS ADR OF TAIL PTR + PUSH HL ; SAVE ADR OF TAIL PTR + LD A,(HL) ; DEREFERENCE HL + INC HL + LD H,(HL) + LD L,A ; HL IS NOW ACTUAL TAIL PTR + LD C,(HL) ; C := CHAR TO BE RETURNED + INC HL ; BUMP TAIL PTR + POP DE ; RECOVER ADR OF TAIL PTR + LD A,L ; GET LOW BYTE OF TAIL PTR + SUB ACIA_BUFSZ+2 ; SUBTRACT SIZE OF BUFFER AND POINTER + CP E ; IF EQUAL TO START, TAIL PTR IS PAST BUF END + JR NZ,ACIA_IN2 ; IF NOT, BYPASS + LD H,D ; SET HL TO + LD L,E ; ... TAIL PTR ADR + INC HL ; BUMP PAST TAIL PTR + INC HL ; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START +ACIA_IN2: + EX DE,HL ; DE := TAIL PTR VAL, HL := ADR OF TAIL PTR + LD (HL),E ; SAVE UPDATED TAIL PTR + INC HL + LD (HL),D + LD E,C ; MOVE CHAR TO RETURN TO E HB_EI ; INTERRUPTS OK AGAIN XOR A ; SIGNAL SUCCESS RET ; AND DONE @@ -339,252 +315,404 @@ ACIAB_IN1: ; ; ACIA_OUT: - CALL ACIA_OST ; READY FOR CHAR? - JR Z,ACIA_OUT ; LOOP IF NOT - LD C,(IY+3) ; C := ACIA CMD PORT - INC C ; BUMP TO DATA PORT - OUT (C),E ; SEND CHAR FROM E - XOR A ; SIGNAL SUCCESS - RET + CALL ACIA_OST ; READY FOR CHAR? + JR Z,ACIA_OUT ; LOOP IF NOT + LD C,(IY+3) ; C := ACIA CMD PORT + INC C ; BUMP TO DATA PORT + OUT (C),E ; SEND CHAR FROM E + XOR A ; SIGNAL SUCCESS + RET ; ; ; #IF (INTMODE == 0) ; ACIA_IST: - LD C,(IY+3) ; STATUS PORT - IN A,(C) ; GET STATUS - AND $01 ; ISOLATE BIT 0 (RX READY) - JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING - XOR A ; ZERO ACCUM - INC A ; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING - RET ; DONE + LD C,(IY+3) ; STATUS PORT + IN A,(C) ; GET STATUS + AND $01 ; ISOLATE BIT 0 (RX READY) + JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING + XOR A ; ZERO ACCUM + INC A ; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING + RET ; DONE ; #ELSE ; ACIA_IST: - LD A,(IY+2) ; GET MODULE ID - OR A ; SET FLAGS - JR Z,ACIAA_IST ; HANDLE MODULE 0 - DEC A ; TEST FOR NEXT - JR Z,ACIAB_IST ; HANDLE MODULE 1 - CALL PANIC ; ELSE FATAL ERROR - RET -; -ACIAA_IST: - LD A,(ACIAA_BUFCNT) ; GET BUFFER UTILIZATION COUNT + LD L,(IY+6) ; GET ADDRESS + LD H,(IY+7) ; ... OF RECEIVE BUFFER + LD A,(HL) ; BUFFER UTILIZATION COUNT OR A ; SET FLAGS JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING - RET ; AND DONE -; -ACIAB_IST: - LD A,(ACIAB_BUFCNT) ; GET BUFFER UTILIZATION COUNT - OR A ; SET FLAGS - JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING - RET ; AND DONE + RET ; #ENDIF ; ; ; ACIA_OST: - LD C,(IY+3) ; CMD PORT - IN A,(C) ; GET STATUS - AND $02 ; ISOLATE BIT 2 (TX EMPTY) - JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING - XOR A ; ZERO ACCUM - INC A ; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION - RET ; DONE + LD C,(IY+3) ; CMD PORT + IN A,(C) ; GET STATUS + AND $02 ; ISOLATE BIT 2 (TX EMPTY) + JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING + XOR A ; ZERO ACCUM + INC A ; ACCUM := 1 TO SIGNAL 1 BUFFER POSITION + RET ; DONE ; ; ; ACIA_INITDEV: - HB_DI ; AVOID CONFLICTS - CALL ACIA_INITDEVX ; DO THE REAL WORK - HB_EI ; INTS BACK ON - RET ; DONE -; -ACIA_INITDEVX: + HB_DI ; AVOID CONFLICTS + CALL ACIA_INITDEVX ; DO THE REAL WORK + HB_EI ; INTS BACK ON + RET ; DONE ; ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! ; - ; PROGRAM THE ACIA CHIP - LD C,(IY+3) ; COMMAND PORT - LD A,$FF ; MASTER RESET - OUT (C),A ; DO IT - LD A,ACIA_RTSON ; NORMAL OPERATION - OUT (C),A ; DO IT +ACIA_INITDEVX: +; +#IF (ACIADEBUG) + CALL NEWLINE + PRTS("ACIA$") + LD A,(IY+2) + CALL PRTDECB + CALL COUT + CALL PC_COLON +#ENDIF +; + ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT) + LD A,D ; TEST DE FOR + AND E ; ... VALUE OF -1 + INC A ; ... SO Z SET IF -1 + JR NZ,ACIA_INITDEV1 ; IF DE == -1, REINIT CURRENT CONFIG +; + ; LOAD EXISTING CONFIG TO REINIT + LD E,(IY+4) ; LOW BYTE + LD D,(IY+5) ; HIGH BYTE +; +ACIA_INITDEV1: +; +#IF (ACIADEBUG) + PUSH DE + POP BC + PRTS(" CFG=$") + CALL PRTHEXWORD +#ENDIF +; + LD A,E ; GET CONFIG LSB + AND $E0 ; CHECK FOR DTR, XON, PARITY=MARK/SPACE + JR NZ,ACIA_INITFAIL ; IF ANY BIT SET, FAIL, NOT SUPPORTED +; + LD A,D ; GET CONFIG MSB + AND $1F ; ISOLATE ENCODED BAUD RATE +; +#IF (ACIADEBUG) + PRTS(" ENC=$") + CALL PRTHEXBYTE +#ENDIF +; + ; BAUD RATE + PUSH DE ; SAVE REQUESTED CONFIG + LD L,(IY+10) ; LOAD CLK FREQ + LD H,(IY+11) ; ... INTO DE:HL + LD E,(IY+12) ; ... " + LD D,(IY+13) ; ... " + LD C,75 ; BAUD RATE ENCODING CONSTANT + CALL ENCODE ; C = TEST BAUD RATE (ENCODED) = BAUDTST + POP DE ; GET REQ CONFIG BACK, D = BAUDREQ +; + ; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH! + LD A,C ; A = BAUDTST + XOR D ; XOR WITH BAUDREQ + BIT 4,A ; DO BIT 4 VALS MATCH? + JR NZ,ACIA_INITFAIL ; IF NOT, BAIL OUT +; + LD A,C ; BAUDTST TO A + AND $0F ; ISOLATE DIV 2 BAUD BITS + LD C,A ; C = BAUDTST +; + LD A,D ; MSB W/ BAUD RATE TO A + AND $0F ; ISOLATE DIV 2 BAUD BITS + LD L,A ; L = BAUDREQ +; + LD A,C ; A = BAUDTST + LD B,%00000000 ; ACIA VAL FOR DIV 1 + CP L ; BAUDTST = BAUDREQ? + JR Z,ACIA_INITBROK ; IF MATCH, WE ARE DONE +; + SUB 4 ; DIVIDE BY 16 (NOW DIV 16 TOT) + JR C,ACIA_INITFAIL ; FAIL IF UNDERFLOW + LD B,%00000001 ; ACIA VAL FOR DIV 16 + CP L ; BAUDTST = BAUDREQ? + JR Z,ACIA_INITBROK ; IF MATCH, WE ARE DONE +; + SUB 2 ; DIVIDE BY 4 (NOW DIV 64 TOT) + JR C,ACIA_INITFAIL ; FAIL IF UNDERFLOW + LD B,%00000010 ; ACIA R4 VAL FOR DIV 32 + CP L ; BAUDTST = BAUDREQ? + JR Z,ACIA_INITBROK ; IF MATCH, WE ARE DONE +; +ACIA_INITFAIL: +; +#IF (ACIADEBUG) + PRTS(" BAD CFG$") +#ENDIF +; + OR $FF + RET ; INVALID CONFIG +; +ACIA_INITBROK: + ; REG B HAS WORKING CONFIG VALUE W/ BAUD RATE BITS + LD C,B ; WORKING VAL TO C + LD A,E ; LSB OF INCOMING CONFIG + AND %00111111 ; ISOLATE LOW 6 BITS TO COMPARE + LD B,8 ; WORD SELECT TABLE SIZE + LD HL,ACIA_WSTBL ; POINT TO TABLE +ACIA_INITWS: + CP (HL) ; MATCH? + JR Z,ACIA_INITWS2 ; IF SO, REG B HAS ACIA VAL + 1 + INC HL ; NEXT ENTRY + DJNZ ACIA_INITWS ; KEEP CHECKING TILL DONE + JR ACIA_INITFAIL ; FAIL IF NO MATCH + +ACIA_WSTBL: + .DB %00001011 ; 8/O/1 + .DB %00011011 ; 8/E/1 + .DB %00000011 ; 8/N/1 + .DB %00000111 ; 8/N/2 + .DB %00001010 ; 7/O/1 + .DB %00011010 ; 7/E/1 + .DB %00001110 ; 7/O/2 + .DB %00011110 ; 7/E/2 + +ACIA_INITWS2: + LD A,B ; PUT FANAL VALUE IN A + DEC A ; ZERO INDEX ADJUSTMENT + RLA ; MOVE BITS TO + RLA ; ... PROPER LOCATION + OR C ; COMBINE WITH WORKING VALUE + JR ACIA_INITGO +; +ACIA_INITSAFE: + LD A,%00010110 ; DEFAULT CONFIG +; +ACIA_INITGO: +; +#IF (INTMODE > 0) + OR %10000000 ; ENABLE RCV INT +#ENDIF +; + LD (ACIA_CMD),A ; SAVE SHADOW REGISTER +; +#IF (ACIADEBUG) + PRTS(" CMD=$") + CALL PRTHEXBYTE + LD DE,65 + CALL VDELAY ; WAIT FOR FINAL CHAR TO SEND +#ENDIF +; + ; PROGRAM THE ACIA CHIP + LD C,(IY+3) ; COMMAND PORT + LD A,$FF ; MASTER RESET + OUT (C),A ; DO IT + LD A,(ACIA_CMD) ; RESTORE CONFIG VALUE + OUT (C),A ; DO IT ; #IF (INTMODE > 0) ; - ; RESET THE RECEIVE BUFFER - LD E,(IY+6) - LD D,(IY+7) ; DE := _CNT - XOR A ; A := 0 - LD (DE),A ; _CNT = 0 - INC DE ; DE := ADR OF _HD - PUSH DE ; SAVE IT - INC DE - INC DE - INC DE - INC DE ; DE := ADR OF _BUF - POP HL ; HL := ADR OF _HD - LD (HL),E - INC HL - LD (HL),D ; _HD := _BUF - INC HL - LD (HL),E - INC HL - LD (HL),D ; _TL := _BUF + ; RESET THE RECEIVE BUFFER + LD E,(IY+6) + LD D,(IY+7) ; DE := _CNT + XOR A ; A := 0 + LD (DE),A ; _CNT = 0 + INC DE ; DE := ADR OF _HD + PUSH DE ; SAVE IT + INC DE + INC DE + INC DE + INC DE ; DE := ADR OF _BUF + POP HL ; HL := ADR OF _HD + LD (HL),E + INC HL + LD (HL),D ; _HD := _BUF + INC HL + LD (HL),E + INC HL + LD (HL),D ; _TL := _BUF ; #ENDIF ; - XOR A ; SIGNAL SUCCESS - RET ; RETURN + XOR A ; SIGNAL SUCCESS + RET ; RETURN ; ; ; ACIA_QUERY: - LD E,(IY+4) ; FIRST CONFIG BYTE TO E - LD D,(IY+5) ; SECOND CONFIG BYTE TO D - XOR A ; SIGNAL SUCCESS - RET ; DONE + LD E,(IY+4) ; FIRST CONFIG BYTE TO E + LD D,(IY+5) ; SECOND CONFIG BYTE TO D + XOR A ; SIGNAL SUCCESS + RET ; DONE ; ; ; ACIA_DEVICE: - LD D,CIODEV_ACIA ; D := DEVICE TYPE - LD E,(IY) ; E := PHYSICAL UNIT - LD C,$00 ; C := DEVICE TYPE, 0x00 IS RS-232 - XOR A ; SIGNAL SUCCESS - RET + LD D,CIODEV_ACIA ; D := DEVICE TYPE + LD E,(IY) ; E := PHYSICAL UNIT + LD C,$00 ; C := DEVICE TYPE, 0x00 IS RS-232 + XOR A ; SIGNAL SUCCESS + RET ; ; ACIA DETECTION ROUTINE ; +; NOTE THAT THE ACIA MODULES ONLY QUALIFY ADDRESS BITS 7 & 6, SO +; THE ACIA'S TWO PORTS APPEAR REPEATEDLY OVER AN ADDRESS RANGE +; OF $40 STARTING FROM THE REAL BASE PORT. +; WE TAKE ADVANTAGE OF THIS TO AVOID CONFLICTING WITH SIO +; AND COMPACT FLASH MODULES DURING DETECTION PROBES. +; ACIA_DETECT: - LD C,(IY+3) ; BASE PORT ADDRESS - CALL ACIA_DETECT2 ; CHECK IT - JR Z,ACIA_DETECT1 ; FOUND IT, RECORD IT - LD A,ACIA_NONE ; NOTHING FOUND - RET ; DONE -; -ACIA_DETECT1: - ; ACIA FOUND, RECORD IT - LD A,ACIA_ACIA ; RETURN CHIP TYPE - RET ; DONE + LD A,(IY+3) ; BASE PORT ADDRESS + ADD A,$20 ; OFFSET (SEE ABOVE) + LD C,A ; PUT IN C FOR I/O + CALL ACIA_DETECT2 ; CHECK IT + JR Z,ACIA_DETECT1 ; FOUND IT, RECORD IT + LD A,ACIA_NONE ; NOTHING FOUND + RET ; DONE +; +ACIA_DETECT1: + ; ACIA FOUND, RECORD IT + LD A,ACIA_ACIA ; RETURN CHIP TYPE + RET ; DONE ; ACIA_DETECT2: - ; LOOK FOR ACIA AT PORT ADDRESS IN C - LD A,$03 ; MASTER RESET - OUT (C),A ; DO IT - IN A,(C) ; GET STATUS - OR A ; CHECK FOR ZERO - RET NZ ; RETURN IF NOT ZERO - LD A,$02 ; CLEAR MASTER RESET - OUT (C),A ; DO IT - ; CHECK FOR EXPECTED BITS: - ; TDRE=1, DCD & CTS = 0 - AND %00001110 ; BIT MASK FOR "STABLE" BITS - CP %00000010 ; EXPECTED VALUE - RET ; RETURN RESULT, Z = CHIP FOUND + ; LOOK FOR ACIA AT PORT ADDRESS IN C + LD A,$03 ; MASTER RESET + OUT (C),A ; DO IT + IN A,(C) ; GET STATUS + OR A ; CHECK FOR ZERO + RET NZ ; RETURN IF NOT ZERO + LD A,$02 ; CLEAR MASTER RESET + OUT (C),A ; DO IT + ; CHECK FOR EXPECTED BITS: + ; TDRE=1, DCD & CTS = 0 + AND %00001110 ; BIT MASK FOR "STABLE" BITS + CP %00000010 ; EXPECTED VALUE + RET ; RETURN RESULT, Z = CHIP FOUND ; ; ; ACIA_PRTCFG: - ; ANNOUNCE PORT - CALL NEWLINE ; FORMATTING - PRTS("ACIA$") ; FORMATTING - LD A,(IY) ; DEVICE NUM - CALL PRTDECB ; PRINT DEVICE NUM - PRTS(": IO=0x$") ; FORMATTING - LD A,(IY+3) ; GET BASE PORT - CALL PRTHEXBYTE ; PRINT BASE PORT + ; ANNOUNCE PORT + CALL NEWLINE ; FORMATTING + PRTS("ACIA$") ; FORMATTING + LD A,(IY) ; DEVICE NUM + CALL PRTDECB ; PRINT DEVICE NUM + PRTS(": IO=0x$") ; FORMATTING + LD A,(IY+3) ; GET BASE PORT + CALL PRTHEXBYTE ; PRINT BASE PORT - ; PRINT THE ACIA TYPE - CALL PC_SPACE ; FORMATTING - LD A,(IY+1) ; GET ACIA TYPE BYTE - RLCA ; MAKE IT A WORD OFFSET - LD HL,ACIA_TYPE_MAP ; POINT HL TO TYPE MAP TABLE - CALL ADDHLA ; HL := ENTRY - LD E,(HL) ; DEREFERENCE - INC HL ; ... - LD D,(HL) ; ... TO GET STRING POINTER - CALL WRITESTR ; PRINT IT -; - ; ALL DONE IF NO ACIA WAS DETECTED - LD A,(IY+1) ; GET ACIA TYPE BYTE - OR A ; SET FLAGS - RET Z ; IF ZERO, NOT PRESENT + ; PRINT THE ACIA TYPE + CALL PC_SPACE ; FORMATTING + LD A,(IY+1) ; GET ACIA TYPE BYTE + RLCA ; MAKE IT A WORD OFFSET + LD HL,ACIA_TYPE_MAP ; POINT HL TO TYPE MAP TABLE + CALL ADDHLA ; HL := ENTRY + LD E,(HL) ; DEREFERENCE + INC HL ; ... + LD D,(HL) ; ... TO GET STRING POINTER + CALL WRITESTR ; PRINT IT ; - PRTS(" MODE=$") ; FORMATTING - LD E,(IY+4) ; LOAD CONFIG - LD D,(IY+5) ; ... WORD TO DE - CALL PS_PRTSC0 ; PRINT CONFIG + ; ALL DONE IF NO ACIA WAS DETECTED + LD A,(IY+1) ; GET ACIA TYPE BYTE + OR A ; SET FLAGS + RET Z ; IF ZERO, NOT PRESENT ; - XOR A - RET + PRTS(" MODE=$") ; FORMATTING + LD E,(IY+4) ; LOAD CONFIG + LD D,(IY+5) ; ... WORD TO DE + CALL PS_PRTSC0 ; PRINT CONFIG +; + XOR A + RET ; ; ; ACIA_TYPE_MAP: - .DW ACIA_STR_NONE - .DW ACIA_STR_ACIA + .DW ACIA_STR_NONE + .DW ACIA_STR_ACIA -ACIA_STR_NONE .DB "$" -ACIA_STR_ACIA .DB "ACIA$" +ACIA_STR_NONE .DB "$" +ACIA_STR_ACIA .DB "ACIA$" ; ; WORKING VARIABLES ; -ACIA_DEV .DB 0 ; DEVICE NUM USED DURING INIT +ACIA_DEV .DB 0 ; DEVICE NUM USED DURING INIT +ACIA_CMD .DB 0 ; COMMAND PORT SHADOW REGISTER ; #IF (INTMODE == 0) ; -ACIAA_RCVBUF .EQU 0 -ACIAB_RCVBUF .EQU 0 +ACIA0_RCVBUF .EQU 0 +ACIA1_RCVBUF .EQU 0 ; #ELSE ; ; RECEIVE BUFFERS ; -ACIAA_RCVBUF: -ACIAA_BUFCNT .DB 0 ; CHARACTERS IN RING BUFFER -ACIAA_HD .DW ACIAA_BUF ; BUFFER HEAD POINTER -ACIAA_TL .DW ACIAA_BUF ; BUFFER TAIL POINTER -ACIAA_INTP .DW ACIAA_INT ; INT HANDLER POINTER -ACIAA_BUF .FILL 32,0 ; RECEIVE RING BUFFER -ACIAA_BUFEND .EQU $ ; END OF BUFFER -ACIAA_BUFSZ .EQU $ - ACIAA_BUF ; SIZE OF RING BUFFER -; -ACIAB_RCVBUF: -ACIAB_BUFCNT .DB 0 ; CHARACTERS IN RING BUFFER -ACIAB_HD .DW ACIAB_BUF ; BUFFER HEAD POINTER -ACIAB_TL .DW ACIAB_BUF ; BUFFER TAIL POINTER -ACIAB_INTP .DW ACIAB_INT ; INT HANDLER POINTER -ACIAB_BUF .FILL 32,0 ; RECEIVE RING BUFFER -ACIAB_BUFEND .EQU $ ; END OF BUFFER -ACIAB_BUFSZ .EQU $ - ACIAB_BUF ; SIZE OF RING BUFFER +ACIA0_RCVBUF: +ACIA0_BUFCNT .DB 0 ; CHARACTERS IN RING BUFFER +ACIA0_HD .DW ACIA0_BUF ; BUFFER HEAD POINTER +ACIA0_TL .DW ACIA0_BUF ; BUFFER TAIL POINTER +ACIA0_BUF .FILL 32,0 ; RECEIVE RING BUFFER +ACIA0_BUFEND .EQU $ ; END OF BUFFER +ACIA0_BUFSZ .EQU $ - ACIA0_BUF ; SIZE OF RING BUFFER +; +#IF (ACIACNT >= 2) +; +ACIA1_RCVBUF: +ACIA1_BUFCNT .DB 0 ; CHARACTERS IN RING BUFFER +ACIA1_HD .DW ACIA1_BUF ; BUFFER HEAD POINTER +ACIA1_TL .DW ACIA1_BUF ; BUFFER TAIL POINTER +ACIA1_BUF .FILL 32,0 ; RECEIVE RING BUFFER +ACIA1_BUFEND .EQU $ ; END OF BUFFER +ACIA1_BUFSZ .EQU $ - ACIA1_BUF ; SIZE OF RING BUFFER +; +#ENDIF ; #ENDIF ; ; ACIA PORT TABLE ; ACIA_CFG: -ACIAA_CFG: - ; ACIA MODULE A CONFIG - .DB 0 ; DEVICE NUMBER (SET DURING INIT) - .DB 0 ; ACIA TYPE (SET DURING INIT) - .DB 0 ; MODULE ID - .DB ACIAA_BASE ; BASE PORT (SET DURING DETECT) - .DW DEFSERCFG ; LINE CONFIGURATION - .DW ACIAA_RCVBUF ; POINTER TO RCV BUFFER STRUCT -ACIAB_CFG: - ; ACIA MODULE B CONFIG - .DB 0 ; DEVICE NUMBER (SET DURING INIT) - .DB 0 ; ACIA TYPE (SET DURING INIT) - .DB 1 ; MODULE ID - .DB ACIAB_BASE ; BASE PORT (SET DURING DETECT) - .DW DEFSERCFG ; LINE CONFIGURATION - .DW ACIAB_RCVBUF ; POINTER TO RCV BUFFER STRUCT -; -ACIA_CNT .EQU ($ - ACIA_CFG) / 8 +; +ACIA0_CFG: + ; ACIA MODULE A CONFIG + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; ACIA TYPE (SET DURING INIT) + .DB 0 ; MODULE ID + .DB ACIA0BASE ; BASE PORT + .DW DEFSERCFG ; LINE CONFIGURATION + .DW ACIA0_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW ACIA0_INT ; INT HANDLER POINTER + .DW (ACIA0CLK / ACIA0DIV) & $FFFF ; CLOCK FREQ AS + .DW (ACIA0CLK / ACIA0DIV) >> 16 ; ... DWORD VALUE +; +ACIA_CFGSIZ .EQU $ - ACIA_CFG ; SIZE OF ONE CFG TABLE ENTRY +; +#IF (ACIACNT >= 2) +; +ACIA1_CFG: + ; ACIA MODULE B CONFIG + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; ACIA TYPE (SET DURING INIT) + .DB 1 ; MODULE ID + .DB ACIA1BASE ; BASE PORT + .DW DEFSERCFG ; LINE CONFIGURATION + .DW ACIA1_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW ACIA1_INT ; INT HANDLER POINTER + .DW (ACIA1CLK / ACIA1DIV) & $FFFF ; CLOCK FREQ AS + .DW (ACIA1CLK / ACIA1DIV) >> 16 ; ... DWORD VALUE +; +#ENDIF +; +ACIA_CFGCNT .EQU ($ - ACIA_CFG) / ACIA_CFGSIZ diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 93785db4..778e6ef5 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -31,17 +31,23 @@ ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ; SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT SIODEBUG .EQU FALSE ; PS -DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 -DEFSIOCLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY -SIOCNT .EQU 1 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) +SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) SIO0MODE .EQU SIOMODE_EZZ80 ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80 -SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP +SIO0ACLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO0BCLK .EQU 1843200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP -DEFSIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ; VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index 933c17e6..fac10b42 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -27,6 +27,10 @@ DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +UARTSBC .EQU FALSE ; ENABLE SBC/ZETA ONBOARD UART DETECTION +UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION +UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION +UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ; diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index 8dc7498d..ab683279 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -27,6 +27,10 @@ DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +UARTSBC .EQU FALSE ; ENABLE SBC/ZETA ONBOARD UART DETECTION +UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION +UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION +UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ; diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index fa6dabf3..f1a9129d 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -29,19 +29,25 @@ UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TR UARTOSC .EQU 1843200 ; UART OSC FREQUENCY ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ; -SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO SUPPORT +SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT SIODEBUG .EQU FALSE ; PS -DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 -DEFSIOCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY -SIOCNT .EQU 1 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) +SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80 -SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP +SIO0ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG +SIO0BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG +SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP -DEFSIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1ACLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1ACFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG +SIO1BCLK .EQU 7372800 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1BCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG ; VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 6beed599..00f84c8f 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -27,21 +27,40 @@ DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT UARTENABLE .EQU FALSE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +; ACIAENABLE .EQU TRUE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT +ACIADEBUG .EQU FALSE ; PS +ACIACNT .EQU 1 ; 1 OR 2 ACIA CHIPS +ACIA0MODE .EQU ACIAMODE_RC ; TYPE OF FIRST ACIA TO DETECT: SIOMODE_RC +ACIA0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST ACIA CHIP +ACIA0CLK .EQU CPUOSC ; 7372800 - ACIA FIXED OSC FREQUENCY +ACIA0DIV .EQU 1 ; 1=RC2014 +ACIA0CFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +ACIA1MODE .EQU ACIAMODE_RC ; TYPE OF SECOND ACIA TO DETECT: SIOMODE_RC +ACIA1BASE .EQU $40 ; IO PORT ADDRESS BASE FOR SECOND ACIA CHIP +ACIA1CLK .EQU CPUOSC ; 7372800 - ACIA FIXED OSC FREQUENCY +ACIA1DIV .EQU 1 ; 1=RC2014 +ACIA1CFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ; SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT SIODEBUG .EQU FALSE ; PS -DEFSIODIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 -DEFSIOCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY SIOCNT .EQU 2 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) SIO0MODE .EQU SIOMODE_RC ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80 -SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO0BASE .EQU $80 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP +SIO0ACLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO0BCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1MODE .EQU SIOMODE_RC ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP -DEFSIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1ACLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1ADIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO1BCLK .EQU CPUOSC ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO1BDIV .EQU 1 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ; VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 1b9079bb..f5e936dd 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -27,21 +27,23 @@ DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +UARTSBC .EQU TRUE ; ENABLE SBC/ZETA ONBOARD UART DETECTION +UARTCAS .EQU TRUE ; ENABLE ECB CASSETTE UART DETECTION +UARTMFP .EQU TRUE ; ENABLE MF/PIC UART DETECTION +UART4 .EQU TRUE ; ENABLE 4UART UART DETECTION ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT ; -SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO SUPPORT +SIOENABLE .EQU TRUE ; TRUE FOR ZILOG SIO SUPPORT SIODEBUG .EQU FALSE ; PS -DEFSIODIV .EQU 8 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 -DEFSIOCLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY SIOCNT .EQU 1 ; 1 OR 2 SIO CHIPS (EACH CHIP HAS 2 CHANNELS) SIO0MODE .EQU SIOMODE_ZP ; TYPE OF FIRST SIO TO DETECT: SIOMODE_RC/SMB/ZP/EZZ80 -;SIO1MODE .EQU SIOMODE_ZP ; TYPE OF SECOND SIO TO DETECT: SIOMODE_RC, SIOMODE_SMB SIO0BASE .EQU $B0 ; IO PORT ADDRESS BASE FOR FIRST SIO CHIP -;SIO1BASE .EQU $84 ; IO PORT ADDRESS BASE FOR SECOND SIO CHIP -DEFSIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -DEFSIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -;DEFSIO1ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG -;DEFSIO1BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO0ACLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0ADIV .EQU 8 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0ACFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG +SIO0BCLK .EQU 4915200 ; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY +SIO0BDIV .EQU 8 ; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5 +SIO0BCFG .EQU DEFSERCFG ; DEFAULT SERIAL LINE CONFIG ; VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT diff --git a/Source/HBIOS/cfg_una.asm b/Source/HBIOS/cfg_una.asm index a451e466..87cd0e8b 100644 --- a/Source/HBIOS/cfg_una.asm +++ b/Source/HBIOS/cfg_una.asm @@ -7,6 +7,7 @@ ; CPUOSC .EQU 18432000 ; CPU OSC FREQ RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!! +INTMODE .EQU 0 ; 0=NONE, 1=INT MODE 1, 2=INT MODE 2 ; DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE) ; diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 3279cbd0..66d480f6 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -27,6 +27,10 @@ DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE) ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE) UARTOSC .EQU 1843200 ; UART OSC FREQUENCY +UARTSBC .EQU TRUE ; ENABLE SBC/ZETA ONBOARD UART DETECTION +UARTCAS .EQU FALSE ; ENABLE ECB CASSETTE UART DETECTION +UARTMFP .EQU FALSE ; ENABLE MF/PIC UART DETECTION +UART4 .EQU FALSE ; ENABLE 4UART UART DETECTION SIOENABLE .EQU FALSE ; TRUE FOR ZILOG SIO/2 SUPPORT SIOMODE .EQU SIOMODE_RC ; SIOMODE_RC, SIOMODE_SMB ACIAENABLE .EQU FALSE ; TRUE FOR MOTOROLA 6850 ACIA SUPPORT diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 619d6bdc..f175ff3e 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -67,10 +67,6 @@ MODCNT .SET MODCNT + 1 ; ; ; -;#IF ((PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180)) -;#DEFINE DIAGPORT $00 -;#ENDIF -; #IF (DIAGENABLE) #DEFINE DIAG(N) PUSH AF #DEFCONT \ LD A,N @@ -266,7 +262,6 @@ HBX_BNKSEL: ; HBX_BNKSEL_INT: ; -;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA)) #IF (MEMMGR == MM_SBC) #IF (INTMODE == 1) ; THIS BIT OF ABSURDITY HANDLES A RARE (BUT FATAL) SITUATION @@ -291,7 +286,6 @@ HBX_ROM: OUT (MPCL_ROM),A ; SET ROM PAGE SELECTOR RET ; DONE #ENDIF -;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80)) #IF (MEMMGR == MM_Z2) BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE @@ -306,7 +300,6 @@ HBX_ROM: OUT (MPGSEL_1),A ; BANK_1: 16K - 32K RET ; DONE #ENDIF -;#IF (PLATFORM == PLT_N8) #IF (MEMMGR == MM_N8) BIT 7,A ; TEST BIT 7 FOR RAM VS. ROM JR Z,HBX_ROM ; IF NOT SET, SELECT ROM PAGE @@ -330,7 +323,6 @@ HBX_ROM: RET ; DONE ; #ENDIF -;#IF (PLATFORM == PLT_MK4) #IF (MEMMGR == MM_Z180) RLCA ; RAM FLAG TO CARRY FLAG AND BIT 0 JR NC,HBX_BNKSEL1 ; IF NC, WANT ROM PAGE, SKIP AHEAD @@ -481,43 +473,43 @@ HBX_STACK .EQU $ ; #IF (INTMODE == 2) ; -; HBIOS INTERRUPT VECTOR TABLE (16 ENTRIES) -; -; # SBC N8,MK4 ZETA ZETA2 -; --- -------------- -------------- -------------- -------------- -; 0 CTC0A Z180/INT1 CTC0A/PRESCL -; 1 CTC0B Z180/INT2 CTC0B/TIMER -; 2 CTC0C Z180/TIM0 CTC0C/UART -; 3 CTC0D Z180/TIM1 CTC0D/FDC -; 4 Z180/DMA0 -; 5 Z180/DMA1 -; 6 Z180/CSIO -; 7 SIO0 Z180/SER0 -; 8 SIO1 Z180/SER1 -; 9 PIO0A PIO0A -; 10 PIO0B PIO0B -; 11 PIO1A PIO1A -; 12 PIO1B PIO1B +; HBIOS INTERRUPT SLOT ASSIGNMENTS +; +; # SBC ZETA N8,MK4,RCZ180 +; --- -------------- -------------- -------------- +; 0 CTC0A Z180/INT1 +; 1 CTC0B Z180/INT2 +; 2 CTC0C Z180/TIM0 +; 3 CTC0D Z180/TIM1 +; 4 Z180/DMA0 +; 5 Z180/DMA1 +; 6 Z180/CSIO +; 7 SIO0A/B Z180/SER0 +; 8 SIO1A/B Z180/SER1 +; 9 PIO0A PIO0A +; 10 PIO0B PIO0B +; 11 PIO1A PIO1A +; 12 PIO1B PIO1B ; 13 ; 14 ; 15 ; 16 ; -; # RCZ80 RCZ180 EZZ80 -; --- -------------- -------------- ------------- -; 0 CTC0A Z180/INT1 CTC0A/SIO0CLK -; 1 CTC0B Z180/INT2 CTC0B/SIO1CLK -; 2 CTC0C Z180/TIM0 CTC0C/PRESCL -; 3 CTC0D Z180/TIM1 CTC0D/TIMER -; 4 Z180/DMA0 -; 5 Z180/DMA1 -; 6 Z180/CSIO -; 7 SIO0 Z180/SER0 SIO0 -; 8 SIO1 Z180/SER1 SIO1 -; 9 PIO0A PIO0A PIO0A -; 10 PIO0B PIO0B PIO0B -; 11 PIO1A PIO1A PIO1A -; 12 PIO1B PIO1B PIO1B +; # RCZ80 EZZ80 ZETA2 +; --- -------------- ------------- -------------- +; 0 CTC0A CTC0A/SIO0CLK CTC0A/PRESCL +; 1 CTC0B CTC0B/SIO1CLK CTC0B/TIMER +; 2 CTC0C CTC0C/PRESCL CTC0C/UART +; 3 CTC0D CTC0D/TIMER CTC0D/FDC +; 4 +; 5 +; 6 +; 7 SIO0A/B SIO0A/B +; 8 SIO1A/B SIO1A/B +; 9 PIO0A PIO0A +; 10 PIO0B PIO0B +; 11 PIO1A PIO1A +; 12 PIO1B PIO1B ; 13 ; 14 ; 15 @@ -570,36 +562,6 @@ INT_IM1: RETI ; UNEXPECTED INT, RET W/ INTS LEFT DISABLED #ENDIF ; -; *** INTERRUPT HANDLER STUBS ARE DEPRECATED!!!! -; NO LONGER NEEDED NOR SUPPORTED -; -; INTERRUPT HANDLER STUBS -; -; THE FOLLOWING INTERRUPT STUBS RECEIVE CONTROL FROM THE -; INTERRUPT, SETUP A HANDLER VECTOR IN HBIOS AND THEN -; BRANCH TO THE COMMON INTERRUPT DISPATCHER -; -;#IF (INTMODE == 2) -;; -;INT_BAD: ; BAD INTERRUPT HANDLER -; PUSH HL ; SAVE HL -; LD HL,HB_BADINT ; HL := INT HANDLER IN BIOS BANK -; JR HBX_INT ; GO TO ROUTING CODE -;; -;INT_TIMER: ; TIMER INTERRUPT HANDLER -; PUSH HL ; SAVE HL -; LD HL,HB_TIMINT ; HL := INT ADR IN BIOS -; JR HBX_INT ; GO TO ROUTING CODE -;; -; #IF (SIOENABLE) -;INT_SIO: ; SIO INTERRUPT HANDLER -; PUSH HL ; SAVE HL -; LD HL,SIO_INT ; HL := SIO INT HANDLER IN BIOS BANK -; JR HBX_INT ; GO TO ROUTING CODE -; #ENDIF -;; -;#ENDIF -; #IF (INTMODE > 0) ; ; COMMON INTERRUPT DISPATCHING CODE @@ -781,7 +743,7 @@ HB_START: ; LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; SET BASE FOR CPU IO REGISTERS LD A,Z180_BASE OUT0 (Z180_ICR),A @@ -805,7 +767,6 @@ HB_START: LD A,$F0 OUT0 (Z180_DCNTL),A -;#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) #IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8)) ; MMU SETUP LD A,$80 @@ -832,7 +793,6 @@ HB_START: #ENDIF ; -;#IF ((PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_RCZ180) | (PLATFORM == PLT_EZZ80)) #IF (MEMMGR == MM_Z2) ; SET PAGING REGISTERS #IFDEF ROMBOOT @@ -987,7 +947,7 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK ; LD HL,0 ; L = 0 MEANS Z80 ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; ; TEST FOR ORIGINAL Z180 USING MLT LD DE,$0506 ; 5 X 6 @@ -997,13 +957,13 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK JR NZ,HB_CPU1 ; IT IS A Z80 IF != 30 INC L ; FLAG Z80180 OR BETTER ; - ; TEST FOR OLDER S-CLASS + ; TEST FOR OLDER S-CLASS (REV K) IN0 A,(Z180_CCR) ; SUPPOSEDLY ONLY ON S-CLASS INC A ; FF -> 0 JR Z,HB_CPU1 INC L ; FLAG Z8S180 REV K (SL1960) OR BETTER ; - ; TEST FOR NEWER S-CLASS + ; TEST FOR NEWER S-CLASS (REV N) OUT0 (Z180_ASTC1L),D ; D = 0 AT THIS POINT IN0 A,(Z180_ASTC1L) ; COUNTER REG INC A ; FF -> 0 @@ -1020,7 +980,7 @@ HB_CPU1: ; CALL HB_CPUSPD ; CPU SPEED DETECTION ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; ; SET DESIRED WAIT STATES LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4) @@ -1057,25 +1017,26 @@ HB_CPU1: ; ; PRE-CONSOLE INITIALIZATION ; - LD A,FORCECON ; CALCULATE PRE-INIT TABLE - RLCA ; ENTRY THAT WE WANT TO - LD DE,(PC_INITTBL) ; EXECUTE FIRST - LD HL,PC_INITTBL - PUSH HL - PUSH DE - PUSH HL - CALL ADDHLA - POP DE ; PLACE IT AT THE TOP OF THE - PUSH HL ; TABLE BY SWAPPING IT - LDI ; WITH THE FIRST (DUMMY) - LDI ; ENTRY - POP HL - POP DE - LD (HL),D + + LD A,FORCECON ; CALCULATE PRE-INIT TABLE ; A IS INDEX OF CONSOLE DEVICE ENTRY + RLCA ; ENTRY THAT WE WANT TO ; A IS OFFSET OF CONSOLE DEVICE ENTRY + LD DE,(PC_INITTBL) ; EXECUTE FIRST ; DE IS VALUE OF TOP ENTRY + LD HL,PC_INITTBL ; HL IS ADDRESS OF TOP OF TABLE + PUSH HL ; PUSH (1) TOP OF TABLE + PUSH DE ; PUSH (2) VALUE OF TOP ENTRY + PUSH HL ; PUSH (3) TOP OF TABLE + CALL ADDHLA ; HL IS ADDRESS OF DESIRED CONSOLE ENTRY + POP DE ; PLACE IT AT THE TOP OF THE ; POP (3) DE IS TOP OF TABLE + PUSH HL ; TABLE BY SWAPPING IT ; PUSH (3) ADDRESS OF DESIRED CONSOLE ENTRY + LDI ; WITH THE FIRST (DUMMY) ; COPY DESIRED ENTRY + LDI ; ENTRY ; ... TO TOP OF TABLE + POP HL ; POP (3) HL IS ADDRESS OF DESIRED CONSOLE ENTRY + POP DE ; POP (2) DE IS VALUE OF ORIGINAL TOP ENTRY + LD (HL),E ; SAVE DE OVER ORIGINAL ENTRY INC HL - LD (HL),E + LD (HL),D LD B,PC_INITTBLLEN - POP DE + POP DE ; POP (1) DE IS ADDRESS OF TOP OF TABLE CALL CALLLIST ; PROCESS THE PRE-INIT CALL TABLE ; #IF 0 @@ -1180,7 +1141,7 @@ PSCNX .EQU $ + 1 LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS LD I,A ; ... AND PLACE IT IN I REGISTER - #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) + #IFDEF CPU_Z180 ; SETUP Z180 IVT XOR A ; SETUP LO BYTE OF IVT ADDRESS OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER @@ -1218,7 +1179,7 @@ PSCNX .EQU $ + 1 ; ; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (HB_IVT01 + 1),HL ; IVT INDEX 1 + LD (IVT(INT_CTC0B)),HL ; IVT ENTRY FOR CTC0B ; ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE @@ -1273,7 +1234,7 @@ PSCNX .EQU $ + 1 ; ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (HB_IVT03 + 1),HL ; IVT INDEX 3 + LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D ; ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE @@ -1313,22 +1274,25 @@ PSCNX .EQU $ + 1 OUT (CTCD),A ; SETUP CTCD LD A,72 ; CTCD TIMER CONSTANT = 72 OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT + #ELSE + .ECHO "*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR #ENDIF + ; #ENDIF ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; #IF (INTMODE == 2) ; ; MASK ALL EXTERNAL INTERRUPTS FOR NOW - ;XOR A ; INT0-2 DISABLED LD A,$01 ; INT0 ENABLED, INT1-2 DISABLED OUT0 (Z180_ITC),A ; WRITE TO INT/TRAP CONTROL REGISTER ; ; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT LD HL,HB_TIMINT - LD (HB_IVT02 + 1),HL ; IVT INDEX 3 + LD (IVT(INT_TIM0)),HL ; Z180 TIMER 0 ; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0 LD HL,(CB_CPUKHZ) ; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ @@ -1390,7 +1354,7 @@ HB_PCPU: CALL PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA PRTS("MHz$") ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 PRTS(" IO=0x$") LD A,Z180_BASE CALL PRTHEXBYTE @@ -1399,7 +1363,7 @@ HB_PCPU: ; DISPLAY CPU CONFIG ; CALL NEWLINE -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 LD A,Z180_MEMWAIT #ELSE LD A,0 @@ -1407,7 +1371,7 @@ HB_PCPU: CALL PRTDECB CALL PRTSTRD .TEXT " MEM W/S, $" -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 LD A,Z180_IOWAIT + 1 #ELSE LD A,1 @@ -2392,7 +2356,7 @@ TEMPCNT .DB 250 ; HB_TIMINT2: ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; ACK/RESET Z180 TIMER INTERRUPT IN0 A,(Z180_TCR) IN0 A,(Z180_TMDR0L) @@ -2846,6 +2810,7 @@ SIZ_UF .EQU $ - ORG_UF #INCLUDE "time.asm" #INCLUDE "bcd.asm" #INCLUDE "decode.asm" +#INCLUDE "encode.asm" ; #IF (WBWDEBUG == USEXIO) #INCLUDE "xio.asm" @@ -2876,7 +2841,7 @@ HB_CPUSPD: RET NZ ; HB_CPUSPD1: -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; USE MEM W/S = 2 AND I/O W/S = 3 FOR TEST IN0 A,(Z180_DCNTL) PUSH AF @@ -2893,7 +2858,7 @@ HB_CPUSPD1: LD (HB_CURSEC),A ; SAVE NEW VALUE CALL HB_WAITSEC ; WAIT FOR SECONDS TICK ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; RESTORE W/S SETTINGS FROM BEFORE TEST POP AF OUT0 (Z180_DCNTL),A @@ -2928,7 +2893,7 @@ HB_WAITSEC: LD DE,0 ; INIT LOOP COUNTER HB_WAITSEC1: ; -#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_RCZ80) | (PLATFORM == PLT_EZZ80)) +#IFDEF CPU_Z80 ; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4 CALL DLY32 CALL DLY16 @@ -2939,7 +2904,7 @@ HB_WAITSEC1: INC HL ; 6 TSTATES #ENDIF ; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) +#IFDEF CPU_Z180 ; LOOP TARGET IS 4000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4 CALL DLY2 ADD IX,BC ; 10 + 4 = 14 TSTATES @@ -3776,8 +3741,7 @@ STR_PLATFORM .DB PLATFORM_NAME, "$" STR_SWITCH .DB "*** Activating CRT Console ***$" STR_BADINT .DB "\r\n*** BAD INT ***\r\n$" ; -#IF (DSKYENABLE) ; 'H','B','I','O',' ','2','9','1' -;MSG_HBVER .DB $BE,$FF,$8A,$FB,$80,$6D,$77,$B0 ; "HBIO 291" +#IF (DSKYENABLE) ; 'H','B','I','O',' ',' ',' ',' ' MSG_HBVER .DB $BE,$FF,$8A,$FB,$80,$80,$80,$80 ; "HBIO " #ENDIF ; diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm index a2fe6d13..9a6abaae 100644 --- a/Source/HBIOS/sio.asm +++ b/Source/HBIOS/sio.asm @@ -16,7 +16,7 @@ ; ; SIO PORT A (COM1:) and SIO PORT B (COM2:) ARE MAPPED TO DEVICE UC1: AND UL1: IN CP/M. ; -SIO_BUFSZ .EQU 32 ; RECEIVE RING BUFFER SIZE +SIO_BUFSZ .EQU 32 ; RECEIVE RING BUFFER SIZE ; SIO_NONE .EQU 0 SIO_SIO .EQU 1 @@ -24,20 +24,19 @@ SIO_SIO .EQU 1 SIO_RTSON .EQU $EA SIO_RTSOFF .EQU $E8 ; -#IF (INTMODE == 2) -; -#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180)) -SIO0_IVT .EQU HB_IVT0D -SIO1_IVT .EQU HB_IVT0E -SIO0_VEC .EQU IVT_SER2 -SIO1_VEC .EQU IVT_SER3 +#IF (INTMODE == 0) +SIO_WR1VAL .EQU $00 ; WR1 VALUE FOR NO INTS #ELSE -SIO0_IVT .EQU HB_IVT07 -SIO1_IVT .EQU HB_IVT08 -SIO0_VEC .EQU IVT_SER0 -SIO1_VEC .EQU IVT_SER1 +SIO_WR1VAL .EQU $18 ; WR1 VALUE FOR INT ON RECEIVED CHARS #ENDIF ; +#IF (INTMODE == 2) +; +SIO0_IVT .EQU IVT(INT_SIO0) +SIO1_IVT .EQU IVT(INT_SIO1) +SIO0_VEC .EQU VEC(INT_SIO0) +SIO1_VEC .EQU VEC(INT_SIO1) +; #ENDIF ; #IF (SIO0MODE == SIOMODE_RC) @@ -100,10 +99,6 @@ SIO1B_DAT .EQU SIO1BASE + $02 ; #ENDIF ; -; CONDITIONALS THAT DETERMINE THE ENCODED VALUE OF THE BAUD RATE -; -#INCLUDE "siobaud.inc" -; SIO_PREINIT: ; ; SETUP THE DISPATCH TABLE ENTRIES @@ -155,11 +150,11 @@ SIO_PREINIT2: #IF (INTMODE == 2) ; SETUP IM2 VECTORS LD HL,SIO_INT0 - LD (SIO0_IVT + 1),HL ; IVT INDEX + LD (SIO0_IVT),HL ; IVT INDEX ; #IF (SIOCNT >= 2) LD HL,SIO_INT1 - LD (SIO1_IVT + 1),HL ; IVT INDEX + LD (SIO1_IVT),HL ; IVT INDEX #ENDIF ; #ENDIF @@ -184,6 +179,13 @@ SIO_INITUNIT: INC (HL) ; INCREMENT IT (FOR NEXT LOOP) LD (IY),A ; UPDATE UNIT NUM + ; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED + ; DUE TO THE CONSTRAINTS OF THE SIO. HERE WE FORCE A GENERIC + ; FAILSAFE CONFIG ONTO THE CHANNEL. IF THE SUBSEQUENT "REAL" + ; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT + ; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG. + CALL SIO_INITSAFE +; ; SET DEFAULT CONFIG LD DE,-1 ; LEAVE CONFIG ALONE ; CALL INITDEVX TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL @@ -294,7 +296,7 @@ SIO_INTRCV2: INC HL ; BUMP HEAD POINTER POP DE ; RECOVER ADR OF HEAD PTR LD A,L ; GET LOW BYTE OF HEAD PTR - ADD A,-SIO_BUFSZ-4 ; SUBTRACT SIZE OF BUFFER AND POINTER + SUB SIO_BUFSZ+4 ; SUBTRACT SIZE OF BUFFER AND POINTER CP E ; IF EQUAL TO START, HEAD PTR IS PAST BUF END JR NZ,SIO_INTRCV3 ; IF NOT, BYPASS LD H,D ; SET HL TO @@ -378,7 +380,7 @@ SIO_IN1: INC HL ; BUMP TAIL PTR POP DE ; RECOVER ADR OF TAIL PTR LD A,L ; GET LOW BYTE OF TAIL PTR - ADD A,-SIO_BUFSZ-2 ; SUBTRACT SIZE OF BUFFER AND POINTER + SUB SIO_BUFSZ+2 ; SUBTRACT SIZE OF BUFFER AND POINTER CP E ; IF EQUAL TO START, TAIL PTR IS PAST BUF END JR NZ,SIO_IN2 ; IF NOT, BYPASS LD H,D ; SET HL TO @@ -468,159 +470,207 @@ SIO_INITDEVX: ; ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! +; +#IF (SIODEBUG) + CALL NEWLINE + PRTS("SIO$") + LD A,(IY+2) + SRL A + CALL PRTDECB + LD A,(IY+2) + AND $01 + ADD A,'A' + CALL COUT + CALL PC_COLON +#ENDIF ; ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT) LD A,D ; TEST DE FOR AND E ; ... VALUE OF -1 INC A ; ... SO Z SET IF -1 - JR NZ,SIO_INITDEV1 ; IF DE == -1, REINIT CURRENT CONFIG + JR NZ,SIO_INITDEV1 ; IF DE == -1, REINIT CURRENT CONFIG ; ; LOAD EXISTING CONFIG TO REINIT LD E,(IY+5) ; LOW BYTE LD D,(IY+6) ; HIGH BYTE ; SIO_INITDEV1: - PUSH DE ; SAVE CONFIG - +; +#IF (SIODEBUG) + PUSH DE + POP BC + PRTS(" CFG=$") + CALL PRTHEXWORD +#ENDIF +; + LD A,E ; GET CONFIG LSB + AND $E0 ; CHECK FOR DTR, XON, PARITY=MARK/SPACE + JR NZ,SIO_INITFAIL ; IF ANY BIT SET, FAIL, NOT SUPPORTED +; LD A,D ; GET CONFIG MSB AND $1F ; ISOLATE ENCODED BAUD RATE - +; #IF (SIODEBUG) - PUSH AF - PRTS(" ENCODE[$") + PRTS(" ENC=$") CALL PRTHEXBYTE - PRTC(']') - POP AF -#ENDIF -; -; ONLY FOUR BAUD RATES ARE POSSIBLE WITH A FIXED CLOCK. -; THESE ARE PREDETERMINED BY HARDWARE SETTINGS AND MATCHING -; CONFIGURATION SETTINGS. WE PRECALCULATED THE FOUR -; POSSIBLE ENCODED VALUES. -; - CP SIOBAUD1 ; We set the divider and the lower bit (d2) of the stop bits - LD D,$04 ; /1 N,8,1 - JR Z,BROK - CP SIOBAUD2 - LD D,$44 ; /16 N,8,1 - JR Z,BROK - CP SIOBAUD3 - LD D,$84 ; /32 N,8,1 - JR Z,BROK - CP SIOBAUD4 - LD D,$C4 ; /64 N,8,1 - JR Z,BROK - +#ENDIF +; + PUSH DE ; SAVE REQUESTED CONFIG + LD L,(IY+9) ; LOAD CLK FREQ + LD H,(IY+10) ; ... INTO DE:HL + LD E,(IY+11) ; ... " + LD D,(IY+12) ; ... " + LD C,75 ; BAUD RATE ENCODING CONSTANT + CALL ENCODE ; C = TEST BAUD RATE (ENCODED) = BAUDTST + POP DE ; GET REQ CONFIG BACK, D = BAUDREQ +; + ; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH! + LD A,C ; A = BAUDTST + XOR D ; XOR WITH BAUDREQ + BIT 4,A ; DO BIT 4 VALS MATCH? + JR NZ,SIO_INITFAIL ; IF NOT, BAIL OUT +; + LD A,C ; BAUDTST TO A + AND $0F ; ISOLATE DIV 2 BAUD BITS + LD C,A ; C = BAUDTST +; + LD A,D ; MSB W/ BAUD RATE TO A + AND $0F ; ISOLATE DIV 2 BAUD BITS + LD L,A ; L = BAUDREQ +; +; PUSH AF ; *DEBUG* +; CALL NEWLINE ; *DEBUG* +; LD A,L ; *DEBUG* +; CALL PRTHEXBYTE ; *DEBUG* +; LD A,C ; *DEBUG* +; CALL PRTHEXBYTE ; *DEBUG* +; CALL NEWLINE ; *DEBUG* +; POP AF ; *DEBUG* +; + LD A,C ; A = BAUDTST + LD B,$04 ; SIO R4 VAL FOR DIV 1 + CP L ; BAUDTST = BAUDREQ? + JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE +; + SUB 4 ; DIVIDE BY 16 (NOW DIV 16 TOT) + JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW + LD B,$44 ; SIO R4 VAL FOR DIV 16 + CP L ; BAUDTST = BAUDREQ? + JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE +; + SUB 1 ; DIVIDE BY 2 (NOW DIV 32 TOT) + JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW + LD B,$84 ; SIO R4 VAL FOR DIV 32 + CP L ; BAUDTST = BAUDREQ? + JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE +; + SUB 1 ; DIVIDE BY 2 (NOW DIV 64 TOT) + JR C,SIO_INITFAIL ; FAIL IF UNDERFLOW + LD B,$C4 ; SIO R4 VAL FOR DIV 64 + CP L ; BAUDTST = BAUDREQ? + JR Z,SIO_INITBROK ; IF MATCH, WE ARE DONE +; +SIO_INITFAIL: +; #IF (SIODEBUG) - PUSH AF - PRTS(" BR FAIL[$") - CALL PRTHEXBYTE - PRTC(']') - POP AF + PRTS(" BAD CFG$") #ENDIF ; -EXITINIT: - POP DE + OR $FF RET ; NZ status here indicating fail / invalid baud rate. - -BROK: - LD A,E - AND $E0 - JR NZ,EXITINIT ; NZ status here indicates dtr, xon, parity mark or space so return - - LD A,E ; set stop bit (d3) and add divider +; +SIO_INITBROK: + LD A,E ; set stop bit (d3) and add divider AND $04 RLA - OR D ; carry gets reset here - LD D,A + OR B ; carry gets reset here + LD L,A ; save in L LD A,E ; get the parity bits SRL A ; move them to bottom two bits SRL A ; we know top bits are zero from previous test SRL A ; add stop bits - OR D ; carry = 0 + OR L ; carry = 0 ; ; SET DIVIDER, STOP AND PARITY WR4 ; - LD BC,SIO_INITVALS+3 - LD (BC),A - -#IF (SIODEBUG) - PUSH AF - PRTS(" WR4[$") - CALL PRTHEXBYTE - PRTC(']') - POP AF -#ENDIF - + LD (SIO_WR4),A +; LD A,E ; 112233445566d1d0 CC RRA ; CC112233445566d1 d0 RRA ; d0CC112233445566 d1 RRA ; d1d0CC1122334455 66 - LD D,A + LD L,A RRA ; 66d1d0CC11223344 55 AND $60 ; 0011110000000000 00 - OR $8a + OR $8A ; ; SET TRANSMIT DATA BITS WR5 ; - LD BC,SIO_INITVALS+11 - LD (BC),A - -#IF (SIODEBUG) - PUSH AF - PRTS(" WR5[$") - CALL PRTHEXBYTE - PRTC(']') - POP AF -#ENDIF + LD (SIO_WR5),A ; ; SET RECEIVE DATA BITS WR3 ; - LD A,D ; DATA BITS + LD A,L ; DATA BITS AND $C0 ; CLEAR OTHER BITS OR $21 ; CTS/DCD AUTO, RX ENABLE - - LD BC,SIO_INITVALS+9 - LD (BC),A - -#IF (SIODEBUG) - PUSH AF - PRTS(" WR3[$") - CALL PRTHEXBYTE - PRTC(']') - POP AF -#ENDIF +; + LD (SIO_WR3),A +; +; SAVE CONFIG PERMANENTLY NOW +; + LD (IY+5),E ; SAVE LOW WORD + LD (IY+6),D ; SAVE HI WORD +; + JR SIO_INITGO ; GO TO SEND INIT +; +; ENTER HERE TO PERFORM A "SAFE" INITIALIZTION. I.E., INIT THE +; CHANNEL USING THE DEFAULT, GENERIC REGISTER VALUES. THIS CAN BE +; USED TO ENSURE INITIALIZATION IF THE FULL CONFIGURATION ABOVE +; FAILS. +; +SIO_INITSAFE: + LD HL,SIO_INITDEFS + LD DE,SIO_INITVALS + LD BC,SIO_INITLEN + LDIR +; +SIO_INITGO: ; ; SET INTERRUPT VECTOR OFFSET WR2 ; #IF (INTMODE == 2) LD A,(IY+2) ; CHIP / CHANNEL SRL A ; SHIFT AWAY CHANNEL BIT - LD E,SIO0_VEC ; ASSUME CHIP 0 - JR Z,SIO_IVT1 ; IF SO, DO IT - LD E,SIO1_VEC ; ASSUME CHIP 1 + LD L,SIO0_VEC ; ASSUME CHIP 0 + JR Z,SIO_INITIVT ; IF SO, DO IT + LD L,SIO1_VEC ; ASSUME CHIP 1 DEC A ; CHIP 1? - JR Z,SIO_IVT1 ; IF SO, TO IT + JR Z,SIO_INITIVT ; IF SO, DO IT CALL PANIC ; IMPOSSIBLE SITUATION -SIO_IVT1: - LD A,E ; VALUE TO A - LD (SIO_INITVALS+7),A ; SAVE IT - +SIO_INITIVT: + LD A,L ; VALUE TO A + LD (SIO_WR2),A ; SAVE IT +; +#ENDIF +; #IF (SIODEBUG) - PUSH AF - PRTS(" WR2[$") + LD HL,SIO_INITVALS + LD B,SIO_INITLEN/2 +SIO_INITPRT: + PRTS(" WR$") + LD A,(HL) CALL PRTHEXBYTE - PRTC(']') - POP AF -#ENDIF - + INC HL + LD A,'=' + CALL COUT + LD A,(HL) + CALL PRTHEXBYTE + INC HL + DJNZ SIO_INITPRT + LD DE,65 + CALL VDELAY ; WAIT FOR FINAL CHAR TO SEND #ENDIF - - POP DE ; RESTORE CONFIG - - LD (IY+5),E ; SAVE LOW WORD - LD (IY+6),D ; SAVE HI WORD ; ; PROGRAM THE SIO CHIP CHANNEL LD C,(IY+3) ; COMMAND PORT @@ -655,20 +705,41 @@ SIO_IVT1: XOR A ; SIGNAL SUCCESS RET ; RETURN ; +; THE SIO IS A LITTLE PRICKLY ABOUT THE ORDER IN WHICH REGSITERS ARE +; WRITTEN DURING CONFIGURATION. THE TABLE BELOW IS USED TO SETUP +; THE REGISTER VALUES AND THEN THE ENTIRE TABLE CAN BE SPIT OUT. ; SIO_INITVALS: - .DB $00, $18 ; WR0: CHANNEL RESET - .DB $04, $00 ; WR4: CLK BAUD PARITY STOP BIT -#IF (INTMODE == 0) - .DB $01, $00 ; WR1: NO INTERRUPTS -#ELSE - .DB $01, $18 ; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS -#ENDIF - .DB $02, IVT_SER0 ; WR2: IM2 INTERRUPT VECTOR OFFSET + .DB $00, $18 ; WR0: CHANNEL RESET CMD +SIO_WR4 .EQU $+1 + .DB $04, $C4 ; WR4: CLK BAUD PARITY STOP BIT +SIO_WR1 .EQU $+1 + .DB $01, SIO_WR1VAL ; WR1: INTERRUPT STYLE +SIO_WR2 .EQU $+1 + .DB $02, $00 ; WR2: IM2 VEC OFFSET, SET DYNAMICALLY +SIO_WR3 .EQU $+1 .DB $03, $E1 ; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE +SIO_WR5 .EQU $+1 .DB $05, SIO_RTSON ; WR5: DTR, 8 BITS SEND, TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc) +; SIO_INITLEN .EQU $ - SIO_INITVALS ; +; THE FOLLOWING TABLE IS A GENERIC, STATIC SET OF CONFIG VALUES THAT CAN +; BE USED TO INITIALIZE THE WORKING TABLE ABOVE. +; +SIO_INITDEFS: + .DB $00, $18 ; WR0: CHANNEL RESET CMD + .DB $04, $C4 ; WR4: CLK BAUD PARITY STOP BIT + .DB $01, SIO_WR1VAL ; WR1: INTERRUPT STYLE + .DB $02, $00 ; WR2: IM2 VEC OFFSET + .DB $03, $E1 ; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE + .DB $05, SIO_RTSON ; WR5: DTR, 8 BITS SEND, TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc) +; +#IF (($ - SIO_INITDEFS) != SIO_INITLEN) + .ECHO "*** ERROR: SIO_INITDEFS TABLE IS NOT THE SAME SIZE AS SIO_INITVALS TABLE!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR +#ENDIF +; ; ; SIO_QUERY: @@ -752,6 +823,8 @@ SIO_RD: RET ; ; SIO DETECTION ROUTINE +; THERE IS ONLY ONE VARIATION OF SIO CHIP, SO HERE WE JUST CHECK THE +; CHIP PRESENCE BITMAP TO SET THE CHIP TYPE OF EITHER NONE OR SIO. ; SIO_DETECT: LD B,(IY+2) ; GET CHIP/CHANNEL @@ -807,8 +880,8 @@ SIO_PRTCFG: ; ; SIO_TYPE_MAP: - .DW SIO_STR_NONE - .DW SIO_STR_SIO + .DW SIO_STR_NONE + .DW SIO_STR_SIO SIO_STR_NONE .DB "$" SIO_STR_SIO .DB "SIO$" @@ -874,8 +947,10 @@ SIO0A_CFG: .DB $00 ; CHIP 0 / CHANNEL A (LOW BIT IS CHANNEL) .DB SIO0A_CMD ; CMD/STATUS PORT .DB SIO0A_DAT ; DATA PORT - .DW DEFSIO0ACFG ; LINE CONFIGURATION + .DW SIO0ACFG ; LINE CONFIGURATION .DW SIO0A_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW (SIO0ACLK / SIO0ADIV) & $FFFF ; CLOCK FREQ AS + .DW (SIO0ACLK / SIO0ADIV) >> 16 ; ... DWORD VALUE ; SIO_CFGSIZ .EQU $ - SIO_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -886,8 +961,10 @@ SIO0B_CFG: .DB $01 ; CHIP 0 / CHANNEL B (LOW BIT IS CHANNEL) .DB SIO0B_CMD ; CMD/STATUS PORT .DB SIO0B_DAT ; DATA PORT - .DW DEFSIO0BCFG ; LINE CONFIGURATION + .DW SIO0BCFG ; LINE CONFIGURATION .DW SIO0B_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW (SIO0BCLK / SIO0BDIV) & $FFFF ; CLOCK FREQ AS + .DW (SIO0BCLK / SIO0BDIV) >> 16 ; ... DWORD VALUE ; #IF (SIOCNT >= 2) ; @@ -898,8 +975,10 @@ SIO1A_CFG: .DB $02 ; CHIP 1 / CHANNEL A (LOW BIT IS CHANNEL) .DB SIO1A_CMD ; CMD/STATUS PORT .DB SIO1A_DAT ; DATA PORT - .DW DEFSIO1ACFG ; LINE CONFIGURATION + .DW SIO1ACFG ; LINE CONFIGURATION .DW SIO1A_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW (SIO1ACLK / SIO1ADIV) & $FFFF ; CLOCK FREQ AS + .DW (SIO1ACLK / SIO1ADIV) >> 16 ; ... DWORD VALUE ; ; SIO1 CHANNEL B SIO1B_CFG: @@ -908,8 +987,10 @@ SIO1B_CFG: .DB $03 ; CHIP 1 / CHANNEL B (LOW BIT IS CHANNEL) .DB SIO1B_CMD ; CMD/STATUS PORT .DB SIO1B_DAT ; DATA PORT - .DW DEFSIO1BCFG ; LINE CONFIGURATION + .DW SIO1BCFG ; LINE CONFIGURATION .DW SIO1B_RCVBUF ; POINTER TO RCV BUFFER STRUCT + .DW (SIO1BCLK / SIO1BDIV) & $FFFF ; CLOCK FREQ AS + .DW (SIO1BCLK / SIO1BDIV) >> 16 ; ... DWORD VALUE ; #ENDIF ; diff --git a/Source/HBIOS/siobaud.inc b/Source/HBIOS/siobaud.inc deleted file mode 100644 index f9c77746..00000000 --- a/Source/HBIOS/siobaud.inc +++ /dev/null @@ -1,393 +0,0 @@ -; -; SIOBAUD1, SIOBAUD2, SIOBAUD3, SIOBAUD4 ARE SET TO THE -; ENCODED VALUE OF EACH POSSIBLE BAUD RATE WITH A FIXED CLOCK. -; - -#IF (DEFSIOCLK/DEFSIODIV/1 == 75) -SIOBAUD1 .EQU 0 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 150) -SIOBAUD1 .EQU 1 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 300) -SIOBAUD1 .EQU 2 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 600) -SIOBAUD1 .EQU 3 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 1200) -SIOBAUD1 .EQU 4 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 2400) -SIOBAUD1 .EQU 5 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 4800) -SIOBAUD1 .EQU 6 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 9600) -SIOBAUD1 .EQU 7 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 19200) -SIOBAUD1 .EQU 8 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 38400) -SIOBAUD1 .EQU 9 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 76800) -SIOBAUD1 .EQU 10 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 153600) -SIOBAUD1 .EQU 11 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 307200) -SIOBAUD1 .EQU 12 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 614400) -SIOBAUD1 .EQU 13 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 ==1228800) -SIOBAUD1 .EQU 14 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 ==2457600) -SIOBAUD1 .EQU 15 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 225) -SIOBAUD1 .EQU 16 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 450) -SIOBAUD1 .EQU 17 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 900) -SIOBAUD1 .EQU 18 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 1800) -SIOBAUD1 .EQU 19 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 3600) -SIOBAUD1 .EQU 20 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 7200) -SIOBAUD1 .EQU 21 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 14400) -SIOBAUD1 .EQU 22 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 28800) -SIOBAUD1 .EQU 23 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 57600) -SIOBAUD1 .EQU 24 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 115200) -SIOBAUD1 .EQU 25 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 230400) -SIOBAUD1 .EQU 26 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 460800) -SIOBAUD1 .EQU 27 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 == 921600) -SIOBAUD1 .EQU 28 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 ==1843200) -SIOBAUD1 .EQU 29 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 ==3686400) -SIOBAUD1 .EQU 30 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/1 ==7372800) -SIOBAUD1 .EQU 31 -#ENDIF - - -#IF (DEFSIOCLK/DEFSIODIV/16 == 75) -SIOBAUD2 .EQU 0 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 150) -SIOBAUD2 .EQU 1 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 300) -SIOBAUD2 .EQU 2 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 600) -SIOBAUD2 .EQU 3 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 1200) -SIOBAUD2 .EQU 4 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 2400) -SIOBAUD2 .EQU 5 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 4800) -SIOBAUD2 .EQU 6 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 9600) -SIOBAUD2 .EQU 7 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 19200) -SIOBAUD2 .EQU 8 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 38400) -SIOBAUD2 .EQU 9 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 76800) -SIOBAUD2 .EQU 10 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 153600) -SIOBAUD2 .EQU 11 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 307200) -SIOBAUD2 .EQU 12 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 614400) -SIOBAUD2 .EQU 13 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 ==1228800) -SIOBAUD2 .EQU 14 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 ==2457600) -SIOBAUD2 .EQU 15 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 225) -SIOBAUD2 .EQU 16 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 450) -SIOBAUD2 .EQU 17 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 900) -SIOBAUD2 .EQU 18 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 1800) -SIOBAUD2 .EQU 19 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 3600) -SIOBAUD2 .EQU 20 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 7200) -SIOBAUD2 .EQU 21 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 14400) -SIOBAUD2 .EQU 22 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 28800) -SIOBAUD2 .EQU 23 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 57600) -SIOBAUD2 .EQU 24 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 115200) -SIOBAUD2 .EQU 25 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 230400) -SIOBAUD2 .EQU 26 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 460800) -SIOBAUD2 .EQU 27 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 == 921600) -SIOBAUD2 .EQU 28 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 ==1843200) -SIOBAUD2 .EQU 29 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 ==3686400) -SIOBAUD2 .EQU 30 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/16 ==7372800) -SIOBAUD2 .EQU 31 -#ENDIF - -#IF (DEFSIOCLK/DEFSIODIV/32== 75) -SIOBAUD3 .EQU 0 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 150) -SIOBAUD3 .EQU 1 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 300) -SIOBAUD3 .EQU 2 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 600) -SIOBAUD3 .EQU 3 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 1200) -SIOBAUD3 .EQU 4 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 2400) -SIOBAUD3 .EQU 5 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 4800) -SIOBAUD3 .EQU 6 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 9600) -SIOBAUD3 .EQU 7 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 19200) -SIOBAUD3 .EQU 8 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 38400) -SIOBAUD3 .EQU 9 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 76800) -SIOBAUD3 .EQU 10 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 153600) -SIOBAUD3 .EQU 11 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 307200) -SIOBAUD3 .EQU 12 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 614400) -SIOBAUD3 .EQU 13 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32==1228800) -SIOBAUD3 .EQU 14 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32==2457600) -SIOBAUD3 .EQU 15 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 225) -SIOBAUD3 .EQU 16 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 450) -SIOBAUD3 .EQU 17 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 900) -SIOBAUD3 .EQU 18 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 1800) -SIOBAUD3 .EQU 19 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 3600) -SIOBAUD3 .EQU 20 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 7200) -SIOBAUD3 .EQU 21 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 14400) -SIOBAUD3 .EQU 22 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 28800) -SIOBAUD3 .EQU 23 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 57600) -SIOBAUD3 .EQU 24 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 115200) -SIOBAUD3 .EQU 25 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 230400) -SIOBAUD3 .EQU 26 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 460800) -SIOBAUD3 .EQU 27 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32== 921600) -SIOBAUD3 .EQU 28 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32==1843200) -SIOBAUD3 .EQU 29 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32==3686400) -SIOBAUD3 .EQU 30 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/32==7372800) -SIOBAUD3 .EQU 31 -#ENDIF - -#IF (DEFSIOCLK/DEFSIODIV/64== 75) -SIOBAUD4 .EQU 0 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 150) -SIOBAUD4 .EQU 1 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 300) -SIOBAUD4 .EQU 2 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 600) -SIOBAUD4 .EQU 3 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 1200) -SIOBAUD4 .EQU 4 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 2400) -SIOBAUD4 .EQU 5 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 4800) -SIOBAUD4 .EQU 6 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 9600) -SIOBAUD4 .EQU 7 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 19200) -SIOBAUD4 .EQU 8 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 38400) -SIOBAUD4 .EQU 9 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 76800) -SIOBAUD4 .EQU 10 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 153600) -SIOBAUD4 .EQU 11 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 307200) -SIOBAUD4 .EQU 12 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 614400) -SIOBAUD4 .EQU 13 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64==1228800) -SIOBAUD4 .EQU 14 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64==2457600) -SIOBAUD4 .EQU 15 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 225) -SIOBAUD4 .EQU 16 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 450) -SIOBAUD4 .EQU 17 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 900) -SIOBAUD4 .EQU 18 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 1800) -SIOBAUD4 .EQU 19 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 3600) -SIOBAUD4 .EQU 20 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 7200) -SIOBAUD4 .EQU 21 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 14400) -SIOBAUD4 .EQU 22 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 28800) -SIOBAUD4 .EQU 23 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 57600) -SIOBAUD4 .EQU 24 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 115200) -SIOBAUD4 .EQU 25 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 230400) -SIOBAUD4 .EQU 26 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 460800) -SIOBAUD4 .EQU 27 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64== 921600) -SIOBAUD4 .EQU 28 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64==1843200) -SIOBAUD4 .EQU 29 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64==3686400) -SIOBAUD4 .EQU 30 -#ENDIF -#IF (DEFSIOCLK/DEFSIODIV/64==7372800) -SIOBAUD4 .EQU 31 -#ENDIF diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index bf4a9323..257704d6 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -91,6 +91,11 @@ DSRTCMODE_NONE .EQU 0 ; NO DSRTC DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4) DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT ; +; ACIA MODE SELECTIONS +; +ACIAMODE_NONE .EQU 0 +ACIAMODE_RC .EQU 1 ; RC2014 ACIA MODULE (SPENCER OWEN) +; ; SIO MODE SELECTIONS ; SIOMODE_NONE .EQU 0 @@ -192,7 +197,6 @@ SER_BAUD7200 .EQU $15 << 8 SER_BAUD14400 .EQU $16 << 8 SER_BAUD28800 .EQU $17 << 8 SER_BAUD57600 .EQU $18 << 8 - SER_BAUD115200 .EQU $19 << 8 SER_BAUD230400 .EQU $1A << 8 SER_BAUD460800 .EQU $1B << 8 @@ -251,25 +255,6 @@ V80X24B .EQU 4 KBD_US .EQU 0 ; US ENGLISH KBD_DE .EQU 1 ; GERMAN ; -; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE) -; -IVT_INT1 .EQU 0 -IVT_INT2 .EQU 2 -IVT_TIM0 .EQU 4 -IVT_TIM1 .EQU 6 -IVT_DMA0 .EQU 8 -IVT_DMA1 .EQU 10 -IVT_CSIO .EQU 12 -IVT_SER0 .EQU 14 -IVT_SER1 .EQU 16 -IVT_PIO0 .EQU 18 -IVT_PIO1 .EQU 20 -IVT_PIO2 .EQU 22 -IVT_PIO3 .EQU 24 -IVT_SER2 .EQU 26 -IVT_SER3 .EQU 28 -; -; ; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE. ; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC. ; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, @@ -448,6 +433,52 @@ FTH_END .EQU FTH_LOC + FTH_SIZ MON_DSKY .EQU MON_LOC + (0 * 3) ; MONITOR ENTRY (DSKY) MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT) ; +; INTERRUPT MODE 2 SLOT ASSIGNMENTS +; +#IF (INTMODE == 2) + + #IFDEF CPU_Z180 + +; Z180-BASED SYSTEMS + +INT_INT1 .EQU 0 ; Z180 INT 1 +INT_INT2 .EQU 1 ; Z180 INT 2 +INT_TIM0 .EQU 2 ; Z180 TIMER 0 +INT_TIM1 .EQU 3 ; Z180 TIMER 1 +INT_DMA0 .EQU 4 ; Z180 DMA 0 +INT_DMA1 .EQU 5 ; Z180 DMA 1 +INT_CSIO .EQU 6 ; Z180 CSIO +INT_SER0 .EQU 7 ; Z180 SERIAL 0 +INT_SER1 .EQU 8 ; Z180 SERIAL 0 +INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A +INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B +INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A +INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B +INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B +INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B + + #ELSE + +; Z80-BASED SYSTEMS + +INT_CTC0A .EQU 0 ; ZILOG CTC #0, CHANNEL A +INT_CTC0B .EQU 1 ; ZILOG CTC #0, CHANNEL B +INT_CTC0C .EQU 2 ; ZILOG CTC #0, CHANNEL C +INT_CTC0D .EQU 3 ; ZILOG CTC #0, CHANNEL D +INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B +INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B +INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A +INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B +INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A +INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B + + #ENDIF + +#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1 +#DEFINE VEC(INTX) INTX*2 + +#ENDIF +; ; HELPER MACROS ; #DEFINE PRTC(C) CALL PRTCH \ .DB C ; PRINT CHARACTER C TO CONSOLE - PRTC('X') diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm index 565511b7..863ab52a 100644 --- a/Source/HBIOS/uart.asm +++ b/Source/HBIOS/uart.asm @@ -569,7 +569,8 @@ UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT ; UART PORT TABLE ; UART_CFG: -#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2)) +;#IF ((PLATFORM == PLT_SBC) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2)) +#IF (UARTSBC) ; SBC/ZETA ONBOARD SERIAL PORT .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -578,7 +579,8 @@ UART_CFG: .DW DEFSERCFG ; LINE CONFIGURATION .FILL 2,$FF ; FILLER #ENDIF -#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) +;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) +#IF (UARTCAS) ; CASSETTE INTERFACE SERIAL PORT .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -587,7 +589,8 @@ UART_CFG: .DW SER_300_8N1 ; LINE CONFIGURATION .FILL 2,$FF ; FILLER #ENDIF -#IF (PLATFORM == PLT_SBC) +;#IF (PLATFORM == PLT_SBC) +#IF (UARTMFP) ; MF/PIC SERIAL PORT .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -596,7 +599,8 @@ UART_CFG: .DW DEFSERCFG ; LINE CONFIGURATION .FILL 2,$FF ; FILLER #ENDIF -#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) +;#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) +#IF (UART4) ; 4UART SERIAL PORT A .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -604,8 +608,6 @@ UART_CFG: .DB $C0 + UART_LSR ; LINE STATUS PORT (LSR) .DW DEFSERCFG ; LINE CONFIGURATION .FILL 2,$FF ; FILLER -#ENDIF -#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) ; 4UART SERIAL PORT B .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -613,8 +615,6 @@ UART_CFG: .DB $C8 + UART_LSR ; LINE STATUS PORT (LSR) .DW DEFSERCFG ; LINE CONFIGURATION .FILL 2,$FF ; FILLER -#ENDIF -#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) ; 4UART SERIAL PORT C .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -622,8 +622,6 @@ UART_CFG: .DB $D0 + UART_LSR ; LINE STATUS PORT (LSR) .DW DEFSERCFG ; LINE CONFIGURATION .FILL 2,$FF ; FILLER -#ENDIF -#IF (PLATFORM == PLT_SBC) | (PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) ; 4UART SERIAL PORT D .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index 27042a0c..43cecdb0 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.1" +#DEFINE BIOSVER "2.9.2-pre.2" From 56c5710b3fc6b4f62760efd25316d0de70a4515d Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Wed, 7 Aug 2019 12:17:07 -0700 Subject: [PATCH 2/2] Fix DPB selection in ASSIGN --- Doc/ChangeLog.txt | 1 + ReadMe.txt | 2 +- Source/Apps/Assign.asm | 45 +++++++++++++++--------------------------- Source/CBIOS/cbios.asm | 4 ---- Source/CBIOS/ver.inc | 2 +- Source/HBIOS/ver.inc | 2 +- 6 files changed, 20 insertions(+), 36 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 4da46964..1420bbdf 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -6,6 +6,7 @@ Version 2.9.2 - WBW: Support missing pull-up resistors on SPI SD adapter boards (common) - WBW: Support two SIO modules w/ auto-detection - PMS: Support ECB USB-FIFO board +- WBW: Fixed ASSIGN issue with incorrect DPB selection Version 2.9.1 ------------- diff --git a/ReadMe.txt b/ReadMe.txt index f5277665..f60708bf 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -7,7 +7,7 @@ *********************************************************************** Wayne Warthen (wwarthen@gmail.com) -Version 2.9.2-pre.2, 2019-08-04 +Version 2.9.2-pre.3, 2019-08-07 https://www.retrobrewcomputers.org/ RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for diff --git a/Source/Apps/Assign.asm b/Source/Apps/Assign.asm index adb53a13..129de63d 100644 --- a/Source/Apps/Assign.asm +++ b/Source/Apps/Assign.asm @@ -20,6 +20,7 @@ ; Change Log: ; 2016-03-21 [WBW] Updated for HBIOS 2.8 ; 2016-04-08 [WBW] Determine key memory addresses dynamically +; 2019-08-07 [WBW] Fixed DPB selection error ;_______________________________________________________________________________ ; ; ToDo: @@ -529,15 +530,21 @@ makdphuna1: ; handle ram/rom ld e,2 ; otherwise, must be ram drive jr makdph0 ; continue ; -makdphwbw: ; determine appropriate dpb (WBW mode) +makdphwbw: ; determine appropriate dpb (WBW mode, unit number in A) ; + ld c,a ; unit number to C + ld b,$17 ; HBIOS: Report Device Info + rst 08 ; call HBIOS, return w/ device type in D, physical unit in E + ld a,d ; device type to A + cp $00 ; ram/rom? + jr nz,makdph00 ; if not, skip ahead to other types + ld a,e ; physical unit number to A ld e,1 ; assume rom - cp $00+0 ; rom? + cp $00 ; rom? jr z,makdph0 ; yes, jump ahead - ld e,2 ; assume ram - cp $00+1 ; ram? - jr z,makdph0 ; yes, jump ahead - and $F0 ; ignore unit nibble now + ld e,2 ; otherwise ram + jr makdph0 ; jump ahead +makdph00: ld e,6 ; assume floppy cp $10 ; floppy? jr z,makdph0 ; yes, jump ahead @@ -580,27 +587,7 @@ makdph1: dec de ; ... prefix data (cks & als buf sizes) call makdph2 ; handle cks buf, then fall thru for als buf ret nz ; bail out on error - -;makdph2: -; ex de,hl ; point hl to cks/als size adr -; ld c,(hl) ; bc := cks/als size -; inc hl ; ... and bump -; ld b,(hl) ; ... past -; inc hl ; ... cks/als size -; ex de,hl ; bc and hl roles restored -; ld a,b ; check to see -; or c ; ... if bc is zero -; jr z,makdph3 ; if zero, bypass alloc, use zero for address -; call alloc ; alloc bc bytes, address returned in bc -; jp nz,instovf ; handle overflow error -;makdph3: -; ld (hl),c ; save cks/als buf -; inc hl ; ... address in -; ld (hl),b ; ... dph and bump -; inc hl ; ... to next dph entry -; xor a ; signal success -; ret - +; makdph2: ; DE = address of CKS or ALS buf to allocate ; HL = address of field in DPH to get allocated address @@ -1701,10 +1688,10 @@ stack .equ $ ; stack top ; Messages ; indent .db " ",0 -msgban1 .db "ASSIGN v1.0c for RomWBW CP/M 2.2, 21-Apr-2016",0 +msgban1 .db "ASSIGN v1.0d for RomWBW CP/M 2.2, 08-Aug-2019",0 msghb .db " (HBIOS Mode)",0 msgub .db " (UBIOS Mode)",0 -msgban2 .db "Copyright 2016, Wayne Warthen, GNU GPL v3",0 +msgban2 .db "Copyright 2019, Wayne Warthen, GNU GPL v3",0 msguse .db "Usage: ASSIGN D:[=[{D:|[]:[]}]][,...]",13,10 .db " ex. ASSIGN (display all active assignments)",13,10 .db " ASSIGN /? (display version and usage)",13,10 diff --git a/Source/CBIOS/cbios.asm b/Source/CBIOS/cbios.asm index 7dadf2bc..7365c768 100644 --- a/Source/CBIOS/cbios.asm +++ b/Source/CBIOS/cbios.asm @@ -2486,7 +2486,6 @@ DRV_INIT8: ; SLICE CREATION LOOP ; ALLOCATE ENTRY AND FILL IN UNIT, SLICE LD HL,4 ; 4 BYTES PER ENTRY CALL ALLOC ; ALLOCATE SPACE - ;CALL NZ,PANIC ; SHOULD NEVER ERROR HERE CALL C,PANIC ; SHOULD NEVER ERROR HERE LD (HL),D ; SAVE UNIT IN FIRST BYTE OF DRVMAP ENTRY INC HL ; POINT TO NEXT BYTE OF DRVMAP ENTRY @@ -2521,7 +2520,6 @@ DPH_INIT: ADD HL,HL ; ... OF DPH (16) ADD HL,HL ; ... FOR TOTAL SIZE CALL ALLOC ; ALLOCATE THE SPACE - ;CALL NZ,PANIC ; SHOULD NEVER ERROR CALL C,PANIC ; SHOULD NEVER ERROR ; ; SET DPHTOP TO START OF ALLOCATED SPACE @@ -2530,7 +2528,6 @@ DPH_INIT: ; ALLOCATE DIRECTORY BUFFER LD HL,128 ; SIZE OF DIRECTORY BUFFER CALL ALLOC ; ALLOCATE THE SPACE - ;CALL NZ,PANIC ; SHOULD NEVER ERROR CALL C,PANIC ; SHOULD NEVER ERROR LD (DIRBUF),HL ; ... AND SAVE IN DIRBUF ; @@ -2578,7 +2575,6 @@ DPH_INIT1A: ; INVOKE THE DPH BUILD ROUTINE PUSH BC ; SAVE LOOP CONTROL CALL MAKDPH ; MAKE THE DPH AT DE, UNIT IN A - ;CALL NZ,PANIC ; FOR NOW, PANIC ON ANY ERROR POP BC ; RESTORE LOOP CONTROL ; STORE THE DPH POINTER IN DRIVE MAP POP DE ; RESTORE DPH ADDRESS TO DE diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc index 43cecdb0..ac80a848 100644 --- a/Source/CBIOS/ver.inc +++ b/Source/CBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.2" +#DEFINE BIOSVER "2.9.2-pre.3" diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc index 43cecdb0..ac80a848 100644 --- a/Source/HBIOS/ver.inc +++ b/Source/HBIOS/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 9 #DEFINE RUP 2 #DEFINE RTP 0 -#DEFINE BIOSVER "2.9.2-pre.2" +#DEFINE BIOSVER "2.9.2-pre.3"