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Initial RHYOPHYRE Support

pull/289/head v3.1.1-pre.166
Wayne Warthen 4 years ago
parent
e804326d54
commit
f6d0e7fea4
26 changed files with 345 additions and 64 deletions
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  1. 11
      Source/Apps/rtc.asm
  2. 1
      Source/HBIOS/Build.cmd
  3. 2
      Source/HBIOS/Build.ps1
  4. 1
      Source/HBIOS/Build.sh
  5. 45
      Source/HBIOS/Config/RPH_std.asm
  6. 2
      Source/HBIOS/Makefile
  7. 4
      Source/HBIOS/cfg_dyno.asm
  8. 4
      Source/HBIOS/cfg_ezz80.asm
  9. 9
      Source/HBIOS/cfg_master.asm
  10. 4
      Source/HBIOS/cfg_mbc.asm
  11. 4
      Source/HBIOS/cfg_mk4.asm
  12. 4
      Source/HBIOS/cfg_n8.asm
  13. 4
      Source/HBIOS/cfg_rcz180.asm
  14. 4
      Source/HBIOS/cfg_rcz280.asm
  15. 4
      Source/HBIOS/cfg_rcz80.asm
  16. 248
      Source/HBIOS/cfg_rph.asm
  17. 4
      Source/HBIOS/cfg_sbc.asm
  18. 4
      Source/HBIOS/cfg_scz180.asm
  19. 2
      Source/HBIOS/cfg_una.asm
  20. 4
      Source/HBIOS/cfg_zeta.asm
  21. 4
      Source/HBIOS/cfg_zeta2.asm
  22. 32
      Source/HBIOS/hbios.asm
  23. 1
      Source/HBIOS/hbios.inc
  24. 3
      Source/HBIOS/std.asm
  25. 2
      Source/ver.inc
  26. 2
      Source/ver.lib

11
Source/Apps/rtc.asm
View File

@ -29,6 +29,8 @@
; ;
;[2021/07/10] v1.7 Support MBC (AJL) ;[2021/07/10] v1.7 Support MBC (AJL)
; ;
;[2022/03/27] v1.8 Support RHYOPHYRE
;
; Constants ; Constants
; ;
mask_data .EQU %10000000 ; RTC data line mask_data .EQU %10000000 ; RTC data line
@ -46,6 +48,7 @@ PORT_SCZ180 .EQU $0C ; RTC port for SCZ180
PORT_DYNO .EQU $0C ; RTC port for DYNO PORT_DYNO .EQU $0C ; RTC port for DYNO
PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280 PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280
PORT_MBC .EQU $70 ; RTC port for MBC PORT_MBC .EQU $70 ; RTC port for MBC
PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE
BDOS .EQU 5 ; BDOS invocation vector BDOS .EQU 5 ; BDOS invocation vector
@ -1126,6 +1129,11 @@ HINIT:
LD DE,PLT_MBC LD DE,PLT_MBC
CP 13 ; MBC CP 13 ; MBC
JR Z,RTC_INIT2 JR Z,RTC_INIT2
;
LD C,PORT_RPH
LD DE,PLT_RPH
CP 14 ; RHYOPHYRE
JR Z,RTC_INIT2
; ;
; Unknown platform ; Unknown platform
LD DE,PLTERR ; BIOS error message LD DE,PLTERR ; BIOS error message
@ -1622,7 +1630,7 @@ TESTING_BIT_DELAY_OVER:
RTC_HELP_MSG: RTC_HELP_MSG:
.DB 0Ah, 0Dh ; line feed and carriage return .DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "RTC: Version 1.7"
.TEXT "RTC: Version 1.8"
.DB 0Ah, 0Dh ; line feed and carriage return .DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp" .TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp"
.DB 0Ah, 0Dh ; line feed and carriage return .DB 0Ah, 0Dh ; line feed and carriage return
@ -1751,6 +1759,7 @@ PLT_SCZ180 .TEXT ", SC Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$" PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$"
PLT_RCZ280 .TEXT ", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$" PLT_RCZ280 .TEXT ", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$" PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$"
PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$"
; ;
; Generic FOR-NEXT loop algorithm ; Generic FOR-NEXT loop algorithm

1
Source/HBIOS/Build.cmd
View File

@ -211,5 +211,6 @@ call Build EZZ80 std 512 || exit /b
call Build EZZ80 tz80 512 || exit /b call Build EZZ80 tz80 512 || exit /b
call Build DYNO std 512 || exit /b call Build DYNO std 512 || exit /b
call Build UNA std 512 || exit /b call Build UNA std 512 || exit /b
call Build RPH std 512 || exit /b
goto :eof goto :eof

2
Source/HBIOS/Build.ps1
View File

@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
# #
$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA" $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
$PlatformListZ280 = "RCZ280" $PlatformListZ280 = "RCZ280"
# #

1
Source/HBIOS/Build.sh
View File

@ -27,6 +27,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; ROMSIZE="0"; bash Build.sh
ROM_PLATFORM="RPH"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh ROM_PLATFORM="SBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; ROMSIZE="512"; bash Build.sh
ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh ROM_PLATFORM="MBC"; ROM_CONFIG="std"; ROMSIZE="512"; bash Build.sh

45
Source/HBIOS/Config/MBC_ddw.asm → Source/HBIOS/Config/RPH_std.asm
View File

@ -1,6 +1,6 @@
; ;
;================================================================================================== ;==================================================================================================
; MBC CONFIGURATION
; N8 STANDARD CONFIGURATION
;================================================================================================== ;==================================================================================================
; ;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE ; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
@ -22,35 +22,18 @@
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE). ; DIRECTORIES ABOVE THIS ONE).
; ;
#DEFINE PLATFORM_NAME "Multi Board Computer"
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
; ;
#include "cfg_mbc.asm"
;
CPUOSC .EQU 4000000 ; CPU OSC FREQ IN MHZ
;
BATCOND .SET FALSE
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
DSKYENABLE .SET TRUE ; ENABLES DSKY
DSKYMODE .SET DSKYMODE_NG ; DSKY VERTSION: DSKYMODE_[V1|NG]
DSKYOSC .SET 100000
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
;DIAGLVL .EQU DL_VERBOSE
DMAENABLE .EQU TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
INTMODE .SET 2
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT
AY38910ENABLE .EQU TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU CPUOSC / 2 ; DEFAULT TO CPUOSC / 4
AYMODE .EQU AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
#include "cfg_rph.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

2
Source/HBIOS/Makefile
View File

@ -12,7 +12,7 @@ include $(TOOLS)/Makefile.inc
FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm FONTS := font8x11c.asm font8x11u.asm font8x16c.asm font8x16u.asm font8x8c.asm font8x8u.asm fontcgac.asm fontcgau.asm
ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO),)
ifneq ($(findstring $(ROM_PLATFORM), N8 MK4 RCZ180 SCZ180 DYNO RPH),)
TASM=$(BINDIR)/uz80as -t hd64180 TASM=$(BINDIR)/uz80as -t hd64180
endif endif

4
Source/HBIOS/cfg_dyno.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_ezz80.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

9
Source/HBIOS/cfg_master.asm
View File

@ -12,7 +12,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -30,7 +30,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_NONE ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
@ -60,6 +60,11 @@ N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR
N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
; ;
RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
RPH_DEFACR .EQU $00 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR
MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR

4
Source/HBIOS/cfg_mbc.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
; ;

4
Source/HBIOS/cfg_mk4.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
; ;

4
Source/HBIOS/cfg_n8.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
; ;

4
Source/HBIOS/cfg_rcz180.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_rcz280.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)

4
Source/HBIOS/cfg_rcz80.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

248
Source/HBIOS/cfg_rph.asm
View File

@ -0,0 +1,248 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "RHYOPHYRE"
;
#INCLUDE "hbios.inc"
;
PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
RAMLOC .EQU 0 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
;
Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
Z180_TIMER .EQU FALSE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
;
RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR
RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
RPH_DEFACR .EQU $00 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
;
RTCIO .EQU RPH_RTC ; RTC LATCH REGISTER ADR
;
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
;
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
;
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
;
LEDENABLE .EQU FALSE ; ENABLES STATUS LED
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC]
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY
DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG]
DSKYPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF DSKY PPI
DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
;
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
;
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
;
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
;
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
;
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|RC|RCV9958|RCKBD]
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
;
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0BASE .EQU RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
;
CENENABLE .EQU FALSE ; CEN: ENABLE CENTRONICS DRIVER (CEN.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
;
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
SN7CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
SNMODE .EQU SNMODE_NONE ; DRIVER MODE: SNMODE_[NONE|RC2014|VGM]
;
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4
AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)

4
Source/HBIOS/cfg_sbc.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
; ;

4
Source/HBIOS/cfg_scz180.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
; ;

2
Source/HBIOS/cfg_una.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "../UBIOS/ubios.inc" #INCLUDE "../UBIOS/ubios.inc"
; ;
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
; ;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE

4
Source/HBIOS/cfg_zeta.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
; ;

4
Source/HBIOS/cfg_zeta2.asm
View File

@ -15,7 +15,7 @@
; ;
#INCLUDE "hbios.inc" #INCLUDE "hbios.inc"
; ;
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC]
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@ -33,7 +33,7 @@ DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
; ;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED) ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VEREIFICATION (0=DISABLED)
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC]
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

32
Source/HBIOS/hbios.asm
View File

@ -556,6 +556,28 @@ HBX_RAMX:
HBX_MMA .DB 0 ; TEMPORARY STORAGE FOR REG A HBX_MMA .DB 0 ; TEMPORARY STORAGE FOR REG A
#ENDIF #ENDIF
; ;
#IF (MEMMGR == MM_RPH)
BIT 7,A ; TEST BIT 7 FOR RAM VS. ROM
JR Z,HBX_ROM ; IF NOT SET, SELECT ROM PAGE
;
HBX_RAM:
AND %00011111 ; AVOID WRAPPING BITS
RLCA ; SCALE SELECTOR TO
RLCA ; ... GO FROM Z180 4K PAGE SIZE
RLCA ; ... TO DESIRED 32K PAGE SIZE
OUT0 (Z180_BBR),A ; WRITE TO BANK BASE
LD A,RPH_DEFACR | 80H ; SELECT RAM BY SETTING BIT 7
OUT0 (RPH_ACR),A ; ... IN RPH ACR REGISTER
RET ; DONE
;
HBX_ROM:
OR RPH_DEFACR ; COMBINE WITH DEFAULT BITS
OUT0 (RPH_ACR),A ; BANK INDEX TO RPH ACR REGISTER
XOR A ; ZERO ACCUM
OUT0 (Z180_BBR),A ; ZERO BANK BASE
RET ; DONE
#ENDIF
;
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
; Copy Data - Possibly between banks. This resembles CP/M 3, but ; Copy Data - Possibly between banks. This resembles CP/M 3, but
; usage of the HL and DE registers is reversed. ; usage of the HL and DE registers is reversed.
@ -1101,6 +1123,11 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n
OUT0 (N8_ACR),A ; ... REGISTER IS INITIALIZED OUT0 (N8_ACR),A ; ... REGISTER IS INITIALIZED
#ENDIF #ENDIF
; ;
#IF (PLATFORM == PLT_RPH)
LD A,RPH_DEFACR ; ENSURE RPH ACR
OUT0 (RPH_ACR),A ; ... REGISTER IS INITIALIZED
#ENDIF
;
#IF (DIAGENABLE) #IF (DIAGENABLE)
LD A,%00000001 LD A,%00000001
OUT (DIAGPORT),A OUT (DIAGPORT),A
@ -1238,7 +1265,7 @@ Z280_INITZ:
LD A,$F0 LD A,$F0
OUT0 (Z180_DCNTL),A OUT0 (Z180_DCNTL),A
#IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8))
#IF ((MEMMGR == MM_Z180) | (MEMMGR == MM_N8) | (MEMMGR == MM_RPH))
; Z180 MMU SETUP ; Z180 MMU SETUP
LD A,$80 LD A,$80
OUT0 (Z180_CBAR),A ; SETUP FOR 32K/32K BANK CONFIG OUT0 (Z180_CBAR),A ; SETUP FOR 32K/32K BANK CONFIG
@ -2419,6 +2446,9 @@ HB_Z280BUS1:
#ENDIF #ENDIF
#IF (MEMMGR == MM_MBC) #IF (MEMMGR == MM_MBC)
.TEXT "MBC$" .TEXT "MBC$"
#ENDIF
#IF (MEMMGR == MM_RPH)
.TEXT "RPH$"
#ENDIF #ENDIF
CALL PRTSTRD CALL PRTSTRD
.TEXT " MMU$" .TEXT " MMU$"

1
Source/HBIOS/hbios.inc
View File

@ -136,6 +136,7 @@ PLT_SCZ180 .EQU 10 ; SCZ180
PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280 PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280
PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER
PLT_RPH .EQU 14 ; RHYOPHYRE GRAPHICS COMPUTER
; ;
; HBIOS GLOBAL ERROR RETURN VALUES ; HBIOS GLOBAL ERROR RETURN VALUES
; ;

3
Source/HBIOS/std.asm
View File

@ -15,6 +15,7 @@
; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard ; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard
; 12. RCZ280 Z280 CPU on RC2014 or ZZ80MB ; 12. RCZ280 Z280 CPU on RC2014 or ZZ80MB
; 13. MBC Andrew Lynch's Multi Board Computer ; 13. MBC Andrew Lynch's Multi Board Computer
; 14. RPH Andrew Lynch's RHYOPHYRE Graphics Computer
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;
@ -70,6 +71,7 @@ MM_Z180 .EQU 4 ; Z180 NATIVE MEMORY MANAGER
MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER MM_Z280 .EQU 5 ; Z280 NATIVE MEMORY MANAGER
MM_ZRC .EQU 6 ; ZRC BANK SWITCHING MM_ZRC .EQU 6 ; ZRC BANK SWITCHING
MM_MBC .EQU 7 ; MBC MEMORY MANAGER MM_MBC .EQU 7 ; MBC MEMORY MANAGER
MM_RPH .EQU 8 ; Z180 WITH RPH EXTENSIONS
; ;
; BOOT STYLE ; BOOT STYLE
; ;
@ -170,6 +172,7 @@ PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY) PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
PPIDEMODE_RPH .EQU 7 ; RHYOPHYRE (RPH)
; ;
; SD MODE SELECTIONS ; SD MODE SELECTIONS
; ;

2
Source/ver.inc
View File

@ -2,4 +2,4 @@
#DEFINE RMN 1 #DEFINE RMN 1
#DEFINE RUP 1 #DEFINE RUP 1
#DEFINE RTP 0 #DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.165"
#DEFINE BIOSVER "3.1.1-pre.166"

2
Source/ver.lib
View File

@ -3,5 +3,5 @@ rmn equ 1
rup equ 1 rup equ 1
rtp equ 0 rtp equ 0
biosver macro biosver macro
db "3.1.1-pre.165"
db "3.1.1-pre.166"
endm endm

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