mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Fix Bugs
- Initial Z280 work caused some regression.
This commit is contained in:
Wayne Warthen
@@ -26,10 +26,14 @@
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;
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#include "cfg_rcz280.asm"
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;
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CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
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CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ
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;
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INTMODE .SET 1
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;
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Z280_MEMWAIT .SET 0 ; Z280: MEMORY WAIT STATES (0-3)
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Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3)
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;
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UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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@@ -42,6 +42,7 @@ Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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;
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Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3)
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
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;
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N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
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N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
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@@ -37,6 +37,7 @@ MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
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;
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Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3)
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3)
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;
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RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
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;
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@@ -427,10 +427,20 @@ HBX_BNKSEL1:
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;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
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;
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HBX_BNKCPY:
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#IF (INTMODE > 0)
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;LD A,I
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#IF (CPUFAM == CPU_Z280)
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PUSH IY
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PUSH BC
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;LD C,$00
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LD C,Z280_MSR
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;LDCTL IY,(C)
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.DB $FD,$ED,$66
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POP BC
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PUSH IY
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DI
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;PUSH AF
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#ELSE
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LD A,I
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DI
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PUSH AF
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#ENDIF
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LD (HBX_BC_SP),SP ; PUT STACK
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LD SP,HBX_TMPSTK ; ... IN HI MEM
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@@ -461,9 +471,18 @@ HBX_BC_LAST:
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LD SP,$FFFF ; RESTORE STACK
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HBX_BC_SP .EQU $ - 2 ; ... TO ORIGINAL VALUE
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#IF (INTMODE > 0)
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;POP AF
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;JP PO,$+4
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#IF (CPUFAM == CPU_Z280)
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POP IY
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PUSH BC
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;LD C,$00
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LD C,Z280_MSR
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;LDCTL (C),IY
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.DB $FD,$ED,$6E
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POP BC
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POP IY
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#ELSE
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POP AF
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JP PO,$+4
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EI
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#ENDIF
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RET
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@@ -825,17 +844,19 @@ HB_START:
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LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
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;
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#IF (CPUFAM == CPU_Z280)
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;LD C,$12 ; CACHE CONTROL REGISTER
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;LD HL,$0060 ; DISABLE INSTRUCTION CACHE
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;;LDCTL (C),HL ; SET IT (8 BITS)
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;;LD C,$12 ; CACHE CONTROL REGISTER
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;LD C,Z280_CCR ; CACHE CONTROL REGISTER
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;LD HL,$0060 ; DISABLE INSTRUCTION CACHE
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;;LDCTL (C),HL ; SET IT (8 BITS)
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;.DB $ED,$6E
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;;PCACHE ; PURGE ANY REMNANTS OF CACHE
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;.DB $ED,$65
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;
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LD C,$02 ; BUS TIMING AND CONTROL REGISTER
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LD HL,$0033 ; 3 I/O WAIT STATES ADDED
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;LD HL,$00F3 ; 3 I/O W/S & 3 INT ACK W/S
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;LDCTL (C),HL ; SET IT (8 BITS)
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;LD C,$02 ; BUS TIMING AND CONTROL REGISTER
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LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
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LD HL,$0033 ; 3 I/O WAIT STATES ADDED
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;LD HL,$00F3 ; 3 I/O W/S & 3 INT ACK W/S
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;LDCTL (C),HL ; SET IT (8 BITS)
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.DB $ED,$6E
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#ENDIF
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;
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@@ -969,6 +990,7 @@ HB_START:
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LD DE,0
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LD BC,$8000
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CALL HBX_BNKCPY
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;DI
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;
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; TRANSITION TO HBIOS IN RAM BANK
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;
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@@ -1198,15 +1220,15 @@ HB_CPU2:
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;
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z280)
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;
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; Z280 PHI IS OSC / 2
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LD A,(CPUOSC / 2) / 1000000
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LD (CB_CPUMHZ),A
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LD DE,(CPUOSC / 2) / 1000
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LD (CB_CPUKHZ),DE
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;
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#ENDIF
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;#IF (CPUFAM == CPU_Z280)
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;;
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; ; Z280 PHI IS OSC / 2
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; LD A,(CPUOSC / 2) / 1000000
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; LD (CB_CPUMHZ),A
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; LD DE,(CPUOSC / 2) / 1000
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; LD (CB_CPUKHZ),DE
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;;
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;#ENDIF
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;
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DIAG(%00011111)
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;
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@@ -1224,6 +1246,31 @@ HB_CPU2:
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;
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z280)
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;
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LD C,Z280_BTCR ; BUS TIMING AND CONTROL REG
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;LDCTL HL,(C) ; GET IT
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.DB $ED,$66
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LD A,L ; PUT IN A
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AND %00111100 ; CLEAR DC AND I/O FIELDS
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OR Z280_INTWAIT << 6 ; SET INT ACK WAIT STATES
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OR Z280_IOWAIT ; SET I/O WAIT STATES
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LD L,A ; BACK TO L
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;LDCTL (C),HL ; SET IT
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.DB $ED,$6E
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;
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LD C,Z280_BTIR ; BUS TIMING AND INIT REG
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;LDCTL HL,(C) ; GET IT
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.DB $ED,$66
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LD A,L ; PUT IN A
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AND %11110011 ; CLEAR DC AND I/O FIELDS
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OR Z280_MEMWAIT << 2 ; SET LOW MEM WAIT STATES
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LD L,A ; BACK TO L
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;LDCTL (C),HL ; SET IT
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.DB $ED,$6E
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;
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#ENDIF
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;
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#IF (INTMODE == 2)
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; SETUP Z80 IVT AND INT MODE 2
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LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS
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@@ -1483,6 +1530,33 @@ HB_SPDTST:
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CALL PRTHEXBYTE
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z280)
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CALL PRTSTRD
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.TEXT ", BUS @ $"
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LD C,Z280_BTIR ; BUS TIMING AND CTL REG
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;LDCTL HL,(C) ; GET IT
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.DB $ED,$66
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LD A,L ; MOVE TO A
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AND %00000011 ; ISOLATE CS FIELD
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LD HL,(CB_CPUKHZ) ; GET CPU SPEED
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CP %00000001 ; BUS @ 1/1
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JR Z,HB_Z280BUS ; GOT IT, SHOW IT
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SRL H ; DIVIDE
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RR L ; ... BY 2
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CP %00000000 ; BUS @ 1/2
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JR Z,HB_Z280BUS ; GOT IT, SHOW IT
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SRL H ; DIVIDE
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RR L ; ... BY 2
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CP %00000010 ; BUS @ 1/4
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JR Z,HB_Z280BUS ; GOT IT, SHOW IT
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PRTS("???$") ; INVALID VALUE
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JR HB_Z280BUS1 ; CONTINUE
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HB_Z280BUS:
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CALL PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
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HB_Z280BUS1:
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PRTS("MHz$") ; SUFFIX
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#ENDIF
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;
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; DISPLAY CPU CONFIG
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;
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CALL NEWLINE
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@@ -1506,12 +1580,21 @@ HB_SPDTST:
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CALL PRTDECB
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CALL PRTSTRD
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.TEXT " I/O W/S$"
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#IF (CPUFAM == CPU_Z280)
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CALL PRTSTRD
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.TEXT ", $"
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LD A,Z280_INTWAIT
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CALL PRTDECB
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CALL PRTSTRD
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.TEXT " INT W/S$"
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#ENDIF
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#IF (INTMODE > 0)
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CALL PRTSTRD
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.TEXT ", INT MODE $"
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LD A,INTMODE
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CALL PRTDECB
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#ENDIF
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;
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; DISPLAY MEMORY CONFIG
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;
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@@ -1529,19 +1612,25 @@ HB_SPDTST:
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CALL NEWLINE
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PRTS("Z280: $")
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PRTS("MSR=$")
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LD C,$00 ; MASTER STATUS REGISTER
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LD C,Z280_MSR ; MASTER STATUS REGISTER
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;LDTCL HL,(C) ; GET VALUE
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.DB $ED,$66
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CALL PRTHEXWORDHL
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CALL PC_SPACE
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PRTS("BTCR=$")
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LD C,$02 ; BUS TIMING AND CONTROL REGISTER
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LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER
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;LDTCL HL,(C) ; GET VALUE
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.DB $ED,$66
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CALL PRTHEXWORDHL
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CALL PC_SPACE
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PRTS("BTIR=$")
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LD C,Z280_BTIR ; BUS TIMING AND CONTROL REGISTER
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;LDTCL HL,(C) ; GET VALUE
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.DB $ED,$66
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CALL PRTHEXWORDHL
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CALL PC_SPACE
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PRTS("CCR=$")
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LD C,$12 ; CACHE CONTROL REGISTER
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LD C,Z280_CCR ; CACHE CONTROL REGISTER
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;LDTCL HL,(C) ; GET VALUE
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.DB $ED,$66
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CALL PRTHEXWORDHL
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@@ -2840,15 +2929,34 @@ SYS_SETSECS:
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;
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SYS_PEEK:
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#IF (INTMODE == 1)
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;LD A,I
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#IF (CPUFAM == CPU_Z280)
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PUSH IY
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;LD C,$00
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LD C,Z280_MSR
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;LDCTL IY,(C)
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.DB $FD,$ED,$66
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PUSH IY
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DI
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;PUSH AF
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#ELSE
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LD A,I
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DI
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PUSH AF
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#ENDIF
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#ENDIF
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CALL HBX_PEEK ; IMPLEMENTED IN PROXY
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#IF (INTMODE == 1)
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;POP AF
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;JP PO,$+4
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#IF (CPUFAM == CPU_Z280)
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;LD C,$00
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LD C,Z280_MSR
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POP IY
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;LDCTL (C),IY
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.DB $FD,$ED,$6E
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POP IY
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#ELSE
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POP AF
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JP PO,$+4
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EI
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#ENDIF
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#ENDIF
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XOR A
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RET
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@@ -2862,15 +2970,96 @@ SYS_PEEK:
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;
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SYS_POKE:
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#IF (INTMODE == 1)
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;EI
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;
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;LD C,$00
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;.DB $ED,$66
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;CALL PC_SPACE
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;CALL PRTHEXWORDHL
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;
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;CALL PC_SPACE
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;LD A,I
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DI
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;PUSH AF
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;POP HL
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;CALL PRTHEXWORDHL
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;
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;DI
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;
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;LD C,$00
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;.DB $ED,$66
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;CALL PC_SPACE
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;CALL PRTHEXWORDHL
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;
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;CALL PC_SPACE
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;LD A,I
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;PUSH AF
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;POP HL
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;CALL PRTHEXWORDHL
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;
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;
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;
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;
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;OUT (DIAGPORT),A
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;DI
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;HALT
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;
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;;PUSH HL
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;;;LD C,$00
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;;LD C,Z280_MSR
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;;LDCTL HL,(C)
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;;BIT 5,L
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;;POP HL
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;;PUSH AF
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;;DI
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;
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;;POP AF
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;;JP Z,$+4
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;;EI
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;
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;
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;
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;;PUSH IY
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;;;LD C,$00
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;;LD C,Z280_MSR
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;;LDCTL IY,(C)
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;;PUSH IY
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;;DI
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;
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;;;LD C,$00
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;;LD C,Z280_MSR
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;;POP IY
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;;LDCTL (C),IY
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;;POP IY
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#IF (CPUFAM == CPU_Z280)
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PUSH IY
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;LD C,$00
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LD C,Z280_MSR
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;LDCTL IY,(C)
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.DB $FD,$ED,$66
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PUSH IY
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DI
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#ELSE
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LD A,I
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DI
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PUSH AF
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#ENDIF
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#ENDIF
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CALL HBX_POKE ; IMPLEMENTED IN PROXY
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#IF (INTMODE == 1)
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;POP AF
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;JP PO,$+4
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#IF (CPUFAM == CPU_Z280)
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;LD C,$00
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LD C,Z280_MSR
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POP IY
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;LDCTL (C),IY
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.DB $FD,$ED,$6E
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POP IY
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#ELSE
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POP AF
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JP PO,$+4
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EI
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#ENDIF
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#ENDIF
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XOR A
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RET
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@@ -330,6 +330,9 @@ FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
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#IF (CPUFAM == CPU_Z180)
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#INCLUDE "z180.inc"
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#ENDIF
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#IF (CPUFAM == CPU_Z280)
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#INCLUDE "z280.inc"
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#ENDIF
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#ENDIF
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;
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; SETUP DEFAULT CPU SPEED VALUES
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@@ -345,6 +348,9 @@ CPUKHZ .SET CPUKHZ / 2 ; ADJUST FOR HALF SPEED OPERATION
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CPUKHZ .SET CPUKHZ * 2 ; ADJUST FOR DOUBLE SPEED OPERATION
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#ENDIF
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#ENDIF
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#IF (CPUFAM == CPU_Z280)
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CPUKHZ .SET CPUKHZ / 2 ; Z180 PHI IS ALWAYS 1/2 OSC
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#ENDIF
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#ENDIF
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;
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CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ
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13
Source/HBIOS/z280.inc
Normal file
13
Source/HBIOS/z280.inc
Normal file
@@ -0,0 +1,13 @@
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;
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; Z280 REGISTERS
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;
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Z280_MSR .EQU $00 ; MASTER STATUS REG
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Z280_ISR .EQU $16 ; INTERRUPT STATUS REG
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Z280_VPR .EQU $06 ; INT/TRAP VECT PTR REG
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Z280_IOPR .EQU $08 ; I/O PAGE REG
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Z280_BTIR .EQU $FF ; BUS TIMING & INIT REG
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Z280_BTCR .EQU $02 ; BUS TIMING & CONTROL REG
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Z280_SLR .EQU $04 ; STACK LIMIT REG
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Z280_TCR .EQU $10 ; TRAP CONTROL REG
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Z280_CCR .EQU $12 ; CACHE CONTROL REG
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Z280_LAR .EQU $14 ; LOCAL ADDRESS REG
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@@ -2,4 +2,4 @@
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#DEFINE RMN 1
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#DEFINE RUP 1
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#DEFINE RTP 0
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#DEFINE BIOSVER "3.1.1-pre.19"
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#DEFINE BIOSVER "3.1.1-pre.20"
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@@ -3,5 +3,5 @@ rmn equ 1
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rup equ 1
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rtp equ 0
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biosver macro
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db "3.1.1-pre.19"
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db "3.1.1-pre.20"
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endm
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